1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
19 #ifndef CONFIG_NXP_ESBC
20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
22 #define CONFIG_SYS_FSL_PBL_PBI \
23 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SPL_SKIP_RELOCATE
31 #define CONFIG_SPL_COMMON_INIT_DDR
32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
38 #ifdef CONFIG_MTD_RAW_NAND
39 #ifdef CONFIG_NXP_ESBC
40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
42 * HDR would be appended at end of image and copied to DDR along
45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
46 CONFIG_U_BOOT_HDR_SIZE)
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
53 #ifdef CONFIG_TARGET_T1040RDB
54 #define CONFIG_SYS_FSL_PBL_RCW \
55 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
57 #ifdef CONFIG_TARGET_T1042RDB_PI
58 #define CONFIG_SYS_FSL_PBL_RCW \
59 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
61 #ifdef CONFIG_TARGET_T1042RDB
62 #define CONFIG_SYS_FSL_PBL_RCW \
63 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
65 #ifdef CONFIG_TARGET_T1040D4RDB
66 #define CONFIG_SYS_FSL_PBL_RCW \
67 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
69 #ifdef CONFIG_TARGET_T1042D4RDB
70 #define CONFIG_SYS_FSL_PBL_RCW \
71 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
75 #ifdef CONFIG_SPIFLASH
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
77 #define CONFIG_SPL_SPI_FLASH_MINIMAL
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
82 #ifndef CONFIG_SPL_BUILD
83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
85 #ifdef CONFIG_TARGET_T1040RDB
86 #define CONFIG_SYS_FSL_PBL_RCW \
87 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
89 #ifdef CONFIG_TARGET_T1042RDB_PI
90 #define CONFIG_SYS_FSL_PBL_RCW \
91 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
93 #ifdef CONFIG_TARGET_T1042RDB
94 #define CONFIG_SYS_FSL_PBL_RCW \
95 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
97 #ifdef CONFIG_TARGET_T1040D4RDB
98 #define CONFIG_SYS_FSL_PBL_RCW \
99 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
101 #ifdef CONFIG_TARGET_T1042D4RDB
102 #define CONFIG_SYS_FSL_PBL_RCW \
103 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
108 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
109 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
110 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
111 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
112 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
113 #ifndef CONFIG_SPL_BUILD
114 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
116 #ifdef CONFIG_TARGET_T1040RDB
117 #define CONFIG_SYS_FSL_PBL_RCW \
118 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
120 #ifdef CONFIG_TARGET_T1042RDB_PI
121 #define CONFIG_SYS_FSL_PBL_RCW \
122 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
124 #ifdef CONFIG_TARGET_T1042RDB
125 #define CONFIG_SYS_FSL_PBL_RCW \
126 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
128 #ifdef CONFIG_TARGET_T1040D4RDB
129 #define CONFIG_SYS_FSL_PBL_RCW \
130 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
132 #ifdef CONFIG_TARGET_T1042D4RDB
133 #define CONFIG_SYS_FSL_PBL_RCW \
134 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
140 /* High Level Configuration Options */
141 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
143 /* support deep sleep */
144 #define CONFIG_DEEP_SLEEP
146 #ifndef CONFIG_RESET_VECTOR_ADDRESS
147 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
150 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
151 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
152 #define CONFIG_PCIE1 /* PCIE controller 1 */
153 #define CONFIG_PCIE2 /* PCIE controller 2 */
154 #define CONFIG_PCIE3 /* PCIE controller 3 */
155 #define CONFIG_PCIE4 /* PCIE controller 4 */
157 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
159 #if defined(CONFIG_SPIFLASH)
160 #elif defined(CONFIG_MTD_RAW_NAND)
161 #ifdef CONFIG_NXP_ESBC
162 #define CONFIG_RAMBOOT_NAND
163 #define CONFIG_BOOTSCRIPT_COPY_RAM
167 #define CONFIG_SYS_CLK_FREQ 100000000
168 #define CONFIG_DDR_CLK_FREQ 66666666
171 * These can be toggled for performance analysis, otherwise use default.
173 #define CONFIG_SYS_CACHE_STASHING
174 #define CONFIG_BACKSIDE_L2_CACHE
175 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
176 #define CONFIG_BTB /* toggle branch predition */
177 #define CONFIG_DDR_ECC
178 #ifdef CONFIG_DDR_ECC
179 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
180 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
183 #define CONFIG_ENABLE_36BIT_PHYS
186 * Config the L3 Cache as L3 SRAM
188 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
190 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
191 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
192 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
194 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
195 #define CONFIG_SYS_L3_SIZE 256 << 10
196 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
197 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
198 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
199 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
200 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
202 #define CONFIG_SYS_DCSRBAR 0xf0000000
203 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
208 #define CONFIG_VERY_BIG_RAM
209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
210 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
213 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
215 #define CONFIG_DDR_SPD
217 #define CONFIG_SYS_SPD_BUS_NUM 0
218 #define SPD_EEPROM_ADDRESS 0x51
220 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
225 #define CONFIG_SYS_FLASH_BASE 0xe8000000
226 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
228 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
229 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
230 CSPR_PORT_SIZE_16 | \
233 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
238 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
240 /* NOR Flash Timing Params */
241 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
242 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
243 FTIM0_NOR_TEADC(0x5) | \
244 FTIM0_NOR_TEAHC(0x5))
245 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
246 FTIM1_NOR_TRAD_NOR(0x1A) |\
247 FTIM1_NOR_TSEQRAD_NOR(0x13))
248 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
249 FTIM2_NOR_TCH(0x4) | \
250 FTIM2_NOR_TWPH(0x0E) | \
252 #define CONFIG_SYS_NOR_FTIM3 0x0
254 #define CONFIG_SYS_FLASH_QUIET_TEST
255 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
257 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
258 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
259 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
260 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
262 #define CONFIG_SYS_FLASH_EMPTY_INFO
263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
266 #define CPLD_LBMAP_MASK 0x3F
267 #define CPLD_BANK_SEL_MASK 0x07
268 #define CPLD_BANK_OVERRIDE 0x40
269 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
270 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
271 #define CPLD_LBMAP_RESET 0xFF
272 #define CPLD_LBMAP_SHIFT 0x03
274 #if defined(CONFIG_TARGET_T1042RDB_PI)
275 #define CPLD_DIU_SEL_DFP 0x80
276 #elif defined(CONFIG_TARGET_T1042D4RDB)
277 #define CPLD_DIU_SEL_DFP 0xc0
280 #if defined(CONFIG_TARGET_T1040D4RDB)
281 #define CPLD_INT_MASK_ALL 0xFF
282 #define CPLD_INT_MASK_THERM 0x80
283 #define CPLD_INT_MASK_DVI_DFP 0x40
284 #define CPLD_INT_MASK_QSGMII1 0x20
285 #define CPLD_INT_MASK_QSGMII2 0x10
286 #define CPLD_INT_MASK_SGMI1 0x08
287 #define CPLD_INT_MASK_SGMI2 0x04
288 #define CPLD_INT_MASK_TDMR1 0x02
289 #define CPLD_INT_MASK_TDMR2 0x01
292 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
293 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
294 #define CONFIG_SYS_CSPR2_EXT (0xf)
295 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
299 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
300 #define CONFIG_SYS_CSOR2 0x0
301 /* CPLD Timing parameters for IFC CS2 */
302 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
303 FTIM0_GPCM_TEADC(0x0e) | \
304 FTIM0_GPCM_TEAHC(0x0e))
305 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
306 FTIM1_GPCM_TRAD(0x1f))
307 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
308 FTIM2_GPCM_TCH(0x8) | \
309 FTIM2_GPCM_TWP(0x1f))
310 #define CONFIG_SYS_CS2_FTIM3 0x0
312 /* NAND Flash on IFC */
313 #define CONFIG_NAND_FSL_IFC
314 #define CONFIG_SYS_NAND_BASE 0xff800000
315 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
317 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
318 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
319 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
320 | CSPR_MSEL_NAND /* MSEL = NAND */ \
322 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
324 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
325 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
326 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
327 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
328 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
329 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
330 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
332 #define CONFIG_SYS_NAND_ONFI_DETECTION
334 /* ONFI NAND Flash mode0 Timing Params */
335 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
336 FTIM0_NAND_TWP(0x18) | \
337 FTIM0_NAND_TWCHT(0x07) | \
338 FTIM0_NAND_TWH(0x0a))
339 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
340 FTIM1_NAND_TWBE(0x39) | \
341 FTIM1_NAND_TRR(0x0e) | \
342 FTIM1_NAND_TRP(0x18))
343 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
344 FTIM2_NAND_TREH(0x0a) | \
345 FTIM2_NAND_TWHRE(0x1e))
346 #define CONFIG_SYS_NAND_FTIM3 0x0
348 #define CONFIG_SYS_NAND_DDR_LAW 11
349 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
350 #define CONFIG_SYS_MAX_NAND_DEVICE 1
352 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
354 #if defined(CONFIG_MTD_RAW_NAND)
355 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
363 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
372 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
380 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
381 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
382 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
383 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
384 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
385 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
386 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
387 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
390 #ifdef CONFIG_SPL_BUILD
391 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
393 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
396 #if defined(CONFIG_RAMBOOT_PBL)
397 #define CONFIG_SYS_RAMBOOT
400 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
401 #if defined(CONFIG_MTD_RAW_NAND)
402 #define CONFIG_A008044_WORKAROUND
406 #define CONFIG_HWCONFIG
408 /* define to use L1 as initial stack */
409 #define CONFIG_L1_INIT_RAM
410 #define CONFIG_SYS_INIT_RAM_LOCK
411 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
414 /* The assembler doesn't like typecast */
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
416 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
417 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
418 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
420 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
421 GENERATED_GBL_DATA_SIZE)
422 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
424 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
425 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
427 /* Serial Port - controlled on board with jumper J8
431 #define CONFIG_SYS_NS16550_SERIAL
432 #define CONFIG_SYS_NS16550_REG_SIZE 1
433 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
435 #define CONFIG_SYS_BAUDRATE_TABLE \
436 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
438 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
439 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
440 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
441 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
443 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
445 #define CONFIG_FSL_DIU_FB
447 #ifdef CONFIG_FSL_DIU_FB
448 #define CONFIG_FSL_DIU_CH7301
449 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
450 #define CONFIG_VIDEO_LOGO
451 #define CONFIG_VIDEO_BMP_LOGO
456 #ifndef CONFIG_DM_I2C
457 #define CONFIG_SYS_I2C
458 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
459 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
460 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
461 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
462 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
463 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
464 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
465 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
466 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
467 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
468 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
469 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
471 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
472 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
475 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
476 /* I2C bus multiplexer */
477 #define I2C_MUX_PCA_ADDR 0x70
478 #define I2C_MUX_CH_DEFAULT 0x8
480 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
481 defined(CONFIG_TARGET_T1040D4RDB) || \
482 defined(CONFIG_TARGET_T1042D4RDB)
483 /* LDI/DVI Encoder for display */
484 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
485 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
486 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
492 #define CONFIG_RTC_DS1337 1
493 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
496 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
500 * eSPI - Enhanced SPI
505 * Memory space is mapped 1-1, but I/O space must start from 0.
509 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
511 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
512 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
513 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
514 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
517 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
519 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
520 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
521 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
522 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
525 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
527 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
528 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
529 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
530 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
533 /* controller 4, Base address 203000 */
535 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
536 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
537 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
538 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
541 #if !defined(CONFIG_DM_PCI)
542 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
543 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
544 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
545 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
546 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
547 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
548 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
549 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
550 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
551 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
552 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
553 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
554 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
555 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
556 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
557 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
558 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
559 #define CONFIG_PCI_INDIRECT_BRIDGE
561 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
562 #endif /* CONFIG_PCI */
565 #define CONFIG_FSL_SATA_V2
566 #ifdef CONFIG_FSL_SATA_V2
567 #define CONFIG_SYS_SATA_MAX_DEVICE 1
569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
578 #define CONFIG_HAS_FSL_DR_USB
580 #ifdef CONFIG_HAS_FSL_DR_USB
581 #ifdef CONFIG_USB_EHCI_HCD
582 #define CONFIG_USB_EHCI_FSL
583 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
588 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
592 #ifndef CONFIG_NOBQFMAN
593 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
594 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
595 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
596 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
597 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
598 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
599 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
600 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
601 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
602 CONFIG_SYS_BMAN_CENA_SIZE)
603 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
604 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
605 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
606 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
607 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
608 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
609 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
610 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
611 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
612 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
613 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
614 CONFIG_SYS_QMAN_CENA_SIZE)
615 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
616 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
618 #define CONFIG_SYS_DPAA_FMAN
619 #define CONFIG_SYS_DPAA_PME
623 /* Default address of microcode for the Linux Fman driver */
624 #if defined(CONFIG_SPIFLASH)
626 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
627 * env, so we got 0x110000.
629 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
630 #elif defined(CONFIG_SDCARD)
632 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
633 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
634 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
636 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
637 #elif defined(CONFIG_MTD_RAW_NAND)
638 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
640 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
643 #if defined(CONFIG_SPIFLASH)
644 #define CONFIG_SYS_QE_FW_ADDR 0x130000
645 #elif defined(CONFIG_SDCARD)
646 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
647 #elif defined(CONFIG_MTD_RAW_NAND)
648 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
650 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
653 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
654 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
655 #endif /* CONFIG_NOBQFMAN */
657 #ifdef CONFIG_FMAN_ENET
658 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
659 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
660 #elif defined(CONFIG_TARGET_T1040D4RDB)
661 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
662 #elif defined(CONFIG_TARGET_T1042D4RDB)
663 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
664 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
665 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
668 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
669 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
670 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
672 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
673 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
676 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
677 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
678 #define CONFIG_VSC9953
679 #ifdef CONFIG_TARGET_T1040RDB
680 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
681 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
683 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
684 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
688 #define CONFIG_ETHPRIME "FM1@DTSEC4"
694 #define CONFIG_LOADS_ECHO /* echo on for serial download */
695 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
698 * Miscellaneous configurable options
700 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
703 * For booting Linux, the board info and command line data
704 * have to be in the first 64 MB of memory, since this is
705 * the maximum mapped by the Linux kernel during initialization.
707 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
708 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
710 #ifdef CONFIG_CMD_KGDB
711 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
715 * Dynamic MTD Partition support with mtdparts
719 * Environment Configuration
721 #define CONFIG_ROOTPATH "/opt/nfsroot"
722 #define CONFIG_BOOTFILE "uImage"
723 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
725 /* default location for tftp and bootm */
726 #define CONFIG_LOADADDR 1000000
728 #define __USB_PHY_TYPE utmi
729 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
731 #ifdef CONFIG_TARGET_T1040RDB
732 #define FDTFILE "t1040rdb/t1040rdb.dtb"
733 #elif defined(CONFIG_TARGET_T1042RDB_PI)
734 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
735 #elif defined(CONFIG_TARGET_T1042RDB)
736 #define FDTFILE "t1042rdb/t1042rdb.dtb"
737 #elif defined(CONFIG_TARGET_T1040D4RDB)
738 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
739 #elif defined(CONFIG_TARGET_T1042D4RDB)
740 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
743 #ifdef CONFIG_FSL_DIU_FB
744 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
746 #define DIU_ENVIRONMENT
749 #define CONFIG_EXTRA_ENV_SETTINGS \
750 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
751 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
752 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
754 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
755 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
756 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
757 "tftpflash=tftpboot $loadaddr $uboot && " \
758 "protect off $ubootaddr +$filesize && " \
759 "erase $ubootaddr +$filesize && " \
760 "cp.b $loadaddr $ubootaddr $filesize && " \
761 "protect on $ubootaddr +$filesize && " \
762 "cmp.b $loadaddr $ubootaddr $filesize\0" \
763 "consoledev=ttyS0\0" \
764 "ramdiskaddr=2000000\0" \
765 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
766 "fdtaddr=1e00000\0" \
767 "fdtfile=" __stringify(FDTFILE) "\0" \
770 #define CONFIG_LINUX \
771 "setenv bootargs root=/dev/ram rw " \
772 "console=$consoledev,$baudrate $othbootargs;" \
773 "setenv ramdiskaddr 0x02000000;" \
774 "setenv fdtaddr 0x00c00000;" \
775 "setenv loadaddr 0x1000000;" \
776 "bootm $loadaddr $ramdiskaddr $fdtaddr"
778 #define CONFIG_HDBOOT \
779 "setenv bootargs root=/dev/$bdev rw " \
780 "console=$consoledev,$baudrate $othbootargs;" \
781 "tftp $loadaddr $bootfile;" \
782 "tftp $fdtaddr $fdtfile;" \
783 "bootm $loadaddr - $fdtaddr"
785 #define CONFIG_NFSBOOTCOMMAND \
786 "setenv bootargs root=/dev/nfs rw " \
787 "nfsroot=$serverip:$rootpath " \
788 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
789 "console=$consoledev,$baudrate $othbootargs;" \
790 "tftp $loadaddr $bootfile;" \
791 "tftp $fdtaddr $fdtfile;" \
792 "bootm $loadaddr - $fdtaddr"
794 #define CONFIG_RAMBOOTCOMMAND \
795 "setenv bootargs root=/dev/ram rw " \
796 "console=$consoledev,$baudrate $othbootargs;" \
797 "tftp $ramdiskaddr $ramdiskfile;" \
798 "tftp $loadaddr $bootfile;" \
799 "tftp $fdtaddr $fdtfile;" \
800 "bootm $loadaddr $ramdiskaddr $fdtaddr"
802 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
804 #include <asm/fsl_secure_boot.h>
806 #endif /* __CONFIG_H */