1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define RESET_VECTOR_OFFSET 0x27FFC
19 #define BOOT_PAGE_OFFSET 0x27000
21 #ifdef CONFIG_MTD_RAW_NAND
22 #ifdef CONFIG_NXP_ESBC
23 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
25 * HDR would be appended at end of image and copied to DDR along
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
29 CONFIG_U_BOOT_HDR_SIZE)
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
33 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
34 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
35 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
40 #ifdef CONFIG_SPIFLASH
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
42 #define CONFIG_SPL_SPI_FLASH_MINIMAL
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
47 #ifndef CONFIG_SPL_BUILD
48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
53 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
54 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
55 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
56 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
57 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
58 #ifndef CONFIG_SPL_BUILD
59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
65 /* High Level Configuration Options */
66 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
68 #ifndef CONFIG_RESET_VECTOR_ADDRESS
69 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
72 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
73 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
74 #define CONFIG_PCIE1 /* PCIE controller 1 */
75 #define CONFIG_PCIE2 /* PCIE controller 2 */
76 #define CONFIG_PCIE3 /* PCIE controller 3 */
77 #define CONFIG_PCIE4 /* PCIE controller 4 */
79 #if defined(CONFIG_SPIFLASH)
80 #elif defined(CONFIG_MTD_RAW_NAND)
81 #ifdef CONFIG_NXP_ESBC
82 #define CONFIG_RAMBOOT_NAND
83 #define CONFIG_BOOTSCRIPT_COPY_RAM
88 * These can be toggled for performance analysis, otherwise use default.
90 #define CONFIG_SYS_CACHE_STASHING
91 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
93 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
96 #define CONFIG_ENABLE_36BIT_PHYS
99 * Config the L3 Cache as L3 SRAM
101 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
103 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
104 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
105 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
107 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
108 #define CONFIG_SYS_L3_SIZE 256 << 10
109 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
111 #define CONFIG_SYS_DCSRBAR 0xf0000000
112 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
117 #define CONFIG_VERY_BIG_RAM
118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121 #define CONFIG_SYS_SPD_BUS_NUM 0
122 #define SPD_EEPROM_ADDRESS 0x51
124 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
129 #define CONFIG_SYS_FLASH_BASE 0xe8000000
130 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
132 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
133 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
134 CSPR_PORT_SIZE_16 | \
137 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
142 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
144 /* NOR Flash Timing Params */
145 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
146 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
147 FTIM0_NOR_TEADC(0x5) | \
148 FTIM0_NOR_TEAHC(0x5))
149 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
150 FTIM1_NOR_TRAD_NOR(0x1A) |\
151 FTIM1_NOR_TSEQRAD_NOR(0x13))
152 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
153 FTIM2_NOR_TCH(0x4) | \
154 FTIM2_NOR_TWPH(0x0E) | \
156 #define CONFIG_SYS_NOR_FTIM3 0x0
158 #define CONFIG_SYS_FLASH_QUIET_TEST
159 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
161 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
162 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
163 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
165 #define CONFIG_SYS_FLASH_EMPTY_INFO
166 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
169 #define CPLD_LBMAP_MASK 0x3F
170 #define CPLD_BANK_SEL_MASK 0x07
171 #define CPLD_BANK_OVERRIDE 0x40
172 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
173 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
174 #define CPLD_LBMAP_RESET 0xFF
175 #define CPLD_LBMAP_SHIFT 0x03
177 #if defined(CONFIG_TARGET_T1042RDB_PI)
178 #define CPLD_DIU_SEL_DFP 0x80
179 #elif defined(CONFIG_TARGET_T1042D4RDB)
180 #define CPLD_DIU_SEL_DFP 0xc0
183 #if defined(CONFIG_TARGET_T1040D4RDB)
184 #define CPLD_INT_MASK_ALL 0xFF
185 #define CPLD_INT_MASK_THERM 0x80
186 #define CPLD_INT_MASK_DVI_DFP 0x40
187 #define CPLD_INT_MASK_QSGMII1 0x20
188 #define CPLD_INT_MASK_QSGMII2 0x10
189 #define CPLD_INT_MASK_SGMI1 0x08
190 #define CPLD_INT_MASK_SGMI2 0x04
191 #define CPLD_INT_MASK_TDMR1 0x02
192 #define CPLD_INT_MASK_TDMR2 0x01
195 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
196 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
197 #define CONFIG_SYS_CSPR2_EXT (0xf)
198 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
202 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
203 #define CONFIG_SYS_CSOR2 0x0
204 /* CPLD Timing parameters for IFC CS2 */
205 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
206 FTIM0_GPCM_TEADC(0x0e) | \
207 FTIM0_GPCM_TEAHC(0x0e))
208 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
209 FTIM1_GPCM_TRAD(0x1f))
210 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
211 FTIM2_GPCM_TCH(0x8) | \
212 FTIM2_GPCM_TWP(0x1f))
213 #define CONFIG_SYS_CS2_FTIM3 0x0
215 /* NAND Flash on IFC */
216 #define CONFIG_SYS_NAND_BASE 0xff800000
217 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
219 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
220 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
221 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
222 | CSPR_MSEL_NAND /* MSEL = NAND */ \
224 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
226 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
227 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
228 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
229 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
230 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
231 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
232 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
234 /* ONFI NAND Flash mode0 Timing Params */
235 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
236 FTIM0_NAND_TWP(0x18) | \
237 FTIM0_NAND_TWCHT(0x07) | \
238 FTIM0_NAND_TWH(0x0a))
239 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
240 FTIM1_NAND_TWBE(0x39) | \
241 FTIM1_NAND_TRR(0x0e) | \
242 FTIM1_NAND_TRP(0x18))
243 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
244 FTIM2_NAND_TREH(0x0a) | \
245 FTIM2_NAND_TWHRE(0x1e))
246 #define CONFIG_SYS_NAND_FTIM3 0x0
248 #define CONFIG_SYS_NAND_DDR_LAW 11
249 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
250 #define CONFIG_SYS_MAX_NAND_DEVICE 1
252 #if defined(CONFIG_MTD_RAW_NAND)
253 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
254 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
255 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
256 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
257 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
258 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
259 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
260 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
261 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
262 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
263 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
264 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
265 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
266 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
267 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
268 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
271 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
272 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
273 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
278 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
279 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
281 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
282 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
283 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
284 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
285 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
288 #if defined(CONFIG_RAMBOOT_PBL)
289 #define CONFIG_SYS_RAMBOOT
292 #define CONFIG_HWCONFIG
294 /* define to use L1 as initial stack */
295 #define CONFIG_L1_INIT_RAM
296 #define CONFIG_SYS_INIT_RAM_LOCK
297 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
300 /* The assembler doesn't like typecast */
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
302 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
303 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
304 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
306 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
308 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
310 /* Serial Port - controlled on board with jumper J8
314 #define CONFIG_SYS_NS16550_SERIAL
315 #define CONFIG_SYS_NS16550_REG_SIZE 1
316 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
318 #define CONFIG_SYS_BAUDRATE_TABLE \
319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
323 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
324 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
326 /* I2C bus multiplexer */
327 #define I2C_MUX_PCA_ADDR 0x70
328 #define I2C_MUX_CH_DEFAULT 0x8
330 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
331 defined(CONFIG_TARGET_T1040D4RDB) || \
332 defined(CONFIG_TARGET_T1042D4RDB)
333 /* LDI/DVI Encoder for display */
334 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
335 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
336 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
342 #define CONFIG_RTC_DS1337 1
343 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
346 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
350 * eSPI - Enhanced SPI
355 * Memory space is mapped 1-1, but I/O space must start from 0.
359 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
361 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
362 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
363 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
364 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
367 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
369 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
370 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
371 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
372 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
375 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
377 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
378 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
379 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
380 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
383 /* controller 4, Base address 203000 */
385 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
386 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
387 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
388 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
391 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
392 #endif /* CONFIG_PCI */
395 #define CONFIG_FSL_SATA_V2
396 #ifdef CONFIG_FSL_SATA_V2
398 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
399 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
407 #define CONFIG_HAS_FSL_DR_USB
409 #ifdef CONFIG_HAS_FSL_DR_USB
410 #ifdef CONFIG_USB_EHCI_HCD
411 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
416 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
420 #ifndef CONFIG_NOBQFMAN
421 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
422 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
423 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
424 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
425 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
426 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
427 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
428 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
429 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
430 CONFIG_SYS_BMAN_CENA_SIZE)
431 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
432 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
433 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
434 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
435 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
436 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
437 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
438 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
439 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
440 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
441 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
442 CONFIG_SYS_QMAN_CENA_SIZE)
443 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
444 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
446 #define CONFIG_SYS_DPAA_FMAN
447 #define CONFIG_SYS_DPAA_PME
449 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
450 #endif /* CONFIG_NOBQFMAN */
452 #ifdef CONFIG_FMAN_ENET
453 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
454 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
455 #elif defined(CONFIG_TARGET_T1040D4RDB)
456 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
457 #elif defined(CONFIG_TARGET_T1042D4RDB)
458 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
459 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
460 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
463 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
464 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
465 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
467 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
468 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
471 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
472 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
473 #define CONFIG_VSC9953
474 #ifdef CONFIG_TARGET_T1040RDB
475 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
476 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
478 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
479 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
487 #define CONFIG_LOADS_ECHO /* echo on for serial download */
488 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
491 * Miscellaneous configurable options
495 * For booting Linux, the board info and command line data
496 * have to be in the first 64 MB of memory, since this is
497 * the maximum mapped by the Linux kernel during initialization.
499 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
500 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
503 * Dynamic MTD Partition support with mtdparts
507 * Environment Configuration
509 #define CONFIG_ROOTPATH "/opt/nfsroot"
510 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
512 #define __USB_PHY_TYPE utmi
513 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
515 #ifdef CONFIG_TARGET_T1040RDB
516 #define FDTFILE "t1040rdb/t1040rdb.dtb"
517 #elif defined(CONFIG_TARGET_T1042RDB_PI)
518 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
519 #elif defined(CONFIG_TARGET_T1042RDB)
520 #define FDTFILE "t1042rdb/t1042rdb.dtb"
521 #elif defined(CONFIG_TARGET_T1040D4RDB)
522 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
523 #elif defined(CONFIG_TARGET_T1042D4RDB)
524 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
527 #define CONFIG_EXTRA_ENV_SETTINGS \
528 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
529 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
530 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
532 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
533 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
534 "tftpflash=tftpboot $loadaddr $uboot && " \
535 "protect off $ubootaddr +$filesize && " \
536 "erase $ubootaddr +$filesize && " \
537 "cp.b $loadaddr $ubootaddr $filesize && " \
538 "protect on $ubootaddr +$filesize && " \
539 "cmp.b $loadaddr $ubootaddr $filesize\0" \
540 "consoledev=ttyS0\0" \
541 "ramdiskaddr=2000000\0" \
542 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
543 "fdtaddr=1e00000\0" \
544 "fdtfile=" __stringify(FDTFILE) "\0" \
547 #include <asm/fsl_secure_boot.h>
549 #endif /* __CONFIG_H */