1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
19 #ifndef CONFIG_NXP_ESBC
20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
22 #define CONFIG_SYS_FSL_PBL_PBI \
23 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SPL_SKIP_RELOCATE
31 #define CONFIG_SPL_COMMON_INIT_DDR
32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
38 #ifdef CONFIG_MTD_RAW_NAND
39 #ifdef CONFIG_NXP_ESBC
40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
42 * HDR would be appended at end of image and copied to DDR along
45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
46 CONFIG_U_BOOT_HDR_SIZE)
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
53 #ifdef CONFIG_TARGET_T1040RDB
54 #define CONFIG_SYS_FSL_PBL_RCW \
55 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
57 #ifdef CONFIG_TARGET_T1042RDB_PI
58 #define CONFIG_SYS_FSL_PBL_RCW \
59 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
61 #ifdef CONFIG_TARGET_T1042RDB
62 #define CONFIG_SYS_FSL_PBL_RCW \
63 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
65 #ifdef CONFIG_TARGET_T1040D4RDB
66 #define CONFIG_SYS_FSL_PBL_RCW \
67 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
69 #ifdef CONFIG_TARGET_T1042D4RDB
70 #define CONFIG_SYS_FSL_PBL_RCW \
71 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
75 #ifdef CONFIG_SPIFLASH
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
77 #define CONFIG_SPL_SPI_FLASH_MINIMAL
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
82 #ifndef CONFIG_SPL_BUILD
83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
85 #ifdef CONFIG_TARGET_T1040RDB
86 #define CONFIG_SYS_FSL_PBL_RCW \
87 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
89 #ifdef CONFIG_TARGET_T1042RDB_PI
90 #define CONFIG_SYS_FSL_PBL_RCW \
91 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
93 #ifdef CONFIG_TARGET_T1042RDB
94 #define CONFIG_SYS_FSL_PBL_RCW \
95 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
97 #ifdef CONFIG_TARGET_T1040D4RDB
98 #define CONFIG_SYS_FSL_PBL_RCW \
99 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
101 #ifdef CONFIG_TARGET_T1042D4RDB
102 #define CONFIG_SYS_FSL_PBL_RCW \
103 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
108 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
109 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
110 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
111 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
112 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
113 #ifndef CONFIG_SPL_BUILD
114 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
116 #ifdef CONFIG_TARGET_T1040RDB
117 #define CONFIG_SYS_FSL_PBL_RCW \
118 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
120 #ifdef CONFIG_TARGET_T1042RDB_PI
121 #define CONFIG_SYS_FSL_PBL_RCW \
122 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
124 #ifdef CONFIG_TARGET_T1042RDB
125 #define CONFIG_SYS_FSL_PBL_RCW \
126 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
128 #ifdef CONFIG_TARGET_T1040D4RDB
129 #define CONFIG_SYS_FSL_PBL_RCW \
130 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
132 #ifdef CONFIG_TARGET_T1042D4RDB
133 #define CONFIG_SYS_FSL_PBL_RCW \
134 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
140 /* High Level Configuration Options */
141 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
143 /* support deep sleep */
144 #define CONFIG_DEEP_SLEEP
146 #ifndef CONFIG_RESET_VECTOR_ADDRESS
147 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
150 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
151 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
152 #define CONFIG_PCIE1 /* PCIE controller 1 */
153 #define CONFIG_PCIE2 /* PCIE controller 2 */
154 #define CONFIG_PCIE3 /* PCIE controller 3 */
155 #define CONFIG_PCIE4 /* PCIE controller 4 */
157 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
159 #define CONFIG_ENV_OVERWRITE
161 #if defined(CONFIG_SPIFLASH)
162 #elif defined(CONFIG_SDCARD)
163 #define CONFIG_SYS_MMC_ENV_DEV 0
164 #elif defined(CONFIG_MTD_RAW_NAND)
165 #ifdef CONFIG_NXP_ESBC
166 #define CONFIG_RAMBOOT_NAND
167 #define CONFIG_BOOTSCRIPT_COPY_RAM
171 #define CONFIG_SYS_CLK_FREQ 100000000
172 #define CONFIG_DDR_CLK_FREQ 66666666
175 * These can be toggled for performance analysis, otherwise use default.
177 #define CONFIG_SYS_CACHE_STASHING
178 #define CONFIG_BACKSIDE_L2_CACHE
179 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
180 #define CONFIG_BTB /* toggle branch predition */
181 #define CONFIG_DDR_ECC
182 #ifdef CONFIG_DDR_ECC
183 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
184 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
187 #define CONFIG_ENABLE_36BIT_PHYS
190 * Config the L3 Cache as L3 SRAM
192 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
194 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
195 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
196 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
198 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
199 #define CONFIG_SYS_L3_SIZE 256 << 10
200 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
201 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
202 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
203 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
204 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
206 #define CONFIG_SYS_DCSRBAR 0xf0000000
207 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
212 #define CONFIG_VERY_BIG_RAM
213 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
214 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
216 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
217 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
219 #define CONFIG_DDR_SPD
221 #define CONFIG_SYS_SPD_BUS_NUM 0
222 #define SPD_EEPROM_ADDRESS 0x51
224 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
229 #define CONFIG_SYS_FLASH_BASE 0xe8000000
230 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
232 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
233 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
234 CSPR_PORT_SIZE_16 | \
237 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
242 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
244 /* NOR Flash Timing Params */
245 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
247 FTIM0_NOR_TEADC(0x5) | \
248 FTIM0_NOR_TEAHC(0x5))
249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
250 FTIM1_NOR_TRAD_NOR(0x1A) |\
251 FTIM1_NOR_TSEQRAD_NOR(0x13))
252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
253 FTIM2_NOR_TCH(0x4) | \
254 FTIM2_NOR_TWPH(0x0E) | \
256 #define CONFIG_SYS_NOR_FTIM3 0x0
258 #define CONFIG_SYS_FLASH_QUIET_TEST
259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
261 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
266 #define CONFIG_SYS_FLASH_EMPTY_INFO
267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
270 #define CPLD_LBMAP_MASK 0x3F
271 #define CPLD_BANK_SEL_MASK 0x07
272 #define CPLD_BANK_OVERRIDE 0x40
273 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
274 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
275 #define CPLD_LBMAP_RESET 0xFF
276 #define CPLD_LBMAP_SHIFT 0x03
278 #if defined(CONFIG_TARGET_T1042RDB_PI)
279 #define CPLD_DIU_SEL_DFP 0x80
280 #elif defined(CONFIG_TARGET_T1042D4RDB)
281 #define CPLD_DIU_SEL_DFP 0xc0
284 #if defined(CONFIG_TARGET_T1040D4RDB)
285 #define CPLD_INT_MASK_ALL 0xFF
286 #define CPLD_INT_MASK_THERM 0x80
287 #define CPLD_INT_MASK_DVI_DFP 0x40
288 #define CPLD_INT_MASK_QSGMII1 0x20
289 #define CPLD_INT_MASK_QSGMII2 0x10
290 #define CPLD_INT_MASK_SGMI1 0x08
291 #define CPLD_INT_MASK_SGMI2 0x04
292 #define CPLD_INT_MASK_TDMR1 0x02
293 #define CPLD_INT_MASK_TDMR2 0x01
296 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
297 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
298 #define CONFIG_SYS_CSPR2_EXT (0xf)
299 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
303 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
304 #define CONFIG_SYS_CSOR2 0x0
305 /* CPLD Timing parameters for IFC CS2 */
306 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
307 FTIM0_GPCM_TEADC(0x0e) | \
308 FTIM0_GPCM_TEAHC(0x0e))
309 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
310 FTIM1_GPCM_TRAD(0x1f))
311 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
312 FTIM2_GPCM_TCH(0x8) | \
313 FTIM2_GPCM_TWP(0x1f))
314 #define CONFIG_SYS_CS2_FTIM3 0x0
316 /* NAND Flash on IFC */
317 #define CONFIG_NAND_FSL_IFC
318 #define CONFIG_SYS_NAND_BASE 0xff800000
319 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
321 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
322 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
323 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
324 | CSPR_MSEL_NAND /* MSEL = NAND */ \
326 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
328 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
329 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
330 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
331 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
332 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
333 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
334 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
336 #define CONFIG_SYS_NAND_ONFI_DETECTION
338 /* ONFI NAND Flash mode0 Timing Params */
339 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
340 FTIM0_NAND_TWP(0x18) | \
341 FTIM0_NAND_TWCHT(0x07) | \
342 FTIM0_NAND_TWH(0x0a))
343 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
344 FTIM1_NAND_TWBE(0x39) | \
345 FTIM1_NAND_TRR(0x0e) | \
346 FTIM1_NAND_TRP(0x18))
347 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
348 FTIM2_NAND_TREH(0x0a) | \
349 FTIM2_NAND_TWHRE(0x1e))
350 #define CONFIG_SYS_NAND_FTIM3 0x0
352 #define CONFIG_SYS_NAND_DDR_LAW 11
353 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
354 #define CONFIG_SYS_MAX_NAND_DEVICE 1
356 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
358 #if defined(CONFIG_MTD_RAW_NAND)
359 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
360 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
361 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
362 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
363 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
364 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
365 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
366 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
367 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
368 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
369 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
370 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
371 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
372 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
373 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
374 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
376 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
377 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
378 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
379 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
380 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
381 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
382 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
383 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
384 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
385 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
386 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
387 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
388 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
389 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
390 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
391 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
394 #ifdef CONFIG_SPL_BUILD
395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
397 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
400 #if defined(CONFIG_RAMBOOT_PBL)
401 #define CONFIG_SYS_RAMBOOT
404 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
405 #if defined(CONFIG_MTD_RAW_NAND)
406 #define CONFIG_A008044_WORKAROUND
410 #define CONFIG_HWCONFIG
412 /* define to use L1 as initial stack */
413 #define CONFIG_L1_INIT_RAM
414 #define CONFIG_SYS_INIT_RAM_LOCK
415 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
418 /* The assembler doesn't like typecast */
419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
420 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
421 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
422 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
424 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
425 GENERATED_GBL_DATA_SIZE)
426 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
428 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
429 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
431 /* Serial Port - controlled on board with jumper J8
435 #define CONFIG_SYS_NS16550_SERIAL
436 #define CONFIG_SYS_NS16550_REG_SIZE 1
437 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
439 #define CONFIG_SYS_BAUDRATE_TABLE \
440 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
442 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
443 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
444 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
445 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
447 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
449 #define CONFIG_FSL_DIU_FB
451 #ifdef CONFIG_FSL_DIU_FB
452 #define CONFIG_FSL_DIU_CH7301
453 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
454 #define CONFIG_VIDEO_LOGO
455 #define CONFIG_VIDEO_BMP_LOGO
460 #ifndef CONFIG_DM_I2C
461 #define CONFIG_SYS_I2C
462 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
463 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
464 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
465 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
466 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
467 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
468 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
469 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
470 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
471 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
472 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
473 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
475 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
476 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
479 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
480 /* I2C bus multiplexer */
481 #define I2C_MUX_PCA_ADDR 0x70
482 #define I2C_MUX_CH_DEFAULT 0x8
484 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
485 defined(CONFIG_TARGET_T1040D4RDB) || \
486 defined(CONFIG_TARGET_T1042D4RDB)
487 /* LDI/DVI Encoder for display */
488 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
489 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
490 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
496 #define CONFIG_RTC_DS1337 1
497 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
500 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
504 * eSPI - Enhanced SPI
509 * Memory space is mapped 1-1, but I/O space must start from 0.
513 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
515 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
516 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
517 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
518 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
521 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
523 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
524 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
525 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
526 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
529 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
531 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
532 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
533 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
534 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
537 /* controller 4, Base address 203000 */
539 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
540 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
541 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
542 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
545 #if !defined(CONFIG_DM_PCI)
546 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
547 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
548 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
549 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
550 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
551 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
552 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
553 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
554 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
555 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
556 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
557 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
558 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
559 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
560 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
561 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
562 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
563 #define CONFIG_PCI_INDIRECT_BRIDGE
565 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
566 #endif /* CONFIG_PCI */
569 #define CONFIG_FSL_SATA_V2
570 #ifdef CONFIG_FSL_SATA_V2
571 #define CONFIG_SYS_SATA_MAX_DEVICE 1
573 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
574 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
582 #define CONFIG_HAS_FSL_DR_USB
584 #ifdef CONFIG_HAS_FSL_DR_USB
585 #ifdef CONFIG_USB_EHCI_HCD
586 #define CONFIG_USB_EHCI_FSL
587 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
592 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
596 #ifndef CONFIG_NOBQFMAN
597 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
598 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
599 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
600 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
601 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
602 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
603 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
604 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
605 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
606 CONFIG_SYS_BMAN_CENA_SIZE)
607 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
608 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
609 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
610 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
611 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
612 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
613 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
614 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
615 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
616 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
617 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
618 CONFIG_SYS_QMAN_CENA_SIZE)
619 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
620 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
622 #define CONFIG_SYS_DPAA_FMAN
623 #define CONFIG_SYS_DPAA_PME
627 /* Default address of microcode for the Linux Fman driver */
628 #if defined(CONFIG_SPIFLASH)
630 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
631 * env, so we got 0x110000.
633 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
634 #elif defined(CONFIG_SDCARD)
636 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
637 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
638 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
640 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
641 #elif defined(CONFIG_MTD_RAW_NAND)
642 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
644 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
647 #if defined(CONFIG_SPIFLASH)
648 #define CONFIG_SYS_QE_FW_ADDR 0x130000
649 #elif defined(CONFIG_SDCARD)
650 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
651 #elif defined(CONFIG_MTD_RAW_NAND)
652 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
654 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
657 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
658 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
659 #endif /* CONFIG_NOBQFMAN */
661 #ifdef CONFIG_FMAN_ENET
662 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
663 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
664 #elif defined(CONFIG_TARGET_T1040D4RDB)
665 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
666 #elif defined(CONFIG_TARGET_T1042D4RDB)
667 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
668 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
669 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
672 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
673 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
674 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
676 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
677 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
680 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
681 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
682 #define CONFIG_VSC9953
683 #ifdef CONFIG_TARGET_T1040RDB
684 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
685 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
687 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
688 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
692 #define CONFIG_ETHPRIME "FM1@DTSEC4"
698 #define CONFIG_LOADS_ECHO /* echo on for serial download */
699 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
702 * Miscellaneous configurable options
704 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
707 * For booting Linux, the board info and command line data
708 * have to be in the first 64 MB of memory, since this is
709 * the maximum mapped by the Linux kernel during initialization.
711 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
712 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
714 #ifdef CONFIG_CMD_KGDB
715 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
719 * Dynamic MTD Partition support with mtdparts
723 * Environment Configuration
725 #define CONFIG_ROOTPATH "/opt/nfsroot"
726 #define CONFIG_BOOTFILE "uImage"
727 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
729 /* default location for tftp and bootm */
730 #define CONFIG_LOADADDR 1000000
732 #define __USB_PHY_TYPE utmi
733 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
735 #ifdef CONFIG_TARGET_T1040RDB
736 #define FDTFILE "t1040rdb/t1040rdb.dtb"
737 #elif defined(CONFIG_TARGET_T1042RDB_PI)
738 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
739 #elif defined(CONFIG_TARGET_T1042RDB)
740 #define FDTFILE "t1042rdb/t1042rdb.dtb"
741 #elif defined(CONFIG_TARGET_T1040D4RDB)
742 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
743 #elif defined(CONFIG_TARGET_T1042D4RDB)
744 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
747 #ifdef CONFIG_FSL_DIU_FB
748 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
750 #define DIU_ENVIRONMENT
753 #define CONFIG_EXTRA_ENV_SETTINGS \
754 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
755 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
756 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
758 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
759 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
760 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
761 "tftpflash=tftpboot $loadaddr $uboot && " \
762 "protect off $ubootaddr +$filesize && " \
763 "erase $ubootaddr +$filesize && " \
764 "cp.b $loadaddr $ubootaddr $filesize && " \
765 "protect on $ubootaddr +$filesize && " \
766 "cmp.b $loadaddr $ubootaddr $filesize\0" \
767 "consoledev=ttyS0\0" \
768 "ramdiskaddr=2000000\0" \
769 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
770 "fdtaddr=1e00000\0" \
771 "fdtfile=" __stringify(FDTFILE) "\0" \
774 #define CONFIG_LINUX \
775 "setenv bootargs root=/dev/ram rw " \
776 "console=$consoledev,$baudrate $othbootargs;" \
777 "setenv ramdiskaddr 0x02000000;" \
778 "setenv fdtaddr 0x00c00000;" \
779 "setenv loadaddr 0x1000000;" \
780 "bootm $loadaddr $ramdiskaddr $fdtaddr"
782 #define CONFIG_HDBOOT \
783 "setenv bootargs root=/dev/$bdev rw " \
784 "console=$consoledev,$baudrate $othbootargs;" \
785 "tftp $loadaddr $bootfile;" \
786 "tftp $fdtaddr $fdtfile;" \
787 "bootm $loadaddr - $fdtaddr"
789 #define CONFIG_NFSBOOTCOMMAND \
790 "setenv bootargs root=/dev/nfs rw " \
791 "nfsroot=$serverip:$rootpath " \
792 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
793 "console=$consoledev,$baudrate $othbootargs;" \
794 "tftp $loadaddr $bootfile;" \
795 "tftp $fdtaddr $fdtfile;" \
796 "bootm $loadaddr - $fdtaddr"
798 #define CONFIG_RAMBOOTCOMMAND \
799 "setenv bootargs root=/dev/ram rw " \
800 "console=$consoledev,$baudrate $othbootargs;" \
801 "tftp $ramdiskaddr $ramdiskfile;" \
802 "tftp $loadaddr $bootfile;" \
803 "tftp $fdtaddr $fdtfile;" \
804 "bootm $loadaddr $ramdiskaddr $fdtaddr"
806 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
808 #include <asm/fsl_secure_boot.h>
810 #endif /* __CONFIG_H */