2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
14 #define CONFIG_PHYS_64BIT
16 #define CONFIG_E500 /* BOOKE e500 family */
17 #include <asm/config_mpc85xx.h>
19 #ifdef CONFIG_RAMBOOT_PBL
20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
21 #ifdef CONFIG_T1040RDB
22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
24 #ifdef CONFIG_T1042RDB_PI
25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
27 #ifdef CONFIG_T1042RDB
28 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
31 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
32 #define CONFIG_SPL_ENV_SUPPORT
33 #define CONFIG_SPL_SERIAL_SUPPORT
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
36 #define CONFIG_SPL_LIBGENERIC_SUPPORT
37 #define CONFIG_SPL_LIBCOMMON_SUPPORT
38 #define CONFIG_SPL_I2C_SUPPORT
39 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
40 #define CONFIG_FSL_LAW /* Use common FSL init code */
41 #define CONFIG_SYS_TEXT_BASE 0x30001000
42 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
43 #define CONFIG_SPL_PAD_TO 0x40000
44 #define CONFIG_SPL_MAX_SIZE 0x28000
45 #ifdef CONFIG_SPL_BUILD
46 #define CONFIG_SPL_SKIP_RELOCATE
47 #define CONFIG_SPL_COMMON_INIT_DDR
48 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
49 #define CONFIG_SYS_NO_FLASH
51 #define RESET_VECTOR_OFFSET 0x27FFC
52 #define BOOT_PAGE_OFFSET 0x27000
55 #define CONFIG_SPL_NAND_SUPPORT
56 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
57 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
58 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
59 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
61 #define CONFIG_SPL_NAND_BOOT
64 #ifdef CONFIG_SPIFLASH
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
66 #define CONFIG_SPL_SPI_SUPPORT
67 #define CONFIG_SPL_SPI_FLASH_SUPPORT
68 #define CONFIG_SPL_SPI_FLASH_MINIMAL
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
74 #ifndef CONFIG_SPL_BUILD
75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
77 #define CONFIG_SPL_SPI_BOOT
81 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
82 #define CONFIG_SPL_MMC_SUPPORT
83 #define CONFIG_SPL_MMC_MINIMAL
84 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
85 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
86 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
87 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89 #ifndef CONFIG_SPL_BUILD
90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
92 #define CONFIG_SPL_MMC_BOOT
97 /* High Level Configuration Options */
99 #define CONFIG_E500MC /* BOOKE e500mc family */
100 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
101 #define CONFIG_MP /* support multiple processors */
103 /* support deep sleep */
104 #define CONFIG_DEEP_SLEEP
105 #define CONFIG_SILENT_CONSOLE
107 #ifndef CONFIG_SYS_TEXT_BASE
108 #define CONFIG_SYS_TEXT_BASE 0xeff40000
111 #ifndef CONFIG_RESET_VECTOR_ADDRESS
112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
115 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
116 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
117 #define CONFIG_FSL_IFC /* Enable IFC Support */
118 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
119 #define CONFIG_PCI /* Enable PCI/PCIE */
120 #define CONFIG_PCI_INDIRECT_BRIDGE
121 #define CONFIG_PCIE1 /* PCIE controler 1 */
122 #define CONFIG_PCIE2 /* PCIE controler 2 */
123 #define CONFIG_PCIE3 /* PCIE controler 3 */
124 #define CONFIG_PCIE4 /* PCIE controler 4 */
126 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
127 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
129 #define CONFIG_FSL_LAW /* Use common FSL init code */
131 #define CONFIG_ENV_OVERWRITE
133 #ifndef CONFIG_SYS_NO_FLASH
134 #define CONFIG_FLASH_CFI_DRIVER
135 #define CONFIG_SYS_FLASH_CFI
136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
139 #if defined(CONFIG_SPIFLASH)
140 #define CONFIG_SYS_EXTRA_ENV_RELOC
141 #define CONFIG_ENV_IS_IN_SPI_FLASH
142 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
143 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
144 #define CONFIG_ENV_SECT_SIZE 0x10000
145 #elif defined(CONFIG_SDCARD)
146 #define CONFIG_SYS_EXTRA_ENV_RELOC
147 #define CONFIG_ENV_IS_IN_MMC
148 #define CONFIG_SYS_MMC_ENV_DEV 0
149 #define CONFIG_ENV_SIZE 0x2000
150 #define CONFIG_ENV_OFFSET (512 * 0x800)
151 #elif defined(CONFIG_NAND)
152 #define CONFIG_SYS_EXTRA_ENV_RELOC
153 #define CONFIG_ENV_IS_IN_NAND
154 #define CONFIG_ENV_SIZE 0x2000
155 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
157 #define CONFIG_ENV_IS_IN_FLASH
158 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
159 #define CONFIG_ENV_SIZE 0x2000
160 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
163 #define CONFIG_SYS_CLK_FREQ 100000000
164 #define CONFIG_DDR_CLK_FREQ 66666666
167 * These can be toggled for performance analysis, otherwise use default.
169 #define CONFIG_SYS_CACHE_STASHING
170 #define CONFIG_BACKSIDE_L2_CACHE
171 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
172 #define CONFIG_BTB /* toggle branch predition */
173 #define CONFIG_DDR_ECC
174 #ifdef CONFIG_DDR_ECC
175 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
176 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
179 #define CONFIG_ENABLE_36BIT_PHYS
181 #define CONFIG_ADDR_MAP
182 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
184 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
185 #define CONFIG_SYS_MEMTEST_END 0x00400000
186 #define CONFIG_SYS_ALT_MEMTEST
187 #define CONFIG_PANIC_HANG /* do not reset board on panic */
190 * Config the L3 Cache as L3 SRAM
192 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
193 #define CONFIG_SYS_L3_SIZE 256 << 10
194 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
195 #ifdef CONFIG_RAMBOOT_PBL
196 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
198 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
199 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
200 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
201 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
203 #define CONFIG_SYS_DCSRBAR 0xf0000000
204 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
209 #define CONFIG_VERY_BIG_RAM
210 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
211 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
213 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
214 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
215 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
217 #define CONFIG_DDR_SPD
218 #define CONFIG_SYS_DDR_RAW_TIMING
219 #define CONFIG_SYS_FSL_DDR3
221 #define CONFIG_SYS_SPD_BUS_NUM 0
222 #define SPD_EEPROM_ADDRESS 0x51
224 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
229 #define CONFIG_SYS_FLASH_BASE 0xe8000000
230 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
232 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
233 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
234 CSPR_PORT_SIZE_16 | \
237 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
242 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
244 /* NOR Flash Timing Params */
245 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
247 FTIM0_NOR_TEADC(0x5) | \
248 FTIM0_NOR_TEAHC(0x5))
249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
250 FTIM1_NOR_TRAD_NOR(0x1A) |\
251 FTIM1_NOR_TSEQRAD_NOR(0x13))
252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
253 FTIM2_NOR_TCH(0x4) | \
254 FTIM2_NOR_TWPH(0x0E) | \
256 #define CONFIG_SYS_NOR_FTIM3 0x0
258 #define CONFIG_SYS_FLASH_QUIET_TEST
259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
261 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
266 #define CONFIG_SYS_FLASH_EMPTY_INFO
267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
270 #define CPLD_LBMAP_MASK 0x3F
271 #define CPLD_BANK_SEL_MASK 0x07
272 #define CPLD_BANK_OVERRIDE 0x40
273 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
274 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
275 #define CPLD_LBMAP_RESET 0xFF
276 #define CPLD_LBMAP_SHIFT 0x03
277 #ifdef CONFIG_T1042RDB_PI
278 #define CPLD_DIU_SEL_DFP 0x80
281 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
282 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
283 #define CONFIG_SYS_CSPR2_EXT (0xf)
284 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
288 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
289 #define CONFIG_SYS_CSOR2 0x0
290 /* CPLD Timing parameters for IFC CS2 */
291 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
292 FTIM0_GPCM_TEADC(0x0e) | \
293 FTIM0_GPCM_TEAHC(0x0e))
294 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
295 FTIM1_GPCM_TRAD(0x1f))
296 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
297 FTIM2_GPCM_TCH(0x8) | \
298 FTIM2_GPCM_TWP(0x1f))
299 #define CONFIG_SYS_CS2_FTIM3 0x0
301 /* NAND Flash on IFC */
302 #define CONFIG_NAND_FSL_IFC
303 #define CONFIG_SYS_NAND_BASE 0xff800000
304 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
306 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
307 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
308 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
309 | CSPR_MSEL_NAND /* MSEL = NAND */ \
311 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
313 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
314 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
315 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
316 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
317 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
318 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
319 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
321 #define CONFIG_SYS_NAND_ONFI_DETECTION
323 /* ONFI NAND Flash mode0 Timing Params */
324 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
325 FTIM0_NAND_TWP(0x18) | \
326 FTIM0_NAND_TWCHT(0x07) | \
327 FTIM0_NAND_TWH(0x0a))
328 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
329 FTIM1_NAND_TWBE(0x39) | \
330 FTIM1_NAND_TRR(0x0e) | \
331 FTIM1_NAND_TRP(0x18))
332 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
333 FTIM2_NAND_TREH(0x0a) | \
334 FTIM2_NAND_TWHRE(0x1e))
335 #define CONFIG_SYS_NAND_FTIM3 0x0
337 #define CONFIG_SYS_NAND_DDR_LAW 11
338 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
339 #define CONFIG_SYS_MAX_NAND_DEVICE 1
340 #define CONFIG_MTD_NAND_VERIFY_WRITE
341 #define CONFIG_CMD_NAND
343 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
345 #if defined(CONFIG_NAND)
346 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
347 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
348 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
349 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
350 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
351 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
352 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
353 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
354 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
355 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
356 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
357 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
358 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
359 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
360 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
361 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
363 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
364 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
365 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
366 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
367 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
368 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
369 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
370 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
371 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
372 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
373 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
374 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
375 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
376 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
377 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
378 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
381 #ifdef CONFIG_SPL_BUILD
382 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
384 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
387 #if defined(CONFIG_RAMBOOT_PBL)
388 #define CONFIG_SYS_RAMBOOT
391 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
392 #if defined(CONFIG_NAND)
393 #define CONFIG_A008044_WORKAROUND
397 #define CONFIG_BOARD_EARLY_INIT_R
398 #define CONFIG_MISC_INIT_R
400 #define CONFIG_HWCONFIG
402 /* define to use L1 as initial stack */
403 #define CONFIG_L1_INIT_RAM
404 #define CONFIG_SYS_INIT_RAM_LOCK
405 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
408 /* The assembler doesn't like typecast */
409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
410 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
411 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
412 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
414 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
415 GENERATED_GBL_DATA_SIZE)
416 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
418 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
419 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
421 /* Serial Port - controlled on board with jumper J8
425 #define CONFIG_CONS_INDEX 1
426 #define CONFIG_SYS_NS16550
427 #define CONFIG_SYS_NS16550_SERIAL
428 #define CONFIG_SYS_NS16550_REG_SIZE 1
429 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
431 #define CONFIG_SYS_BAUDRATE_TABLE \
432 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
434 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
435 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
436 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
437 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
438 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
439 #ifndef CONFIG_SPL_BUILD
440 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
443 /* Use the HUSH parser */
444 #define CONFIG_SYS_HUSH_PARSER
445 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
447 #ifdef CONFIG_T1042RDB_PI
449 #define CONFIG_FSL_DIU_FB
451 #ifdef CONFIG_FSL_DIU_FB
452 #define CONFIG_FSL_DIU_CH7301
453 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
455 #define CONFIG_CMD_BMP
456 #define CONFIG_CFB_CONSOLE
457 #define CONFIG_CFB_CONSOLE_ANSI
458 #define CONFIG_VIDEO_SW_CURSOR
459 #define CONFIG_VGA_AS_SINGLE_DEVICE
460 #define CONFIG_VIDEO_LOGO
461 #define CONFIG_VIDEO_BMP_LOGO
465 /* pass open firmware flat tree */
466 #define CONFIG_OF_LIBFDT
467 #define CONFIG_OF_BOARD_SETUP
468 #define CONFIG_OF_STDOUT_VIA_ALIAS
470 /* new uImage format support */
472 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
475 #define CONFIG_SYS_I2C
476 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
477 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
478 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
479 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
480 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
481 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
482 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
483 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
484 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
485 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
486 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
487 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
488 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
490 /* I2C bus multiplexer */
491 #define I2C_MUX_PCA_ADDR 0x70
492 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
493 #define I2C_MUX_CH_DEFAULT 0x8
496 #ifdef CONFIG_T1042RDB_PI
497 /* LDI/DVI Encoder for display */
498 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
499 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
505 #define CONFIG_RTC_DS1337 1
506 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
509 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
513 * eSPI - Enhanced SPI
515 #define CONFIG_FSL_ESPI
516 #define CONFIG_SPI_FLASH
517 #define CONFIG_SPI_FLASH_STMICRO
518 #define CONFIG_SPI_FLASH_BAR
519 #define CONFIG_CMD_SF
520 #define CONFIG_SF_DEFAULT_SPEED 10000000
521 #define CONFIG_SF_DEFAULT_MODE 0
522 #define CONFIG_ENV_SPI_BUS 0
523 #define CONFIG_ENV_SPI_CS 0
524 #define CONFIG_ENV_SPI_MAX_HZ 10000000
525 #define CONFIG_ENV_SPI_MODE 0
529 * Memory space is mapped 1-1, but I/O space must start from 0.
533 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
535 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
536 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
537 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
538 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
539 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
540 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
541 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
542 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
545 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
547 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
548 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
549 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
550 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
551 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
552 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
553 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
554 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
557 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
559 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
560 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
561 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
562 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
563 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
564 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
565 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
566 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
569 /* controller 4, Base address 203000 */
571 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
572 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
573 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
574 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
575 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
576 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
577 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
578 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
581 #define CONFIG_PCI_PNP /* do pci plug-and-play */
584 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
585 #define CONFIG_DOS_PARTITION
586 #endif /* CONFIG_PCI */
589 #define CONFIG_FSL_SATA_V2
590 #ifdef CONFIG_FSL_SATA_V2
591 #define CONFIG_LIBATA
592 #define CONFIG_FSL_SATA
594 #define CONFIG_SYS_SATA_MAX_DEVICE 1
596 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
597 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
600 #define CONFIG_CMD_SATA
601 #define CONFIG_DOS_PARTITION
602 #define CONFIG_CMD_EXT2
608 #define CONFIG_HAS_FSL_DR_USB
610 #ifdef CONFIG_HAS_FSL_DR_USB
611 #define CONFIG_USB_EHCI
613 #ifdef CONFIG_USB_EHCI
614 #define CONFIG_CMD_USB
615 #define CONFIG_USB_STORAGE
616 #define CONFIG_USB_EHCI_FSL
617 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
618 #define CONFIG_CMD_EXT2
625 #define CONFIG_FSL_ESDHC
626 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
627 #define CONFIG_CMD_MMC
628 #define CONFIG_GENERIC_MMC
629 #define CONFIG_CMD_EXT2
630 #define CONFIG_CMD_FAT
631 #define CONFIG_DOS_PARTITION
635 #ifndef CONFIG_NOBQFMAN
636 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
637 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
638 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
639 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
640 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
641 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
642 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
643 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
644 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
646 #define CONFIG_SYS_DPAA_FMAN
647 #define CONFIG_SYS_DPAA_PME
649 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
654 /* Default address of microcode for the Linux Fman driver */
655 #if defined(CONFIG_SPIFLASH)
657 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
658 * env, so we got 0x110000.
660 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
661 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
662 #elif defined(CONFIG_SDCARD)
664 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
665 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
666 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
668 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
669 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
670 #elif defined(CONFIG_NAND)
671 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
672 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
674 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
675 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
678 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
679 #if defined(CONFIG_SPIFLASH)
680 #define CONFIG_SYS_QE_FW_ADDR 0x130000
681 #elif defined(CONFIG_SDCARD)
682 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
683 #elif defined(CONFIG_NAND)
684 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
686 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
691 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
692 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
693 #endif /* CONFIG_NOBQFMAN */
695 #ifdef CONFIG_SYS_DPAA_FMAN
696 #define CONFIG_FMAN_ENET
697 #define CONFIG_PHY_VITESSE
698 #define CONFIG_PHY_REALTEK
701 #ifdef CONFIG_FMAN_ENET
702 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
703 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
705 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
706 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
708 #define CONFIG_MII /* MII PHY management */
709 #define CONFIG_ETHPRIME "FM1@DTSEC4"
710 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
716 #define CONFIG_LOADS_ECHO /* echo on for serial download */
717 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
720 * Command line configuration.
722 #include <config_cmd_default.h>
724 #ifdef CONFIG_T1042RDB_PI
725 #define CONFIG_CMD_DATE
727 #define CONFIG_CMD_DHCP
728 #define CONFIG_CMD_ELF
729 #define CONFIG_CMD_ERRATA
730 #define CONFIG_CMD_GREPENV
731 #define CONFIG_CMD_IRQ
732 #define CONFIG_CMD_I2C
733 #define CONFIG_CMD_MII
734 #define CONFIG_CMD_PING
735 #define CONFIG_CMD_REGINFO
736 #define CONFIG_CMD_SETEXPR
739 #define CONFIG_CMD_PCI
740 #define CONFIG_CMD_NET
743 /* Hash command with SHA acceleration supported in hardware */
744 #ifdef CONFIG_FSL_CAAM
745 #define CONFIG_CMD_HASH
746 #define CONFIG_SHA_HW_ACCEL
750 * Miscellaneous configurable options
752 #define CONFIG_SYS_LONGHELP /* undef to save memory */
753 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
754 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
755 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
756 #ifdef CONFIG_CMD_KGDB
757 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
759 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
761 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
762 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
763 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
766 * For booting Linux, the board info and command line data
767 * have to be in the first 64 MB of memory, since this is
768 * the maximum mapped by the Linux kernel during initialization.
770 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
771 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
773 #ifdef CONFIG_CMD_KGDB
774 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
778 * Dynamic MTD Partition support with mtdparts
780 #ifndef CONFIG_SYS_NO_FLASH
781 #define CONFIG_MTD_DEVICE
782 #define CONFIG_MTD_PARTITIONS
783 #define CONFIG_CMD_MTDPARTS
784 #define CONFIG_FLASH_CFI_MTD
785 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
787 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
788 "128k(dtb),96m(fs),-(user);"\
789 "fff800000.flash:2m(uboot),9m(kernel),"\
790 "128k(dtb),96m(fs),-(user);spife110000.0:" \
791 "2m(uboot),9m(kernel),128k(dtb),-(user)"
795 * Environment Configuration
797 #define CONFIG_ROOTPATH "/opt/nfsroot"
798 #define CONFIG_BOOTFILE "uImage"
799 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
801 /* default location for tftp and bootm */
802 #define CONFIG_LOADADDR 1000000
804 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
806 #define CONFIG_BAUDRATE 115200
808 #define __USB_PHY_TYPE utmi
809 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
811 #ifdef CONFIG_T1040RDB
812 #define FDTFILE "t1040rdb/t1040rdb.dtb"
813 #elif defined(CONFIG_T1042RDB_PI)
814 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
815 #elif defined(CONFIG_T1042RDB)
816 #define FDTFILE "t1042rdb/t1042rdb.dtb"
819 #ifdef CONFIG_FSL_DIU_FB
820 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
822 #define DIU_ENVIRONMENT
825 #define CONFIG_EXTRA_ENV_SETTINGS \
826 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
827 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
828 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
830 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
831 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
832 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
833 "tftpflash=tftpboot $loadaddr $uboot && " \
834 "protect off $ubootaddr +$filesize && " \
835 "erase $ubootaddr +$filesize && " \
836 "cp.b $loadaddr $ubootaddr $filesize && " \
837 "protect on $ubootaddr +$filesize && " \
838 "cmp.b $loadaddr $ubootaddr $filesize\0" \
839 "consoledev=ttyS0\0" \
840 "ramdiskaddr=2000000\0" \
841 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
843 "fdtfile=" __stringify(FDTFILE) "\0" \
846 #define CONFIG_LINUX \
847 "setenv bootargs root=/dev/ram rw " \
848 "console=$consoledev,$baudrate $othbootargs;" \
849 "setenv ramdiskaddr 0x02000000;" \
850 "setenv fdtaddr 0x00c00000;" \
851 "setenv loadaddr 0x1000000;" \
852 "bootm $loadaddr $ramdiskaddr $fdtaddr"
854 #define CONFIG_HDBOOT \
855 "setenv bootargs root=/dev/$bdev rw " \
856 "console=$consoledev,$baudrate $othbootargs;" \
857 "tftp $loadaddr $bootfile;" \
858 "tftp $fdtaddr $fdtfile;" \
859 "bootm $loadaddr - $fdtaddr"
861 #define CONFIG_NFSBOOTCOMMAND \
862 "setenv bootargs root=/dev/nfs rw " \
863 "nfsroot=$serverip:$rootpath " \
864 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
865 "console=$consoledev,$baudrate $othbootargs;" \
866 "tftp $loadaddr $bootfile;" \
867 "tftp $fdtaddr $fdtfile;" \
868 "bootm $loadaddr - $fdtaddr"
870 #define CONFIG_RAMBOOTCOMMAND \
871 "setenv bootargs root=/dev/ram rw " \
872 "console=$consoledev,$baudrate $othbootargs;" \
873 "tftp $ramdiskaddr $ramdiskfile;" \
874 "tftp $loadaddr $bootfile;" \
875 "tftp $fdtaddr $fdtfile;" \
876 "bootm $loadaddr $ramdiskaddr $fdtaddr"
878 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
880 #ifdef CONFIG_SECURE_BOOT
881 #include <asm/fsl_secure_boot.h>
882 #define CONFIG_CMD_BLOB
885 #endif /* __CONFIG_H */