2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
15 #define CONFIG_E500 /* BOOKE e500 family */
16 #include <asm/config_mpc85xx.h>
18 #ifdef CONFIG_RAMBOOT_PBL
20 #ifndef CONFIG_SECURE_BOOT
21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
23 #define CONFIG_SYS_FSL_PBL_PBI \
24 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29 #define CONFIG_FSL_LAW /* Use common FSL init code */
30 #define CONFIG_SYS_TEXT_BASE 0x30001000
31 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
32 #define CONFIG_SPL_PAD_TO 0x40000
33 #define CONFIG_SPL_MAX_SIZE 0x28000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #define CONFIG_SYS_NO_FLASH
40 #define RESET_VECTOR_OFFSET 0x27FFC
41 #define BOOT_PAGE_OFFSET 0x27000
44 #ifdef CONFIG_SECURE_BOOT
45 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
47 * HDR would be appended at end of image and copied to DDR along
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
51 CONFIG_U_BOOT_HDR_SIZE)
53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
55 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
56 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
59 #ifdef CONFIG_T1040RDB
60 #define CONFIG_SYS_FSL_PBL_RCW \
61 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
63 #ifdef CONFIG_T1042RDB_PI
64 #define CONFIG_SYS_FSL_PBL_RCW \
65 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
67 #ifdef CONFIG_T1042RDB
68 #define CONFIG_SYS_FSL_PBL_RCW \
69 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
71 #ifdef CONFIG_T1040D4RDB
72 #define CONFIG_SYS_FSL_PBL_RCW \
73 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
75 #ifdef CONFIG_T1042D4RDB
76 #define CONFIG_SYS_FSL_PBL_RCW \
77 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
79 #define CONFIG_SPL_NAND_BOOT
82 #ifdef CONFIG_SPIFLASH
83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
84 #define CONFIG_SPL_SPI_FLASH_MINIMAL
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90 #ifndef CONFIG_SPL_BUILD
91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
93 #ifdef CONFIG_T1040RDB
94 #define CONFIG_SYS_FSL_PBL_RCW \
95 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
97 #ifdef CONFIG_T1042RDB_PI
98 #define CONFIG_SYS_FSL_PBL_RCW \
99 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
101 #ifdef CONFIG_T1042RDB
102 #define CONFIG_SYS_FSL_PBL_RCW \
103 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
105 #ifdef CONFIG_T1040D4RDB
106 #define CONFIG_SYS_FSL_PBL_RCW \
107 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
109 #ifdef CONFIG_T1042D4RDB
110 #define CONFIG_SYS_FSL_PBL_RCW \
111 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
113 #define CONFIG_SPL_SPI_BOOT
117 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
118 #define CONFIG_SPL_MMC_MINIMAL
119 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
120 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
121 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
122 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
123 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
124 #ifndef CONFIG_SPL_BUILD
125 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
127 #ifdef CONFIG_T1040RDB
128 #define CONFIG_SYS_FSL_PBL_RCW \
129 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
131 #ifdef CONFIG_T1042RDB_PI
132 #define CONFIG_SYS_FSL_PBL_RCW \
133 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
135 #ifdef CONFIG_T1042RDB
136 #define CONFIG_SYS_FSL_PBL_RCW \
137 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
139 #ifdef CONFIG_T1040D4RDB
140 #define CONFIG_SYS_FSL_PBL_RCW \
141 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
143 #ifdef CONFIG_T1042D4RDB
144 #define CONFIG_SYS_FSL_PBL_RCW \
145 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
147 #define CONFIG_SPL_MMC_BOOT
152 /* High Level Configuration Options */
154 #define CONFIG_E500MC /* BOOKE e500mc family */
155 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
156 #define CONFIG_MP /* support multiple processors */
158 /* support deep sleep */
159 #define CONFIG_DEEP_SLEEP
160 #if defined(CONFIG_DEEP_SLEEP)
161 #define CONFIG_BOARD_EARLY_INIT_F
164 #ifndef CONFIG_SYS_TEXT_BASE
165 #define CONFIG_SYS_TEXT_BASE 0xeff40000
168 #ifndef CONFIG_RESET_VECTOR_ADDRESS
169 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
172 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
173 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
174 #define CONFIG_FSL_IFC /* Enable IFC Support */
175 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
176 #define CONFIG_PCI /* Enable PCI/PCIE */
177 #define CONFIG_PCI_INDIRECT_BRIDGE
178 #define CONFIG_PCIE1 /* PCIE controller 1 */
179 #define CONFIG_PCIE2 /* PCIE controller 2 */
180 #define CONFIG_PCIE3 /* PCIE controller 3 */
181 #define CONFIG_PCIE4 /* PCIE controller 4 */
183 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
184 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
186 #define CONFIG_FSL_LAW /* Use common FSL init code */
188 #define CONFIG_ENV_OVERWRITE
190 #ifndef CONFIG_SYS_NO_FLASH
191 #define CONFIG_FLASH_CFI_DRIVER
192 #define CONFIG_SYS_FLASH_CFI
193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
196 #if defined(CONFIG_SPIFLASH)
197 #define CONFIG_SYS_EXTRA_ENV_RELOC
198 #define CONFIG_ENV_IS_IN_SPI_FLASH
199 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
200 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
201 #define CONFIG_ENV_SECT_SIZE 0x10000
202 #elif defined(CONFIG_SDCARD)
203 #define CONFIG_SYS_EXTRA_ENV_RELOC
204 #define CONFIG_ENV_IS_IN_MMC
205 #define CONFIG_SYS_MMC_ENV_DEV 0
206 #define CONFIG_ENV_SIZE 0x2000
207 #define CONFIG_ENV_OFFSET (512 * 0x800)
208 #elif defined(CONFIG_NAND)
209 #ifdef CONFIG_SECURE_BOOT
210 #define CONFIG_RAMBOOT_NAND
211 #define CONFIG_BOOTSCRIPT_COPY_RAM
213 #define CONFIG_SYS_EXTRA_ENV_RELOC
214 #define CONFIG_ENV_IS_IN_NAND
215 #define CONFIG_ENV_SIZE 0x2000
216 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
218 #define CONFIG_ENV_IS_IN_FLASH
219 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
220 #define CONFIG_ENV_SIZE 0x2000
221 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
224 #define CONFIG_SYS_CLK_FREQ 100000000
225 #define CONFIG_DDR_CLK_FREQ 66666666
228 * These can be toggled for performance analysis, otherwise use default.
230 #define CONFIG_SYS_CACHE_STASHING
231 #define CONFIG_BACKSIDE_L2_CACHE
232 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
233 #define CONFIG_BTB /* toggle branch predition */
234 #define CONFIG_DDR_ECC
235 #ifdef CONFIG_DDR_ECC
236 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
237 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
240 #define CONFIG_ENABLE_36BIT_PHYS
242 #define CONFIG_ADDR_MAP
243 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
245 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
246 #define CONFIG_SYS_MEMTEST_END 0x00400000
247 #define CONFIG_SYS_ALT_MEMTEST
248 #define CONFIG_PANIC_HANG /* do not reset board on panic */
251 * Config the L3 Cache as L3 SRAM
253 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
255 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
256 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
257 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
259 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
260 #define CONFIG_SYS_L3_SIZE 256 << 10
261 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
262 #ifdef CONFIG_RAMBOOT_PBL
263 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
265 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
266 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
267 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
268 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
270 #define CONFIG_SYS_DCSRBAR 0xf0000000
271 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
276 #define CONFIG_VERY_BIG_RAM
277 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
278 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
280 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
281 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
282 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
284 #define CONFIG_DDR_SPD
285 #ifndef CONFIG_SYS_FSL_DDR4
286 #define CONFIG_SYS_FSL_DDR3
289 #define CONFIG_SYS_SPD_BUS_NUM 0
290 #define SPD_EEPROM_ADDRESS 0x51
292 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
297 #define CONFIG_SYS_FLASH_BASE 0xe8000000
298 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
300 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
301 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
302 CSPR_PORT_SIZE_16 | \
305 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
310 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
312 /* NOR Flash Timing Params */
313 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
314 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
315 FTIM0_NOR_TEADC(0x5) | \
316 FTIM0_NOR_TEAHC(0x5))
317 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
318 FTIM1_NOR_TRAD_NOR(0x1A) |\
319 FTIM1_NOR_TSEQRAD_NOR(0x13))
320 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
321 FTIM2_NOR_TCH(0x4) | \
322 FTIM2_NOR_TWPH(0x0E) | \
324 #define CONFIG_SYS_NOR_FTIM3 0x0
326 #define CONFIG_SYS_FLASH_QUIET_TEST
327 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
329 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
330 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
331 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
332 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
334 #define CONFIG_SYS_FLASH_EMPTY_INFO
335 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
338 #define CPLD_LBMAP_MASK 0x3F
339 #define CPLD_BANK_SEL_MASK 0x07
340 #define CPLD_BANK_OVERRIDE 0x40
341 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
342 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
343 #define CPLD_LBMAP_RESET 0xFF
344 #define CPLD_LBMAP_SHIFT 0x03
346 #if defined(CONFIG_T1042RDB_PI)
347 #define CPLD_DIU_SEL_DFP 0x80
348 #elif defined(CONFIG_T1042D4RDB)
349 #define CPLD_DIU_SEL_DFP 0xc0
352 #if defined(CONFIG_T1040D4RDB)
353 #define CPLD_INT_MASK_ALL 0xFF
354 #define CPLD_INT_MASK_THERM 0x80
355 #define CPLD_INT_MASK_DVI_DFP 0x40
356 #define CPLD_INT_MASK_QSGMII1 0x20
357 #define CPLD_INT_MASK_QSGMII2 0x10
358 #define CPLD_INT_MASK_SGMI1 0x08
359 #define CPLD_INT_MASK_SGMI2 0x04
360 #define CPLD_INT_MASK_TDMR1 0x02
361 #define CPLD_INT_MASK_TDMR2 0x01
364 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
365 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
366 #define CONFIG_SYS_CSPR2_EXT (0xf)
367 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
371 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
372 #define CONFIG_SYS_CSOR2 0x0
373 /* CPLD Timing parameters for IFC CS2 */
374 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
375 FTIM0_GPCM_TEADC(0x0e) | \
376 FTIM0_GPCM_TEAHC(0x0e))
377 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
378 FTIM1_GPCM_TRAD(0x1f))
379 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
380 FTIM2_GPCM_TCH(0x8) | \
381 FTIM2_GPCM_TWP(0x1f))
382 #define CONFIG_SYS_CS2_FTIM3 0x0
384 /* NAND Flash on IFC */
385 #define CONFIG_NAND_FSL_IFC
386 #define CONFIG_SYS_NAND_BASE 0xff800000
387 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
389 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
390 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
391 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
392 | CSPR_MSEL_NAND /* MSEL = NAND */ \
394 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
396 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
397 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
398 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
399 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
400 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
401 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
402 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
404 #define CONFIG_SYS_NAND_ONFI_DETECTION
406 /* ONFI NAND Flash mode0 Timing Params */
407 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
408 FTIM0_NAND_TWP(0x18) | \
409 FTIM0_NAND_TWCHT(0x07) | \
410 FTIM0_NAND_TWH(0x0a))
411 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
412 FTIM1_NAND_TWBE(0x39) | \
413 FTIM1_NAND_TRR(0x0e) | \
414 FTIM1_NAND_TRP(0x18))
415 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
416 FTIM2_NAND_TREH(0x0a) | \
417 FTIM2_NAND_TWHRE(0x1e))
418 #define CONFIG_SYS_NAND_FTIM3 0x0
420 #define CONFIG_SYS_NAND_DDR_LAW 11
421 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
422 #define CONFIG_SYS_MAX_NAND_DEVICE 1
423 #define CONFIG_CMD_NAND
425 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
427 #if defined(CONFIG_NAND)
428 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
429 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
430 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
431 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
432 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
433 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
434 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
435 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
436 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
437 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
438 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
439 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
440 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
441 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
442 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
443 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
445 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
446 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
447 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
448 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
449 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
450 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
451 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
452 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
453 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
454 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
455 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
456 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
457 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
458 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
459 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
460 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
463 #ifdef CONFIG_SPL_BUILD
464 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
466 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
469 #if defined(CONFIG_RAMBOOT_PBL)
470 #define CONFIG_SYS_RAMBOOT
473 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
474 #if defined(CONFIG_NAND)
475 #define CONFIG_A008044_WORKAROUND
479 #define CONFIG_BOARD_EARLY_INIT_R
480 #define CONFIG_MISC_INIT_R
482 #define CONFIG_HWCONFIG
484 /* define to use L1 as initial stack */
485 #define CONFIG_L1_INIT_RAM
486 #define CONFIG_SYS_INIT_RAM_LOCK
487 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
489 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
490 /* The assembler doesn't like typecast */
491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
492 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
493 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
494 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
496 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
497 GENERATED_GBL_DATA_SIZE)
498 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
500 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
501 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
503 /* Serial Port - controlled on board with jumper J8
507 #define CONFIG_CONS_INDEX 1
508 #define CONFIG_SYS_NS16550_SERIAL
509 #define CONFIG_SYS_NS16550_REG_SIZE 1
510 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
512 #define CONFIG_SYS_BAUDRATE_TABLE \
513 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
515 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
516 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
517 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
518 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
520 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
522 #define CONFIG_FSL_DIU_FB
524 #ifdef CONFIG_FSL_DIU_FB
525 #define CONFIG_FSL_DIU_CH7301
526 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
527 #define CONFIG_CMD_BMP
528 #define CONFIG_VIDEO_SW_CURSOR
529 #define CONFIG_VGA_AS_SINGLE_DEVICE
530 #define CONFIG_VIDEO_LOGO
531 #define CONFIG_VIDEO_BMP_LOGO
536 #define CONFIG_SYS_I2C
537 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
538 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
539 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
540 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
541 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
542 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
543 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
544 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
545 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
546 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
547 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
548 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
549 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
551 /* I2C bus multiplexer */
552 #define I2C_MUX_PCA_ADDR 0x70
553 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
554 #define I2C_MUX_CH_DEFAULT 0x8
557 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
558 /* LDI/DVI Encoder for display */
559 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
560 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
566 #define CONFIG_RTC_DS1337 1
567 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
570 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
574 * eSPI - Enhanced SPI
576 #define CONFIG_SPI_FLASH_BAR
577 #define CONFIG_SF_DEFAULT_SPEED 10000000
578 #define CONFIG_SF_DEFAULT_MODE 0
579 #define CONFIG_ENV_SPI_BUS 0
580 #define CONFIG_ENV_SPI_CS 0
581 #define CONFIG_ENV_SPI_MAX_HZ 10000000
582 #define CONFIG_ENV_SPI_MODE 0
586 * Memory space is mapped 1-1, but I/O space must start from 0.
590 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
592 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
593 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
594 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
595 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
596 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
597 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
598 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
599 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
602 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
604 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
605 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
606 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
607 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
608 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
609 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
610 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
611 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
614 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
616 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
617 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
618 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
619 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
620 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
621 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
622 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
623 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
626 /* controller 4, Base address 203000 */
628 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
629 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
630 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
631 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
632 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
633 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
634 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
635 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
638 #define CONFIG_PCI_PNP /* do pci plug-and-play */
640 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
641 #define CONFIG_DOS_PARTITION
642 #endif /* CONFIG_PCI */
645 #define CONFIG_FSL_SATA_V2
646 #ifdef CONFIG_FSL_SATA_V2
647 #define CONFIG_LIBATA
648 #define CONFIG_FSL_SATA
650 #define CONFIG_SYS_SATA_MAX_DEVICE 1
652 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
653 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
656 #define CONFIG_CMD_SATA
657 #define CONFIG_DOS_PARTITION
663 #define CONFIG_HAS_FSL_DR_USB
665 #ifdef CONFIG_HAS_FSL_DR_USB
666 #define CONFIG_USB_EHCI
668 #ifdef CONFIG_USB_EHCI
669 #define CONFIG_USB_EHCI_FSL
670 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
677 #define CONFIG_FSL_ESDHC
678 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
679 #define CONFIG_GENERIC_MMC
680 #define CONFIG_DOS_PARTITION
684 #ifndef CONFIG_NOBQFMAN
685 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
686 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
687 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
688 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
689 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
690 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
691 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
692 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
693 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
694 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
695 CONFIG_SYS_BMAN_CENA_SIZE)
696 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
697 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
698 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
699 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
700 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
701 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
702 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
703 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
704 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
705 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
706 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
707 CONFIG_SYS_QMAN_CENA_SIZE)
708 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
709 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
711 #define CONFIG_SYS_DPAA_FMAN
712 #define CONFIG_SYS_DPAA_PME
714 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
719 /* Default address of microcode for the Linux Fman driver */
720 #if defined(CONFIG_SPIFLASH)
722 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
723 * env, so we got 0x110000.
725 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
726 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
727 #elif defined(CONFIG_SDCARD)
729 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
730 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
731 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
733 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
734 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
735 #elif defined(CONFIG_NAND)
736 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
737 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
739 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
740 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
743 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
744 #if defined(CONFIG_SPIFLASH)
745 #define CONFIG_SYS_QE_FW_ADDR 0x130000
746 #elif defined(CONFIG_SDCARD)
747 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
748 #elif defined(CONFIG_NAND)
749 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
751 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
755 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
756 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
757 #endif /* CONFIG_NOBQFMAN */
759 #ifdef CONFIG_SYS_DPAA_FMAN
760 #define CONFIG_FMAN_ENET
761 #define CONFIG_PHY_VITESSE
762 #define CONFIG_PHY_REALTEK
765 #ifdef CONFIG_FMAN_ENET
766 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
767 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
768 #elif defined(CONFIG_T1040D4RDB)
769 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
770 #elif defined(CONFIG_T1042D4RDB)
771 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
772 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
773 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
776 #ifdef CONFIG_T104XD4RDB
777 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
778 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
780 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
781 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
784 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
785 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
786 #define CONFIG_VSC9953
787 #define CONFIG_CMD_ETHSW
788 #ifdef CONFIG_T1040RDB
789 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
790 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
792 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
793 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
797 #define CONFIG_MII /* MII PHY management */
798 #define CONFIG_ETHPRIME "FM1@DTSEC4"
799 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
805 #define CONFIG_LOADS_ECHO /* echo on for serial download */
806 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
809 * Command line configuration.
811 #ifdef CONFIG_T1042RDB_PI
812 #define CONFIG_CMD_DATE
814 #define CONFIG_CMD_ERRATA
815 #define CONFIG_CMD_IRQ
816 #define CONFIG_CMD_REGINFO
819 #define CONFIG_CMD_PCI
822 /* Hash command with SHA acceleration supported in hardware */
823 #ifdef CONFIG_FSL_CAAM
824 #define CONFIG_CMD_HASH
825 #define CONFIG_SHA_HW_ACCEL
829 * Miscellaneous configurable options
831 #define CONFIG_SYS_LONGHELP /* undef to save memory */
832 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
833 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
834 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
835 #ifdef CONFIG_CMD_KGDB
836 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
838 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
840 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
841 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
842 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
845 * For booting Linux, the board info and command line data
846 * have to be in the first 64 MB of memory, since this is
847 * the maximum mapped by the Linux kernel during initialization.
849 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
850 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
852 #ifdef CONFIG_CMD_KGDB
853 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
857 * Dynamic MTD Partition support with mtdparts
859 #ifndef CONFIG_SYS_NO_FLASH
860 #define CONFIG_MTD_DEVICE
861 #define CONFIG_MTD_PARTITIONS
862 #define CONFIG_CMD_MTDPARTS
863 #define CONFIG_FLASH_CFI_MTD
864 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
866 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
867 "128k(dtb),96m(fs),-(user);"\
868 "fff800000.flash:2m(uboot),9m(kernel),"\
869 "128k(dtb),96m(fs),-(user);spife110000.0:" \
870 "2m(uboot),9m(kernel),128k(dtb),-(user)"
874 * Environment Configuration
876 #define CONFIG_ROOTPATH "/opt/nfsroot"
877 #define CONFIG_BOOTFILE "uImage"
878 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
880 /* default location for tftp and bootm */
881 #define CONFIG_LOADADDR 1000000
884 #define CONFIG_BAUDRATE 115200
886 #define __USB_PHY_TYPE utmi
887 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
889 #ifdef CONFIG_T1040RDB
890 #define FDTFILE "t1040rdb/t1040rdb.dtb"
891 #elif defined(CONFIG_T1042RDB_PI)
892 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
893 #elif defined(CONFIG_T1042RDB)
894 #define FDTFILE "t1042rdb/t1042rdb.dtb"
895 #elif defined(CONFIG_T1040D4RDB)
896 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
897 #elif defined(CONFIG_T1042D4RDB)
898 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
901 #ifdef CONFIG_FSL_DIU_FB
902 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
904 #define DIU_ENVIRONMENT
907 #define CONFIG_EXTRA_ENV_SETTINGS \
908 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
909 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
910 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
912 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
913 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
914 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
915 "tftpflash=tftpboot $loadaddr $uboot && " \
916 "protect off $ubootaddr +$filesize && " \
917 "erase $ubootaddr +$filesize && " \
918 "cp.b $loadaddr $ubootaddr $filesize && " \
919 "protect on $ubootaddr +$filesize && " \
920 "cmp.b $loadaddr $ubootaddr $filesize\0" \
921 "consoledev=ttyS0\0" \
922 "ramdiskaddr=2000000\0" \
923 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
924 "fdtaddr=1e00000\0" \
925 "fdtfile=" __stringify(FDTFILE) "\0" \
928 #define CONFIG_LINUX \
929 "setenv bootargs root=/dev/ram rw " \
930 "console=$consoledev,$baudrate $othbootargs;" \
931 "setenv ramdiskaddr 0x02000000;" \
932 "setenv fdtaddr 0x00c00000;" \
933 "setenv loadaddr 0x1000000;" \
934 "bootm $loadaddr $ramdiskaddr $fdtaddr"
936 #define CONFIG_HDBOOT \
937 "setenv bootargs root=/dev/$bdev rw " \
938 "console=$consoledev,$baudrate $othbootargs;" \
939 "tftp $loadaddr $bootfile;" \
940 "tftp $fdtaddr $fdtfile;" \
941 "bootm $loadaddr - $fdtaddr"
943 #define CONFIG_NFSBOOTCOMMAND \
944 "setenv bootargs root=/dev/nfs rw " \
945 "nfsroot=$serverip:$rootpath " \
946 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
947 "console=$consoledev,$baudrate $othbootargs;" \
948 "tftp $loadaddr $bootfile;" \
949 "tftp $fdtaddr $fdtfile;" \
950 "bootm $loadaddr - $fdtaddr"
952 #define CONFIG_RAMBOOTCOMMAND \
953 "setenv bootargs root=/dev/ram rw " \
954 "console=$consoledev,$baudrate $othbootargs;" \
955 "tftp $ramdiskaddr $ramdiskfile;" \
956 "tftp $loadaddr $bootfile;" \
957 "tftp $fdtaddr $fdtfile;" \
958 "bootm $loadaddr $ramdiskaddr $fdtaddr"
960 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
962 #include <asm/fsl_secure_boot.h>
964 #endif /* __CONFIG_H */