include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * T104x RDB board configuration file
  11  */
  12 #include <asm/config_mpc85xx.h>
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15
  16 #ifndef CONFIG_SECURE_BOOT
  17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  18 #else
  19 #define CONFIG_SYS_FSL_PBL_PBI \
  20                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  21 #endif
  22
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #ifdef CONFIG_SPL_BUILD
  27 #define CONFIG_SPL_SKIP_RELOCATE
  28 #define CONFIG_SPL_COMMON_INIT_DDR
  29 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  30 #endif
  31 #define RESET_VECTOR_OFFSET             0x27FFC
  32 #define BOOT_PAGE_OFFSET                0x27000
  33
  34 #ifdef CONFIG_NAND
  35 #ifdef CONFIG_SECURE_BOOT
  36 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  37 /*
  38  * HDR would be appended at end of image and copied to DDR along
  39  * with U-Boot image.
  40  */
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  42                                          CONFIG_U_BOOT_HDR_SIZE)
  43 #else
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #endif
  46 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  47 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  48 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  49 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  50 #ifdef CONFIG_TARGET_T1040RDB
  51 #define CONFIG_SYS_FSL_PBL_RCW \
  52 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  53 #endif
  54 #ifdef CONFIG_TARGET_T1042RDB_PI
  55 #define CONFIG_SYS_FSL_PBL_RCW \
  56 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  57 #endif
  58 #ifdef CONFIG_TARGET_T1042RDB
  59 #define CONFIG_SYS_FSL_PBL_RCW \
  60 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  61 #endif
  62 #ifdef CONFIG_TARGET_T1040D4RDB
  63 #define CONFIG_SYS_FSL_PBL_RCW \
  64 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  65 #endif
  66 #ifdef CONFIG_TARGET_T1042D4RDB
  67 #define CONFIG_SYS_FSL_PBL_RCW \
  68 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  69 #endif
  70 #define CONFIG_SPL_NAND_BOOT
  71 #endif
  72
  73 #ifdef CONFIG_SPIFLASH
  74 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  75 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  80 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #ifdef CONFIG_TARGET_T1040RDB
  85 #define CONFIG_SYS_FSL_PBL_RCW \
  86 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  87 #endif
  88 #ifdef CONFIG_TARGET_T1042RDB_PI
  89 #define CONFIG_SYS_FSL_PBL_RCW \
  90 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  91 #endif
  92 #ifdef CONFIG_TARGET_T1042RDB
  93 #define CONFIG_SYS_FSL_PBL_RCW \
  94 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  95 #endif
  96 #ifdef CONFIG_TARGET_T1040D4RDB
  97 #define CONFIG_SYS_FSL_PBL_RCW \
  98 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
  99 #endif
 100 #ifdef CONFIG_TARGET_T1042D4RDB
 101 #define CONFIG_SYS_FSL_PBL_RCW \
 102 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 103 #endif
 104 #define CONFIG_SPL_SPI_BOOT
 105 #endif
 106
 107 #ifdef CONFIG_SDCARD
 108 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 109 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 110 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 111 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 112 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 113 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 114 #ifndef CONFIG_SPL_BUILD
 115 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 116 #endif
 117 #ifdef CONFIG_TARGET_T1040RDB
 118 #define CONFIG_SYS_FSL_PBL_RCW \
 119 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 120 #endif
 121 #ifdef CONFIG_TARGET_T1042RDB_PI
 122 #define CONFIG_SYS_FSL_PBL_RCW \
 123 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 124 #endif
 125 #ifdef CONFIG_TARGET_T1042RDB
 126 #define CONFIG_SYS_FSL_PBL_RCW \
 127 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 128 #endif
 129 #ifdef CONFIG_TARGET_T1040D4RDB
 130 #define CONFIG_SYS_FSL_PBL_RCW \
 131 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 132 #endif
 133 #ifdef CONFIG_TARGET_T1042D4RDB
 134 #define CONFIG_SYS_FSL_PBL_RCW \
 135 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 136 #endif
 137 #define CONFIG_SPL_MMC_BOOT
 138 #endif
 139
 140 #endif
 141
 142 /* High Level Configuration Options */
 143 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 144
 145 /* support deep sleep */
 146 #define CONFIG_DEEP_SLEEP
 147
 148 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 149 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 150 #endif
 151
 152 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 153 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 154 #define CONFIG_PCI_INDIRECT_BRIDGE
 155 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 156 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 157 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 158 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 159
 160 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 161 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 162
 163 #define CONFIG_ENV_OVERWRITE
 164
 165 #if defined(CONFIG_SPIFLASH)
 166 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 167 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 168 #define CONFIG_ENV_SECT_SIZE            0x10000
 169 #elif defined(CONFIG_SDCARD)
 170 #define CONFIG_SYS_MMC_ENV_DEV          0
 171 #define CONFIG_ENV_SIZE                 0x2000
 172 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 173 #elif defined(CONFIG_NAND)
 174 #ifdef CONFIG_SECURE_BOOT
 175 #define CONFIG_RAMBOOT_NAND
 176 #define CONFIG_BOOTSCRIPT_COPY_RAM
 177 #endif
 178 #define CONFIG_ENV_SIZE                 0x2000
 179 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 180 #else
 181 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 182 #define CONFIG_ENV_SIZE         0x2000
 183 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 184 #endif
 185
 186 #define CONFIG_SYS_CLK_FREQ     100000000
 187 #define CONFIG_DDR_CLK_FREQ     66666666
 188
 189 /*
 190  * These can be toggled for performance analysis, otherwise use default.
 191  */
 192 #define CONFIG_SYS_CACHE_STASHING
 193 #define CONFIG_BACKSIDE_L2_CACHE
 194 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 195 #define CONFIG_BTB                      /* toggle branch predition */
 196 #define CONFIG_DDR_ECC
 197 #ifdef CONFIG_DDR_ECC
 198 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 199 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 200 #endif
 201
 202 #define CONFIG_ENABLE_36BIT_PHYS
 203
 204 #define CONFIG_ADDR_MAP
 205 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 206
 207 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 208 #define CONFIG_SYS_MEMTEST_END          0x00400000
 209
 210 /*
 211  *  Config the L3 Cache as L3 SRAM
 212  */
 213 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 214 /*
 215  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 216  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 217  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 218  */
 219 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 220 #define CONFIG_SYS_L3_SIZE              256 << 10
 221 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 222 #ifdef CONFIG_RAMBOOT_PBL
 223 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 224 #endif
 225 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 226 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 227 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 228
 229 #define CONFIG_SYS_DCSRBAR              0xf0000000
 230 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 231
 232 /*
 233  * DDR Setup
 234  */
 235 #define CONFIG_VERY_BIG_RAM
 236 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 237 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 238
 239 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 240 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 241
 242 #define CONFIG_DDR_SPD
 243
 244 #define CONFIG_SYS_SPD_BUS_NUM  0
 245 #define SPD_EEPROM_ADDRESS      0x51
 246
 247 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 248
 249 /*
 250  * IFC Definitions
 251  */
 252 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 253 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 254
 255 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 256 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 257                                 CSPR_PORT_SIZE_16 | \
 258                                 CSPR_MSEL_NOR | \
 259                                 CSPR_V)
 260 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 261
 262 /*
 263  * TDM Definition
 264  */
 265 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 266
 267 /* NOR Flash Timing Params */
 268 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 269 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 270                                 FTIM0_NOR_TEADC(0x5) | \
 271                                 FTIM0_NOR_TEAHC(0x5))
 272 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 273                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 274                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 275 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 276                                 FTIM2_NOR_TCH(0x4) | \
 277                                 FTIM2_NOR_TWPH(0x0E) | \
 278                                 FTIM2_NOR_TWP(0x1c))
 279 #define CONFIG_SYS_NOR_FTIM3    0x0
 280
 281 #define CONFIG_SYS_FLASH_QUIET_TEST
 282 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 283
 284 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 285 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 286 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 287 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 288
 289 #define CONFIG_SYS_FLASH_EMPTY_INFO
 290 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 291
 292 /* CPLD on IFC */
 293 #define CPLD_LBMAP_MASK                 0x3F
 294 #define CPLD_BANK_SEL_MASK              0x07
 295 #define CPLD_BANK_OVERRIDE              0x40
 296 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 297 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 298 #define CPLD_LBMAP_RESET                0xFF
 299 #define CPLD_LBMAP_SHIFT                0x03
 300
 301 #if defined(CONFIG_TARGET_T1042RDB_PI)
 302 #define CPLD_DIU_SEL_DFP                0x80
 303 #elif defined(CONFIG_TARGET_T1042D4RDB)
 304 #define CPLD_DIU_SEL_DFP                0xc0
 305 #endif
 306
 307 #if defined(CONFIG_TARGET_T1040D4RDB)
 308 #define CPLD_INT_MASK_ALL               0xFF
 309 #define CPLD_INT_MASK_THERM             0x80
 310 #define CPLD_INT_MASK_DVI_DFP           0x40
 311 #define CPLD_INT_MASK_QSGMII1           0x20
 312 #define CPLD_INT_MASK_QSGMII2           0x10
 313 #define CPLD_INT_MASK_SGMI1             0x08
 314 #define CPLD_INT_MASK_SGMI2             0x04
 315 #define CPLD_INT_MASK_TDMR1             0x02
 316 #define CPLD_INT_MASK_TDMR2             0x01
 317 #endif
 318
 319 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 320 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 321 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 322 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 323                                 | CSPR_PORT_SIZE_8 \
 324                                 | CSPR_MSEL_GPCM \
 325                                 | CSPR_V)
 326 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 327 #define CONFIG_SYS_CSOR2        0x0
 328 /* CPLD Timing parameters for IFC CS2 */
 329 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 330                                         FTIM0_GPCM_TEADC(0x0e) | \
 331                                         FTIM0_GPCM_TEAHC(0x0e))
 332 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 333                                         FTIM1_GPCM_TRAD(0x1f))
 334 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 335                                         FTIM2_GPCM_TCH(0x8) | \
 336                                         FTIM2_GPCM_TWP(0x1f))
 337 #define CONFIG_SYS_CS2_FTIM3            0x0
 338
 339 /* NAND Flash on IFC */
 340 #define CONFIG_NAND_FSL_IFC
 341 #define CONFIG_SYS_NAND_BASE            0xff800000
 342 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 343
 344 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 345 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 346                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 347                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 348                                 | CSPR_V)
 349 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 350
 351 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 352                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 353                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 354                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 355                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 356                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 357                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 358
 359 #define CONFIG_SYS_NAND_ONFI_DETECTION
 360
 361 /* ONFI NAND Flash mode0 Timing Params */
 362 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 363                                         FTIM0_NAND_TWP(0x18)   | \
 364                                         FTIM0_NAND_TWCHT(0x07) | \
 365                                         FTIM0_NAND_TWH(0x0a))
 366 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 367                                         FTIM1_NAND_TWBE(0x39)  | \
 368                                         FTIM1_NAND_TRR(0x0e)   | \
 369                                         FTIM1_NAND_TRP(0x18))
 370 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 371                                         FTIM2_NAND_TREH(0x0a) | \
 372                                         FTIM2_NAND_TWHRE(0x1e))
 373 #define CONFIG_SYS_NAND_FTIM3           0x0
 374
 375 #define CONFIG_SYS_NAND_DDR_LAW         11
 376 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 377 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 378
 379 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 380
 381 #if defined(CONFIG_NAND)
 382 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 383 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 384 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 385 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 386 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 387 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 388 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 389 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 390 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 391 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 392 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 393 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 394 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 395 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 396 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 397 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 398 #else
 399 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 400 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 401 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 402 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 403 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 404 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 405 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 406 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 407 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 408 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 409 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 410 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 411 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 412 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 413 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 414 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 415 #endif
 416
 417 #ifdef CONFIG_SPL_BUILD
 418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 419 #else
 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 421 #endif
 422
 423 #if defined(CONFIG_RAMBOOT_PBL)
 424 #define CONFIG_SYS_RAMBOOT
 425 #endif
 426
 427 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 428 #if defined(CONFIG_NAND)
 429 #define CONFIG_A008044_WORKAROUND
 430 #endif
 431 #endif
 432
 433 #define CONFIG_HWCONFIG
 434
 435 /* define to use L1 as initial stack */
 436 #define CONFIG_L1_INIT_RAM
 437 #define CONFIG_SYS_INIT_RAM_LOCK
 438 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 441 /* The assembler doesn't like typecast */
 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 443         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 444           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 445 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 446
 447 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 448                                         GENERATED_GBL_DATA_SIZE)
 449 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 450
 451 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 452 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 453
 454 /* Serial Port - controlled on board with jumper J8
 455  * open - index 2
 456  * shorted - index 1
 457  */
 458 #define CONFIG_SYS_NS16550_SERIAL
 459 #define CONFIG_SYS_NS16550_REG_SIZE     1
 460 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 461
 462 #define CONFIG_SYS_BAUDRATE_TABLE       \
 463         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 464
 465 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 466 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 467 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 468 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 469
 470 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 471 /* Video */
 472 #define CONFIG_FSL_DIU_FB
 473
 474 #ifdef CONFIG_FSL_DIU_FB
 475 #define CONFIG_FSL_DIU_CH7301
 476 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 477 #define CONFIG_VIDEO_LOGO
 478 #define CONFIG_VIDEO_BMP_LOGO
 479 #endif
 480 #endif
 481
 482 /* I2C */
 483 #define CONFIG_SYS_I2C
 484 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 485 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 486 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 487 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 488 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 489 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 490 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 491 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 492 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 493 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 494 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 495 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 496 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 497
 498 /* I2C bus multiplexer */
 499 #define I2C_MUX_PCA_ADDR                0x70
 500 #define I2C_MUX_CH_DEFAULT      0x8
 501
 502 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 503         defined(CONFIG_TARGET_T1040D4RDB)       || \
 504         defined(CONFIG_TARGET_T1042D4RDB)
 505 /* LDI/DVI Encoder for display */
 506 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 507 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 508
 509 /*
 510  * RTC configuration
 511  */
 512 #define RTC
 513 #define CONFIG_RTC_DS1337               1
 514 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 515
 516 /*DVI encoder*/
 517 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 518 #endif
 519
 520 /*
 521  * eSPI - Enhanced SPI
 522  */
 523
 524 /*
 525  * General PCI
 526  * Memory space is mapped 1-1, but I/O space must start from 0.
 527  */
 528
 529 #ifdef CONFIG_PCI
 530 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 531 #ifdef CONFIG_PCIE1
 532 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 533 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 534 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 535 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 536 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 537 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 538 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 539 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 540 #endif
 541
 542 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 543 #ifdef CONFIG_PCIE2
 544 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 545 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 546 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 547 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 548 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 549 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 550 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 551 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 552 #endif
 553
 554 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 555 #ifdef CONFIG_PCIE3
 556 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 557 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 558 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 559 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 560 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 561 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 562 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 563 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 564 #endif
 565
 566 /* controller 4, Base address 203000 */
 567 #ifdef CONFIG_PCIE4
 568 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 569 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 570 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 571 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 572 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 573 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 574 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 575 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 576 #endif
 577
 578 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 579 #endif  /* CONFIG_PCI */
 580
 581 /* SATA */
 582 #define CONFIG_FSL_SATA_V2
 583 #ifdef CONFIG_FSL_SATA_V2
 584 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 585 #define CONFIG_SATA1
 586 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 587 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 588
 589 #define CONFIG_LBA48
 590 #endif
 591
 592 /*
 593 * USB
 594 */
 595 #define CONFIG_HAS_FSL_DR_USB
 596
 597 #ifdef CONFIG_HAS_FSL_DR_USB
 598 #ifdef CONFIG_USB_EHCI_HCD
 599 #define CONFIG_USB_EHCI_FSL
 600 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 601 #endif
 602 #endif
 603
 604 #ifdef CONFIG_MMC
 605 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 606 #endif
 607
 608 /* Qman/Bman */
 609 #ifndef CONFIG_NOBQFMAN
 610 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 611 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 612 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 613 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 614 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 615 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 616 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 617 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 618 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 619                                         CONFIG_SYS_BMAN_CENA_SIZE)
 620 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 621 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 622 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 623 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 624 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 625 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 626 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 627 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 628 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 629 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 630 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 631                                         CONFIG_SYS_QMAN_CENA_SIZE)
 632 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 633 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 634
 635 #define CONFIG_SYS_DPAA_FMAN
 636 #define CONFIG_SYS_DPAA_PME
 637
 638 #define CONFIG_QE
 639 #define CONFIG_U_QE
 640
 641 /* Default address of microcode for the Linux Fman driver */
 642 #if defined(CONFIG_SPIFLASH)
 643 /*
 644  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 645  * env, so we got 0x110000.
 646  */
 647 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 648 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 649 #elif defined(CONFIG_SDCARD)
 650 /*
 651  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 652  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 653  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 654  */
 655 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 656 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 657 #elif defined(CONFIG_NAND)
 658 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 659 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 660 #else
 661 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 662 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 663 #endif
 664
 665 #if defined(CONFIG_SPIFLASH)
 666 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 667 #elif defined(CONFIG_SDCARD)
 668 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 669 #elif defined(CONFIG_NAND)
 670 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 671 #else
 672 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 673 #endif
 674
 675 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 676 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 677 #endif /* CONFIG_NOBQFMAN */
 678
 679 #ifdef CONFIG_SYS_DPAA_FMAN
 680 #define CONFIG_FMAN_ENET
 681 #define CONFIG_PHY_VITESSE
 682 #define CONFIG_PHY_REALTEK
 683 #endif
 684
 685 #ifdef CONFIG_FMAN_ENET
 686 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 687 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 688 #elif defined(CONFIG_TARGET_T1040D4RDB)
 689 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 690 #elif defined(CONFIG_TARGET_T1042D4RDB)
 691 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 692 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 693 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 694 #endif
 695
 696 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 697 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 698 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 699 #else
 700 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 701 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 702 #endif
 703
 704 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 705 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 706 #define CONFIG_VSC9953
 707 #ifdef CONFIG_TARGET_T1040RDB
 708 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 709 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 710 #else
 711 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 712 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 713 #endif
 714 #endif
 715
 716 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 717 #endif
 718
 719 /*
 720  * Environment
 721  */
 722 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 723 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 724
 725 /*
 726  * Miscellaneous configurable options
 727  */
 728 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 729
 730 /*
 731  * For booting Linux, the board info and command line data
 732  * have to be in the first 64 MB of memory, since this is
 733  * the maximum mapped by the Linux kernel during initialization.
 734  */
 735 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 736 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 737
 738 #ifdef CONFIG_CMD_KGDB
 739 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 740 #endif
 741
 742 /*
 743  * Dynamic MTD Partition support with mtdparts
 744  */
 745
 746 /*
 747  * Environment Configuration
 748  */
 749 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 750 #define CONFIG_BOOTFILE         "uImage"
 751 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 752
 753 /* default location for tftp and bootm */
 754 #define CONFIG_LOADADDR         1000000
 755
 756 #define __USB_PHY_TYPE  utmi
 757 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 758
 759 #ifdef CONFIG_TARGET_T1040RDB
 760 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 761 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 762 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 763 #elif defined(CONFIG_TARGET_T1042RDB)
 764 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 765 #elif defined(CONFIG_TARGET_T1040D4RDB)
 766 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 767 #elif defined(CONFIG_TARGET_T1042D4RDB)
 768 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 769 #endif
 770
 771 #ifdef CONFIG_FSL_DIU_FB
 772 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 773 #else
 774 #define DIU_ENVIRONMENT
 775 #endif
 776
 777 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 778         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 779         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 780         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 781         "netdev=eth0\0"                                         \
 782         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 783         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 784         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 785         "tftpflash=tftpboot $loadaddr $uboot && "               \
 786         "protect off $ubootaddr +$filesize && "                 \
 787         "erase $ubootaddr +$filesize && "                       \
 788         "cp.b $loadaddr $ubootaddr $filesize && "               \
 789         "protect on $ubootaddr +$filesize && "                  \
 790         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 791         "consoledev=ttyS0\0"                                    \
 792         "ramdiskaddr=2000000\0"                                 \
 793         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 794         "fdtaddr=1e00000\0"                                     \
 795         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 796         "bdev=sda3\0"
 797
 798 #define CONFIG_LINUX                       \
 799         "setenv bootargs root=/dev/ram rw "            \
 800         "console=$consoledev,$baudrate $othbootargs;"  \
 801         "setenv ramdiskaddr 0x02000000;"               \
 802         "setenv fdtaddr 0x00c00000;"                   \
 803         "setenv loadaddr 0x1000000;"                   \
 804         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 805
 806 #define CONFIG_HDBOOT                                   \
 807         "setenv bootargs root=/dev/$bdev rw "           \
 808         "console=$consoledev,$baudrate $othbootargs;"   \
 809         "tftp $loadaddr $bootfile;"                     \
 810         "tftp $fdtaddr $fdtfile;"                       \
 811         "bootm $loadaddr - $fdtaddr"
 812
 813 #define CONFIG_NFSBOOTCOMMAND                   \
 814         "setenv bootargs root=/dev/nfs rw "     \
 815         "nfsroot=$serverip:$rootpath "          \
 816         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 817         "console=$consoledev,$baudrate $othbootargs;"   \
 818         "tftp $loadaddr $bootfile;"             \
 819         "tftp $fdtaddr $fdtfile;"               \
 820         "bootm $loadaddr - $fdtaddr"
 821
 822 #define CONFIG_RAMBOOTCOMMAND                           \
 823         "setenv bootargs root=/dev/ram rw "             \
 824         "console=$consoledev,$baudrate $othbootargs;"   \
 825         "tftp $ramdiskaddr $ramdiskfile;"               \
 826         "tftp $loadaddr $bootfile;"                     \
 827         "tftp $fdtaddr $fdtfile;"                       \
 828         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 829
 830 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 831
 832 #include <asm/fsl_secure_boot.h>
 833
 834 #endif  /* __CONFIG_H */