1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_PAD_TO 0x40000
20 #define CONFIG_SPL_MAX_SIZE 0x28000
21 #ifdef CONFIG_SPL_BUILD
22 #define CONFIG_SPL_SKIP_RELOCATE
23 #define CONFIG_SPL_COMMON_INIT_DDR
24 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
29 #ifdef CONFIG_MTD_RAW_NAND
30 #ifdef CONFIG_NXP_ESBC
31 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
33 * HDR would be appended at end of image and copied to DDR along
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
37 CONFIG_U_BOOT_HDR_SIZE)
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
41 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
42 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
45 #ifdef CONFIG_SPIFLASH
46 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
47 #define CONFIG_SPL_SPI_FLASH_MINIMAL
48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
52 #ifndef CONFIG_SPL_BUILD
53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
59 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
60 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
61 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
62 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
63 #ifndef CONFIG_SPL_BUILD
64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
70 /* High Level Configuration Options */
71 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
73 /* support deep sleep */
74 #define CONFIG_DEEP_SLEEP
76 #ifndef CONFIG_RESET_VECTOR_ADDRESS
77 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
80 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
81 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
82 #define CONFIG_PCIE1 /* PCIE controller 1 */
83 #define CONFIG_PCIE2 /* PCIE controller 2 */
84 #define CONFIG_PCIE3 /* PCIE controller 3 */
85 #define CONFIG_PCIE4 /* PCIE controller 4 */
87 #if defined(CONFIG_SPIFLASH)
88 #elif defined(CONFIG_MTD_RAW_NAND)
89 #ifdef CONFIG_NXP_ESBC
90 #define CONFIG_RAMBOOT_NAND
91 #define CONFIG_BOOTSCRIPT_COPY_RAM
96 * These can be toggled for performance analysis, otherwise use default.
98 #define CONFIG_SYS_CACHE_STASHING
99 #define CONFIG_BACKSIDE_L2_CACHE
100 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
101 #ifdef CONFIG_DDR_ECC
102 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
105 #define CONFIG_ENABLE_36BIT_PHYS
108 * Config the L3 Cache as L3 SRAM
110 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
112 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
113 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
114 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
116 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
117 #define CONFIG_SYS_L3_SIZE 256 << 10
118 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
119 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
120 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
121 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
122 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
124 #define CONFIG_SYS_DCSRBAR 0xf0000000
125 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
130 #define CONFIG_VERY_BIG_RAM
131 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
134 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
135 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
137 #define CONFIG_SYS_SPD_BUS_NUM 0
138 #define SPD_EEPROM_ADDRESS 0x51
140 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
145 #define CONFIG_SYS_FLASH_BASE 0xe8000000
146 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
148 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
149 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
150 CSPR_PORT_SIZE_16 | \
153 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
158 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
160 /* NOR Flash Timing Params */
161 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
162 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
163 FTIM0_NOR_TEADC(0x5) | \
164 FTIM0_NOR_TEAHC(0x5))
165 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
166 FTIM1_NOR_TRAD_NOR(0x1A) |\
167 FTIM1_NOR_TSEQRAD_NOR(0x13))
168 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
169 FTIM2_NOR_TCH(0x4) | \
170 FTIM2_NOR_TWPH(0x0E) | \
172 #define CONFIG_SYS_NOR_FTIM3 0x0
174 #define CONFIG_SYS_FLASH_QUIET_TEST
175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
177 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
178 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
179 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181 #define CONFIG_SYS_FLASH_EMPTY_INFO
182 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
185 #define CPLD_LBMAP_MASK 0x3F
186 #define CPLD_BANK_SEL_MASK 0x07
187 #define CPLD_BANK_OVERRIDE 0x40
188 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
189 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
190 #define CPLD_LBMAP_RESET 0xFF
191 #define CPLD_LBMAP_SHIFT 0x03
193 #if defined(CONFIG_TARGET_T1042RDB_PI)
194 #define CPLD_DIU_SEL_DFP 0x80
195 #elif defined(CONFIG_TARGET_T1042D4RDB)
196 #define CPLD_DIU_SEL_DFP 0xc0
199 #if defined(CONFIG_TARGET_T1040D4RDB)
200 #define CPLD_INT_MASK_ALL 0xFF
201 #define CPLD_INT_MASK_THERM 0x80
202 #define CPLD_INT_MASK_DVI_DFP 0x40
203 #define CPLD_INT_MASK_QSGMII1 0x20
204 #define CPLD_INT_MASK_QSGMII2 0x10
205 #define CPLD_INT_MASK_SGMI1 0x08
206 #define CPLD_INT_MASK_SGMI2 0x04
207 #define CPLD_INT_MASK_TDMR1 0x02
208 #define CPLD_INT_MASK_TDMR2 0x01
211 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
212 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
213 #define CONFIG_SYS_CSPR2_EXT (0xf)
214 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
218 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
219 #define CONFIG_SYS_CSOR2 0x0
220 /* CPLD Timing parameters for IFC CS2 */
221 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
222 FTIM0_GPCM_TEADC(0x0e) | \
223 FTIM0_GPCM_TEAHC(0x0e))
224 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
225 FTIM1_GPCM_TRAD(0x1f))
226 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
227 FTIM2_GPCM_TCH(0x8) | \
228 FTIM2_GPCM_TWP(0x1f))
229 #define CONFIG_SYS_CS2_FTIM3 0x0
231 /* NAND Flash on IFC */
232 #define CONFIG_SYS_NAND_BASE 0xff800000
233 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
235 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
236 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
237 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
238 | CSPR_MSEL_NAND /* MSEL = NAND */ \
240 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
242 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
243 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
244 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
245 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
246 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
247 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
248 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
250 /* ONFI NAND Flash mode0 Timing Params */
251 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
252 FTIM0_NAND_TWP(0x18) | \
253 FTIM0_NAND_TWCHT(0x07) | \
254 FTIM0_NAND_TWH(0x0a))
255 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
256 FTIM1_NAND_TWBE(0x39) | \
257 FTIM1_NAND_TRR(0x0e) | \
258 FTIM1_NAND_TRP(0x18))
259 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
260 FTIM2_NAND_TREH(0x0a) | \
261 FTIM2_NAND_TWHRE(0x1e))
262 #define CONFIG_SYS_NAND_FTIM3 0x0
264 #define CONFIG_SYS_NAND_DDR_LAW 11
265 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
266 #define CONFIG_SYS_MAX_NAND_DEVICE 1
268 #if defined(CONFIG_MTD_RAW_NAND)
269 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
270 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
271 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
272 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
273 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
274 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
275 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
276 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
277 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
279 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
280 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
281 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
282 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
283 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
284 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
286 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
287 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
288 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
289 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
290 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
291 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
292 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
293 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
294 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
295 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
296 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
297 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
298 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
299 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
300 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
301 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
304 #ifdef CONFIG_SPL_BUILD
305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
307 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
310 #if defined(CONFIG_RAMBOOT_PBL)
311 #define CONFIG_SYS_RAMBOOT
314 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
315 #if defined(CONFIG_MTD_RAW_NAND)
316 #define CONFIG_A008044_WORKAROUND
320 #define CONFIG_HWCONFIG
322 /* define to use L1 as initial stack */
323 #define CONFIG_L1_INIT_RAM
324 #define CONFIG_SYS_INIT_RAM_LOCK
325 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
328 /* The assembler doesn't like typecast */
329 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
330 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
331 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
332 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
334 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
335 GENERATED_GBL_DATA_SIZE)
336 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
338 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
340 /* Serial Port - controlled on board with jumper J8
344 #define CONFIG_SYS_NS16550_SERIAL
345 #define CONFIG_SYS_NS16550_REG_SIZE 1
346 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
348 #define CONFIG_SYS_BAUDRATE_TABLE \
349 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
351 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
352 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
353 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
354 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
356 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
358 #define CONFIG_FSL_DIU_FB
360 #ifdef CONFIG_FSL_DIU_FB
361 #define CONFIG_FSL_DIU_CH7301
362 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
363 #define CONFIG_VIDEO_BMP_LOGO
369 /* I2C bus multiplexer */
370 #define I2C_MUX_PCA_ADDR 0x70
371 #define I2C_MUX_CH_DEFAULT 0x8
373 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
374 defined(CONFIG_TARGET_T1040D4RDB) || \
375 defined(CONFIG_TARGET_T1042D4RDB)
376 /* LDI/DVI Encoder for display */
377 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
378 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
379 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
385 #define CONFIG_RTC_DS1337 1
386 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
389 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
393 * eSPI - Enhanced SPI
398 * Memory space is mapped 1-1, but I/O space must start from 0.
402 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
404 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
405 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
406 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
407 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
410 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
412 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
415 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
418 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
420 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
421 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
422 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
423 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
426 /* controller 4, Base address 203000 */
428 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
429 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
430 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
431 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
434 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
435 #endif /* CONFIG_PCI */
438 #define CONFIG_FSL_SATA_V2
439 #ifdef CONFIG_FSL_SATA_V2
441 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
442 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
450 #define CONFIG_HAS_FSL_DR_USB
452 #ifdef CONFIG_HAS_FSL_DR_USB
453 #ifdef CONFIG_USB_EHCI_HCD
454 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
459 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
463 #ifndef CONFIG_NOBQFMAN
464 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
465 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
466 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
467 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
468 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
469 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
470 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
471 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
472 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
473 CONFIG_SYS_BMAN_CENA_SIZE)
474 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
475 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
476 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
477 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
478 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
479 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
480 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
481 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
482 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
483 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
484 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
485 CONFIG_SYS_QMAN_CENA_SIZE)
486 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
487 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
489 #define CONFIG_SYS_DPAA_FMAN
490 #define CONFIG_SYS_DPAA_PME
492 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
493 #endif /* CONFIG_NOBQFMAN */
495 #ifdef CONFIG_FMAN_ENET
496 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
497 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
498 #elif defined(CONFIG_TARGET_T1040D4RDB)
499 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
500 #elif defined(CONFIG_TARGET_T1042D4RDB)
501 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
502 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
503 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
506 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
507 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
508 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
510 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
511 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
514 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
515 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
516 #define CONFIG_VSC9953
517 #ifdef CONFIG_TARGET_T1040RDB
518 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
519 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
521 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
522 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
526 #define CONFIG_ETHPRIME "FM1@DTSEC4"
532 #define CONFIG_LOADS_ECHO /* echo on for serial download */
533 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
536 * Miscellaneous configurable options
540 * For booting Linux, the board info and command line data
541 * have to be in the first 64 MB of memory, since this is
542 * the maximum mapped by the Linux kernel during initialization.
544 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
545 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
548 * Dynamic MTD Partition support with mtdparts
552 * Environment Configuration
554 #define CONFIG_ROOTPATH "/opt/nfsroot"
555 #define CONFIG_BOOTFILE "uImage"
556 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
558 #define __USB_PHY_TYPE utmi
559 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
561 #ifdef CONFIG_TARGET_T1040RDB
562 #define FDTFILE "t1040rdb/t1040rdb.dtb"
563 #elif defined(CONFIG_TARGET_T1042RDB_PI)
564 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
565 #elif defined(CONFIG_TARGET_T1042RDB)
566 #define FDTFILE "t1042rdb/t1042rdb.dtb"
567 #elif defined(CONFIG_TARGET_T1040D4RDB)
568 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
569 #elif defined(CONFIG_TARGET_T1042D4RDB)
570 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
573 #ifdef CONFIG_FSL_DIU_FB
574 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
576 #define DIU_ENVIRONMENT
579 #define CONFIG_EXTRA_ENV_SETTINGS \
580 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
581 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
582 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
584 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
585 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
586 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
587 "tftpflash=tftpboot $loadaddr $uboot && " \
588 "protect off $ubootaddr +$filesize && " \
589 "erase $ubootaddr +$filesize && " \
590 "cp.b $loadaddr $ubootaddr $filesize && " \
591 "protect on $ubootaddr +$filesize && " \
592 "cmp.b $loadaddr $ubootaddr $filesize\0" \
593 "consoledev=ttyS0\0" \
594 "ramdiskaddr=2000000\0" \
595 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
596 "fdtaddr=1e00000\0" \
597 "fdtfile=" __stringify(FDTFILE) "\0" \
600 #include <asm/fsl_secure_boot.h>
602 #endif /* __CONFIG_H */