include/configs/T1040QDS.h

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * T1040 QDS board configuration file
  28  */
  29 #define CONFIG_T1040QDS
  30 #define CONFIG_PHYS_64BIT
  31 #define CONFIG_SYS_GENERIC_BOARD
  32 #define CONFIG_DISPLAY_BOARDINFO
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  37 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  38 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  39 #endif
  40
  41 /* High Level Configuration Options */
  42 #define CONFIG_BOOKE
  43 #define CONFIG_E500                     /* BOOKE e500 family */
  44 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  45 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  46 #define CONFIG_MP                       /* support multiple processors */
  47
  48 /* support deep sleep */
  49 #define CONFIG_DEEP_SLEEP
  50 #if defined(CONFIG_DEEP_SLEEP)
  51 #define CONFIG_SILENT_CONSOLE
  52 #define CONFIG_BOARD_EARLY_INIT_F
  53 #endif
  54
  55 #ifndef CONFIG_SYS_TEXT_BASE
  56 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  64 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  65 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  66 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  67 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  68 #define CONFIG_PCI_INDIRECT_BRIDGE
  69 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  70 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  71 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  72 #define CONFIG_PCIE4                    /* PCIE controler 4 */
  73
  74 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  75 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  76
  77 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  78
  79 #define CONFIG_ENV_OVERWRITE
  80
  81 #ifdef CONFIG_SYS_NO_FLASH
  82 #define CONFIG_ENV_IS_NOWHERE
  83 #else
  84 #define CONFIG_FLASH_CFI_DRIVER
  85 #define CONFIG_SYS_FLASH_CFI
  86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  87 #endif
  88
  89 #ifndef CONFIG_SYS_NO_FLASH
  90 #if defined(CONFIG_SPIFLASH)
  91 #define CONFIG_SYS_EXTRA_ENV_RELOC
  92 #define CONFIG_ENV_IS_IN_SPI_FLASH
  93 #define CONFIG_ENV_SPI_BUS              0
  94 #define CONFIG_ENV_SPI_CS               0
  95 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  96 #define CONFIG_ENV_SPI_MODE             0
  97 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  98 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  99 #define CONFIG_ENV_SECT_SIZE            0x10000
 100 #elif defined(CONFIG_SDCARD)
 101 #define CONFIG_SYS_EXTRA_ENV_RELOC
 102 #define CONFIG_ENV_IS_IN_MMC
 103 #define CONFIG_SYS_MMC_ENV_DEV          0
 104 #define CONFIG_ENV_SIZE                 0x2000
 105 #define CONFIG_ENV_OFFSET               (512 * 1658)
 106 #elif defined(CONFIG_NAND)
 107 #define CONFIG_SYS_EXTRA_ENV_RELOC
 108 #define CONFIG_ENV_IS_IN_NAND
 109 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 110 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 111 #else
 112 #define CONFIG_ENV_IS_IN_FLASH
 113 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 114 #define CONFIG_ENV_SIZE         0x2000
 115 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 116 #endif
 117 #else /* CONFIG_SYS_NO_FLASH */
 118 #define CONFIG_ENV_SIZE                0x2000
 119 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 120 #endif
 121
 122 #ifndef __ASSEMBLY__
 123 unsigned long get_board_sys_clk(void);
 124 unsigned long get_board_ddr_clk(void);
 125 #endif
 126
 127 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 128 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 129
 130 /*
 131  * These can be toggled for performance analysis, otherwise use default.
 132  */
 133 #define CONFIG_SYS_CACHE_STASHING
 134 #define CONFIG_BACKSIDE_L2_CACHE
 135 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 136 #define CONFIG_BTB                      /* toggle branch predition */
 137 #define CONFIG_DDR_ECC
 138 #ifdef CONFIG_DDR_ECC
 139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 140 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 141 #endif
 142
 143 #define CONFIG_ENABLE_36BIT_PHYS
 144
 145 #define CONFIG_ADDR_MAP
 146 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 147
 148 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 149 #define CONFIG_SYS_MEMTEST_END          0x00400000
 150 #define CONFIG_SYS_ALT_MEMTEST
 151 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 152
 153 /*
 154  *  Config the L3 Cache as L3 SRAM
 155  */
 156 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 157
 158 #define CONFIG_SYS_DCSRBAR              0xf0000000
 159 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 160
 161 /* EEPROM */
 162 #define CONFIG_ID_EEPROM
 163 #define CONFIG_SYS_I2C_EEPROM_NXID
 164 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 169
 170 /*
 171  * DDR Setup
 172  */
 173 #define CONFIG_VERY_BIG_RAM
 174 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 175 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 176
 177 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 178 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 179 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 180
 181 #define CONFIG_DDR_SPD
 182 #ifndef CONFIG_SYS_FSL_DDR4
 183 #define CONFIG_SYS_FSL_DDR3
 184 #endif
 185 #define CONFIG_FSL_DDR_INTERACTIVE
 186
 187 #define CONFIG_SYS_SPD_BUS_NUM  0
 188 #define SPD_EEPROM_ADDRESS      0x51
 189
 190 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 191
 192 /*
 193  * IFC Definitions
 194  */
 195 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 196 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 197
 198 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 199 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 200                                 + 0x8000000) | \
 201                                 CSPR_PORT_SIZE_16 | \
 202                                 CSPR_MSEL_NOR | \
 203                                 CSPR_V)
 204 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 205 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 206                                 CSPR_PORT_SIZE_16 | \
 207                                 CSPR_MSEL_NOR | \
 208                                 CSPR_V)
 209 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 210
 211 /*
 212  * TDM Definition
 213  */
 214 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 215
 216 /* NOR Flash Timing Params */
 217 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 218 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 219                                 FTIM0_NOR_TEADC(0x5) | \
 220                                 FTIM0_NOR_TEAHC(0x5))
 221 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 222                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 223                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 224 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 225                                 FTIM2_NOR_TCH(0x4) | \
 226                                 FTIM2_NOR_TWPH(0x0E) | \
 227                                 FTIM2_NOR_TWP(0x1c))
 228 #define CONFIG_SYS_NOR_FTIM3    0x0
 229
 230 #define CONFIG_SYS_FLASH_QUIET_TEST
 231 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 232
 233 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 235 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 236 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 237
 238 #define CONFIG_SYS_FLASH_EMPTY_INFO
 239 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 240                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 241 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 242 #define QIXIS_BASE              0xffdf0000
 243 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 244 #define QIXIS_LBMAP_SWITCH              0x06
 245 #define QIXIS_LBMAP_MASK                0x0f
 246 #define QIXIS_LBMAP_SHIFT               0
 247 #define QIXIS_LBMAP_DFLTBANK            0x00
 248 #define QIXIS_LBMAP_ALTBANK             0x04
 249 #define QIXIS_RST_CTL_RESET             0x31
 250 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 251 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 252 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 253 #define QIXIS_RST_FORCE_MEM             0x01
 254
 255 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 256 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 257                                 | CSPR_PORT_SIZE_8 \
 258                                 | CSPR_MSEL_GPCM \
 259                                 | CSPR_V)
 260 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 261 #define CONFIG_SYS_CSOR3        0x0
 262 /* QIXIS Timing parameters for IFC CS3 */
 263 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 264                                         FTIM0_GPCM_TEADC(0x0e) | \
 265                                         FTIM0_GPCM_TEAHC(0x0e))
 266 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 267                                         FTIM1_GPCM_TRAD(0x3f))
 268 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 269                                         FTIM2_GPCM_TCH(0x8) | \
 270                                         FTIM2_GPCM_TWP(0x1f))
 271 #define CONFIG_SYS_CS3_FTIM3            0x0
 272
 273 #define CONFIG_NAND_FSL_IFC
 274 #define CONFIG_SYS_NAND_BASE            0xff800000
 275 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 276
 277 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 278 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 279                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 280                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 281                                 | CSPR_V)
 282 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 283
 284 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 285                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 286                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 287                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 288                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 289                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 290                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 291
 292 #define CONFIG_SYS_NAND_ONFI_DETECTION
 293
 294 /* ONFI NAND Flash mode0 Timing Params */
 295 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 296                                         FTIM0_NAND_TWP(0x18)   | \
 297                                         FTIM0_NAND_TWCHT(0x07) | \
 298                                         FTIM0_NAND_TWH(0x0a))
 299 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 300                                         FTIM1_NAND_TWBE(0x39)  | \
 301                                         FTIM1_NAND_TRR(0x0e)   | \
 302                                         FTIM1_NAND_TRP(0x18))
 303 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 304                                         FTIM2_NAND_TREH(0x0a) | \
 305                                         FTIM2_NAND_TWHRE(0x1e))
 306 #define CONFIG_SYS_NAND_FTIM3           0x0
 307
 308 #define CONFIG_SYS_NAND_DDR_LAW         11
 309 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 310 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 311 #define CONFIG_CMD_NAND
 312
 313 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 314
 315 #if defined(CONFIG_NAND)
 316 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 317 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 318 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 319 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 320 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 321 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 322 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 323 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 324 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 325 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 326 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 327 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 328 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 329 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 330 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 331 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 332 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 333 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 334 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 335 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 336 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 337 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 338 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 339 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 340 #else
 341 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 342 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 343 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 344 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 345 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 346 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 347 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 348 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 349 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 350 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 351 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 352 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 353 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 354 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 355 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 356 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 357 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 358 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 359 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 360 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 361 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 362 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 363 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 364 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 365 #endif
 366
 367 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 368
 369 #if defined(CONFIG_RAMBOOT_PBL)
 370 #define CONFIG_SYS_RAMBOOT
 371 #endif
 372
 373 #define CONFIG_BOARD_EARLY_INIT_R
 374 #define CONFIG_MISC_INIT_R
 375
 376 #define CONFIG_HWCONFIG
 377
 378 /* define to use L1 as initial stack */
 379 #define CONFIG_L1_INIT_RAM
 380 #define CONFIG_SYS_INIT_RAM_LOCK
 381 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 384 /* The assembler doesn't like typecast */
 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 386         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 387           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 388 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 389
 390 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 391                                         GENERATED_GBL_DATA_SIZE)
 392 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 393
 394 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 395 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 396
 397 /* Serial Port - controlled on board with jumper J8
 398  * open - index 2
 399  * shorted - index 1
 400  */
 401 #define CONFIG_CONS_INDEX       1
 402 #define CONFIG_SYS_NS16550
 403 #define CONFIG_SYS_NS16550_SERIAL
 404 #define CONFIG_SYS_NS16550_REG_SIZE     1
 405 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 406
 407 #define CONFIG_SYS_BAUDRATE_TABLE       \
 408         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 409
 410 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 411 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 412 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 413 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 414 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 415
 416 /* Use the HUSH parser */
 417 #define CONFIG_SYS_HUSH_PARSER
 418 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 419
 420 /* Video */
 421 #define CONFIG_FSL_DIU_FB
 422 #ifdef CONFIG_FSL_DIU_FB
 423 #define CONFIG_FSL_DIU_CH7301
 424 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 425 #define CONFIG_VIDEO
 426 #define CONFIG_CMD_BMP
 427 #define CONFIG_CFB_CONSOLE
 428 #define CONFIG_VIDEO_SW_CURSOR
 429 #define CONFIG_VGA_AS_SINGLE_DEVICE
 430 #define CONFIG_VIDEO_LOGO
 431 #define CONFIG_VIDEO_BMP_LOGO
 432 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 433 /*
 434  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 435  * disable empty flash sector detection, which is I/O-intensive.
 436  */
 437 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 438 #endif
 439
 440 /* pass open firmware flat tree */
 441 #define CONFIG_OF_LIBFDT
 442 #define CONFIG_OF_BOARD_SETUP
 443 #define CONFIG_OF_STDOUT_VIA_ALIAS
 444
 445 /* new uImage format support */
 446 #define CONFIG_FIT
 447 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 448
 449 /* I2C */
 450 #define CONFIG_SYS_I2C
 451 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 452 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 453 #define CONFIG_SYS_FSL_I2C2_SPEED       50000
 454 #define CONFIG_SYS_FSL_I2C3_SPEED       50000
 455 #define CONFIG_SYS_FSL_I2C4_SPEED       50000
 456 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 457 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 458 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 459 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 460 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 461 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 462 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 463 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 464
 465 #define I2C_MUX_PCA_ADDR                0x77
 466 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 467
 468
 469 /* I2C bus multiplexer */
 470 #define I2C_MUX_CH_DEFAULT      0x8
 471 #define I2C_MUX_CH_DIU          0xC
 472
 473 /* LDI/DVI Encoder for display */
 474 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 475 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 476
 477 /*
 478  * RTC configuration
 479  */
 480 #define RTC
 481 #define CONFIG_RTC_DS3231               1
 482 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 483
 484 /*
 485  * eSPI - Enhanced SPI
 486  */
 487 #define CONFIG_FSL_ESPI
 488 #define CONFIG_SPI_FLASH_STMICRO
 489 #define CONFIG_SPI_FLASH_SST
 490 #define CONFIG_SPI_FLASH_EON
 491 #define CONFIG_CMD_SF
 492 #define CONFIG_SF_DEFAULT_SPEED         10000000
 493 #define CONFIG_SF_DEFAULT_MODE          0
 494
 495 /*
 496  * General PCI
 497  * Memory space is mapped 1-1, but I/O space must start from 0.
 498  */
 499
 500 #ifdef CONFIG_PCI
 501 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 502 #ifdef CONFIG_PCIE1
 503 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 504 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 505 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 506 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 507 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 508 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 509 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 510 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 511 #endif
 512
 513 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 514 #ifdef CONFIG_PCIE2
 515 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 516 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 517 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 518 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 519 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 520 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 521 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 522 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 523 #endif
 524
 525 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 526 #ifdef CONFIG_PCIE3
 527 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 528 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 529 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 530 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 531 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 532 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 533 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 534 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 535 #endif
 536
 537 /* controller 4, Base address 203000 */
 538 #ifdef CONFIG_PCIE4
 539 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 540 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 541 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 542 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 543 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 544 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 545 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 546 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 547 #endif
 548
 549 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 550 #define CONFIG_E1000
 551
 552 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 553 #define CONFIG_DOS_PARTITION
 554 #endif  /* CONFIG_PCI */
 555
 556 /* SATA */
 557 #define CONFIG_FSL_SATA_V2
 558 #ifdef CONFIG_FSL_SATA_V2
 559 #define CONFIG_LIBATA
 560 #define CONFIG_FSL_SATA
 561
 562 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 563 #define CONFIG_SATA1
 564 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 565 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 566 #define CONFIG_SATA2
 567 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 568 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 569
 570 #define CONFIG_LBA48
 571 #define CONFIG_CMD_SATA
 572 #define CONFIG_DOS_PARTITION
 573 #define CONFIG_CMD_EXT2
 574 #endif
 575
 576 /*
 577 * USB
 578 */
 579 #define CONFIG_HAS_FSL_DR_USB
 580
 581 #ifdef CONFIG_HAS_FSL_DR_USB
 582 #define CONFIG_USB_EHCI
 583
 584 #ifdef CONFIG_USB_EHCI
 585 #define CONFIG_CMD_USB
 586 #define CONFIG_USB_STORAGE
 587 #define CONFIG_USB_EHCI_FSL
 588 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 589 #define CONFIG_CMD_EXT2
 590 #endif
 591 #endif
 592
 593 #define CONFIG_MMC
 594
 595 #ifdef CONFIG_MMC
 596 #define CONFIG_FSL_ESDHC
 597 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 598 #define CONFIG_CMD_MMC
 599 #define CONFIG_GENERIC_MMC
 600 #define CONFIG_CMD_EXT2
 601 #define CONFIG_CMD_FAT
 602 #define CONFIG_DOS_PARTITION
 603 #endif
 604
 605 /* Qman/Bman */
 606 #ifndef CONFIG_NOBQFMAN
 607 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 608 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 609 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 610 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 611 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 612 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 613 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 614 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 615 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 616 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 617                                         CONFIG_SYS_BMAN_CENA_SIZE)
 618 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 619 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 620 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 621 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 622 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 623 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 624 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 625 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 626 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 627 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 628 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 629                                         CONFIG_SYS_QMAN_CENA_SIZE)
 630 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 631 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 632
 633 #define CONFIG_SYS_DPAA_FMAN
 634 #define CONFIG_SYS_DPAA_PME
 635
 636 #define CONFIG_QE
 637 #define CONFIG_U_QE
 638 /* Default address of microcode for the Linux Fman driver */
 639 #if defined(CONFIG_SPIFLASH)
 640 /*
 641  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 642  * env, so we got 0x110000.
 643  */
 644 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 645 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 646 #elif defined(CONFIG_SDCARD)
 647 /*
 648  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 649  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 650  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 651  */
 652 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 653 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 654 #elif defined(CONFIG_NAND)
 655 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 656 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 657 #else
 658 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 659 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 660 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 661 #endif
 662 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 663 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 664 #endif /* CONFIG_NOBQFMAN */
 665
 666 #ifdef CONFIG_SYS_DPAA_FMAN
 667 #define CONFIG_FMAN_ENET
 668 #define CONFIG_PHYLIB_10G
 669 #define CONFIG_PHY_VITESSE
 670 #define CONFIG_PHY_REALTEK
 671 #define CONFIG_PHY_TERANETICS
 672 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 673 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 674 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 675 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 676 #endif
 677
 678 #ifdef CONFIG_FMAN_ENET
 679 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
 680 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
 681
 682 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 683 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 684 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 685 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 686
 687 #define CONFIG_MII              /* MII PHY management */
 688 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 689 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 690 #endif
 691
 692 /* Enable VSC9953 L2 Switch driver */
 693 #define CONFIG_VSC9953
 694 #define CONFIG_VSC9953_CMD
 695 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x14
 696 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x18
 697
 698 /*
 699  * Dynamic MTD Partition support with mtdparts
 700  */
 701 #ifndef CONFIG_SYS_NO_FLASH
 702 #define CONFIG_MTD_DEVICE
 703 #define CONFIG_MTD_PARTITIONS
 704 #define CONFIG_CMD_MTDPARTS
 705 #define CONFIG_FLASH_CFI_MTD
 706 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 707                         "spi0=spife110000.0"
 708 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 709                                 "128k(dtb),96m(fs),-(user);"\
 710                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 711                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 712                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 713 #endif
 714
 715 /*
 716  * Environment
 717  */
 718 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 719 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 720
 721 /*
 722  * Command line configuration.
 723  */
 724 #define CONFIG_CMD_DATE
 725 #define CONFIG_CMD_DHCP
 726 #define CONFIG_CMD_EEPROM
 727 #define CONFIG_CMD_ELF
 728 #define CONFIG_CMD_ERRATA
 729 #define CONFIG_CMD_GREPENV
 730 #define CONFIG_CMD_IRQ
 731 #define CONFIG_CMD_I2C
 732 #define CONFIG_CMD_MII
 733 #define CONFIG_CMD_PING
 734 #define CONFIG_CMD_REGINFO
 735
 736 #ifdef CONFIG_PCI
 737 #define CONFIG_CMD_PCI
 738 #endif
 739
 740 /* Hash command with SHA acceleration supported in hardware */
 741 #ifdef CONFIG_FSL_CAAM
 742 #define CONFIG_CMD_HASH
 743 #define CONFIG_SHA_HW_ACCEL
 744 #endif
 745
 746 /*
 747  * Miscellaneous configurable options
 748  */
 749 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 750 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 751 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 752 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 753 #ifdef CONFIG_CMD_KGDB
 754 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 755 #else
 756 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 757 #endif
 758 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 759 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 760 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 761
 762 /*
 763  * For booting Linux, the board info and command line data
 764  * have to be in the first 64 MB of memory, since this is
 765  * the maximum mapped by the Linux kernel during initialization.
 766  */
 767 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 768 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 769
 770 #ifdef CONFIG_CMD_KGDB
 771 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 772 #endif
 773
 774 /*
 775  * Environment Configuration
 776  */
 777 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 778 #define CONFIG_BOOTFILE         "uImage"
 779 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 780
 781 /* default location for tftp and bootm */
 782 #define CONFIG_LOADADDR         1000000
 783
 784 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 785
 786 #define CONFIG_BAUDRATE 115200
 787
 788 #define __USB_PHY_TYPE  utmi
 789
 790 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 791         "hwconfig=fsl_ddr:bank_intlv=auto;"                     \
 792         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 793         "netdev=eth0\0"                                         \
 794         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 795         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 796         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 797         "tftpflash=tftpboot $loadaddr $uboot && "               \
 798         "protect off $ubootaddr +$filesize && "                 \
 799         "erase $ubootaddr +$filesize && "                       \
 800         "cp.b $loadaddr $ubootaddr $filesize && "               \
 801         "protect on $ubootaddr +$filesize && "                  \
 802         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 803         "consoledev=ttyS0\0"                                    \
 804         "ramdiskaddr=2000000\0"                                 \
 805         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
 806         "fdtaddr=c00000\0"                                      \
 807         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
 808         "bdev=sda3\0"
 809
 810 #define CONFIG_LINUX                       \
 811         "setenv bootargs root=/dev/ram rw "            \
 812         "console=$consoledev,$baudrate $othbootargs;"  \
 813         "setenv ramdiskaddr 0x02000000;"               \
 814         "setenv fdtaddr 0x00c00000;"                   \
 815         "setenv loadaddr 0x1000000;"                   \
 816         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 817
 818 #define CONFIG_HDBOOT                                   \
 819         "setenv bootargs root=/dev/$bdev rw "           \
 820         "console=$consoledev,$baudrate $othbootargs;"   \
 821         "tftp $loadaddr $bootfile;"                     \
 822         "tftp $fdtaddr $fdtfile;"                       \
 823         "bootm $loadaddr - $fdtaddr"
 824
 825 #define CONFIG_NFSBOOTCOMMAND                   \
 826         "setenv bootargs root=/dev/nfs rw "     \
 827         "nfsroot=$serverip:$rootpath "          \
 828         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 829         "console=$consoledev,$baudrate $othbootargs;"   \
 830         "tftp $loadaddr $bootfile;"             \
 831         "tftp $fdtaddr $fdtfile;"               \
 832         "bootm $loadaddr - $fdtaddr"
 833
 834 #define CONFIG_RAMBOOTCOMMAND                           \
 835         "setenv bootargs root=/dev/ram rw "             \
 836         "console=$consoledev,$baudrate $othbootargs;"   \
 837         "tftp $ramdiskaddr $ramdiskfile;"               \
 838         "tftp $loadaddr $bootfile;"                     \
 839         "tftp $fdtaddr $fdtfile;"                       \
 840         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 841
 842 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 843
 844 #ifdef CONFIG_SECURE_BOOT
 845 #include <asm/fsl_secure_boot.h>
 846 #define CONFIG_CMD_BLOB
 847 #endif
 848
 849 #endif  /* __CONFIG_H */