9206fe7040e34c013c95548a9da463ad811d126d
[platform/kernel/u-boot.git] / include / configs / T1040QDS.h
1 /*
2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #ifndef __CONFIG_H
24 #define __CONFIG_H
25
26 /*
27  * T1040 QDS board configuration file
28  */
29
30 #ifdef CONFIG_RAMBOOT_PBL
31 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
32 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
35 #endif
36
37 /* High Level Configuration Options */
38 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
39 #define CONFIG_MP                       /* support multiple processors */
40
41 /* support deep sleep */
42 #define CONFIG_DEEP_SLEEP
43
44 #ifndef CONFIG_SYS_TEXT_BASE
45 #define CONFIG_SYS_TEXT_BASE    0xeff40000
46 #endif
47
48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
50 #endif
51
52 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
53 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
54 #define CONFIG_PCI_INDIRECT_BRIDGE
55 #define CONFIG_PCIE1                    /* PCIE controller 1 */
56 #define CONFIG_PCIE2                    /* PCIE controller 2 */
57 #define CONFIG_PCIE3                    /* PCIE controller 3 */
58 #define CONFIG_PCIE4                    /* PCIE controller 4 */
59
60 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
61 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
62
63 #define CONFIG_ENV_OVERWRITE
64
65 #ifndef CONFIG_MTD_NOR_FLASH
66 #define CONFIG_ENV_IS_NOWHERE
67 #else
68 #define CONFIG_FLASH_CFI_DRIVER
69 #define CONFIG_SYS_FLASH_CFI
70 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
71 #endif
72
73 #ifdef CONFIG_MTD_NOR_FLASH
74 #if defined(CONFIG_SPIFLASH)
75 #define CONFIG_SYS_EXTRA_ENV_RELOC
76 #define CONFIG_ENV_IS_IN_SPI_FLASH
77 #define CONFIG_ENV_SPI_BUS              0
78 #define CONFIG_ENV_SPI_CS               0
79 #define CONFIG_ENV_SPI_MAX_HZ           10000000
80 #define CONFIG_ENV_SPI_MODE             0
81 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
82 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
83 #define CONFIG_ENV_SECT_SIZE            0x10000
84 #elif defined(CONFIG_SDCARD)
85 #define CONFIG_SYS_EXTRA_ENV_RELOC
86 #define CONFIG_ENV_IS_IN_MMC
87 #define CONFIG_SYS_MMC_ENV_DEV          0
88 #define CONFIG_ENV_SIZE                 0x2000
89 #define CONFIG_ENV_OFFSET               (512 * 1658)
90 #elif defined(CONFIG_NAND)
91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_ENV_IS_IN_NAND
93 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
94 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
95 #else
96 #define CONFIG_ENV_IS_IN_FLASH
97 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
98 #define CONFIG_ENV_SIZE         0x2000
99 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
100 #endif
101 #else /* CONFIG_MTD_NOR_FLASH */
102 #define CONFIG_ENV_SIZE                0x2000
103 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
104 #endif
105
106 #ifndef __ASSEMBLY__
107 unsigned long get_board_sys_clk(void);
108 unsigned long get_board_ddr_clk(void);
109 #endif
110
111 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
112 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
113
114 /*
115  * These can be toggled for performance analysis, otherwise use default.
116  */
117 #define CONFIG_SYS_CACHE_STASHING
118 #define CONFIG_BACKSIDE_L2_CACHE
119 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
120 #define CONFIG_BTB                      /* toggle branch predition */
121 #define CONFIG_DDR_ECC
122 #ifdef CONFIG_DDR_ECC
123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
125 #endif
126
127 #define CONFIG_ENABLE_36BIT_PHYS
128
129 #define CONFIG_ADDR_MAP
130 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
131
132 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END          0x00400000
134 #define CONFIG_SYS_ALT_MEMTEST
135 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
136
137 /*
138  *  Config the L3 Cache as L3 SRAM
139  */
140 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
141
142 #define CONFIG_SYS_DCSRBAR              0xf0000000
143 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
144
145 /* EEPROM */
146 #define CONFIG_ID_EEPROM
147 #define CONFIG_SYS_I2C_EEPROM_NXID
148 #define CONFIG_SYS_EEPROM_BUS_NUM       0
149 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
153
154 /*
155  * DDR Setup
156  */
157 #define CONFIG_VERY_BIG_RAM
158 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
159 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
160
161 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
162 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
163
164 #define CONFIG_DDR_SPD
165 #define CONFIG_FSL_DDR_INTERACTIVE
166
167 #define CONFIG_SYS_SPD_BUS_NUM  0
168 #define SPD_EEPROM_ADDRESS      0x51
169
170 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
171
172 /*
173  * IFC Definitions
174  */
175 #define CONFIG_SYS_FLASH_BASE   0xe0000000
176 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
177
178 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
179 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
180                                 + 0x8000000) | \
181                                 CSPR_PORT_SIZE_16 | \
182                                 CSPR_MSEL_NOR | \
183                                 CSPR_V)
184 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
185 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
186                                 CSPR_PORT_SIZE_16 | \
187                                 CSPR_MSEL_NOR | \
188                                 CSPR_V)
189 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
190
191 /*
192  * TDM Definition
193  */
194 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
195
196 /* NOR Flash Timing Params */
197 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
198 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
199                                 FTIM0_NOR_TEADC(0x5) | \
200                                 FTIM0_NOR_TEAHC(0x5))
201 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
202                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
203                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
204 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
205                                 FTIM2_NOR_TCH(0x4) | \
206                                 FTIM2_NOR_TWPH(0x0E) | \
207                                 FTIM2_NOR_TWP(0x1c))
208 #define CONFIG_SYS_NOR_FTIM3    0x0
209
210 #define CONFIG_SYS_FLASH_QUIET_TEST
211 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
212
213 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
214 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
215 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
217
218 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
220                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
221 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
222 #define QIXIS_BASE              0xffdf0000
223 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
224 #define QIXIS_LBMAP_SWITCH              0x06
225 #define QIXIS_LBMAP_MASK                0x0f
226 #define QIXIS_LBMAP_SHIFT               0
227 #define QIXIS_LBMAP_DFLTBANK            0x00
228 #define QIXIS_LBMAP_ALTBANK             0x04
229 #define QIXIS_RST_CTL_RESET             0x31
230 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
231 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
232 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
233 #define QIXIS_RST_FORCE_MEM             0x01
234
235 #define CONFIG_SYS_CSPR3_EXT    (0xf)
236 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
237                                 | CSPR_PORT_SIZE_8 \
238                                 | CSPR_MSEL_GPCM \
239                                 | CSPR_V)
240 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
241 #define CONFIG_SYS_CSOR3        0x0
242 /* QIXIS Timing parameters for IFC CS3 */
243 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
244                                         FTIM0_GPCM_TEADC(0x0e) | \
245                                         FTIM0_GPCM_TEAHC(0x0e))
246 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
247                                         FTIM1_GPCM_TRAD(0x3f))
248 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
249                                         FTIM2_GPCM_TCH(0x8) | \
250                                         FTIM2_GPCM_TWP(0x1f))
251 #define CONFIG_SYS_CS3_FTIM3            0x0
252
253 #define CONFIG_NAND_FSL_IFC
254 #define CONFIG_SYS_NAND_BASE            0xff800000
255 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
256
257 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
258 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
260                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
261                                 | CSPR_V)
262 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
263
264 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
265                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
266                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
267                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
268                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
269                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
270                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
271
272 #define CONFIG_SYS_NAND_ONFI_DETECTION
273
274 /* ONFI NAND Flash mode0 Timing Params */
275 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
276                                         FTIM0_NAND_TWP(0x18)   | \
277                                         FTIM0_NAND_TWCHT(0x07) | \
278                                         FTIM0_NAND_TWH(0x0a))
279 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
280                                         FTIM1_NAND_TWBE(0x39)  | \
281                                         FTIM1_NAND_TRR(0x0e)   | \
282                                         FTIM1_NAND_TRP(0x18))
283 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
284                                         FTIM2_NAND_TREH(0x0a) | \
285                                         FTIM2_NAND_TWHRE(0x1e))
286 #define CONFIG_SYS_NAND_FTIM3           0x0
287
288 #define CONFIG_SYS_NAND_DDR_LAW         11
289 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
290 #define CONFIG_SYS_MAX_NAND_DEVICE      1
291 #define CONFIG_CMD_NAND
292
293 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
294
295 #if defined(CONFIG_NAND)
296 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
297 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
298 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
299 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
300 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
301 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
302 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
303 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
304 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
305 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
306 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
307 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
308 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
309 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
310 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
311 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
312 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
313 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
314 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
315 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
316 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
317 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
318 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
319 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
320 #else
321 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
322 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
323 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
324 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
325 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
326 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
327 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
328 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
329 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
330 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
331 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
332 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
333 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
334 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
335 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
336 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
337 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
338 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
339 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
340 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
341 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
342 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
343 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
344 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
345 #endif
346
347 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
348
349 #if defined(CONFIG_RAMBOOT_PBL)
350 #define CONFIG_SYS_RAMBOOT
351 #endif
352
353 #define CONFIG_BOARD_EARLY_INIT_R
354 #define CONFIG_MISC_INIT_R
355
356 #define CONFIG_HWCONFIG
357
358 /* define to use L1 as initial stack */
359 #define CONFIG_L1_INIT_RAM
360 #define CONFIG_SYS_INIT_RAM_LOCK
361 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
364 /* The assembler doesn't like typecast */
365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
366         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
367           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
368 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
369
370 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
371                                         GENERATED_GBL_DATA_SIZE)
372 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
373
374 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
375 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
376
377 /* Serial Port - controlled on board with jumper J8
378  * open - index 2
379  * shorted - index 1
380  */
381 #define CONFIG_CONS_INDEX       1
382 #define CONFIG_SYS_NS16550_SERIAL
383 #define CONFIG_SYS_NS16550_REG_SIZE     1
384 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
385
386 #define CONFIG_SYS_BAUDRATE_TABLE       \
387         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
388
389 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
390 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
391 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
392 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
393
394 /* Video */
395 #define CONFIG_FSL_DIU_FB
396 #ifdef CONFIG_FSL_DIU_FB
397 #define CONFIG_FSL_DIU_CH7301
398 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
399 #define CONFIG_VIDEO_LOGO
400 #define CONFIG_VIDEO_BMP_LOGO
401 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
402 /*
403  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
404  * disable empty flash sector detection, which is I/O-intensive.
405  */
406 #undef CONFIG_SYS_FLASH_EMPTY_INFO
407 #endif
408
409 /* I2C */
410 #define CONFIG_SYS_I2C
411 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
412 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
413 #define CONFIG_SYS_FSL_I2C2_SPEED       50000
414 #define CONFIG_SYS_FSL_I2C3_SPEED       50000
415 #define CONFIG_SYS_FSL_I2C4_SPEED       50000
416 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
417 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
418 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
419 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
420 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
421 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
422 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
423 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
424
425 #define I2C_MUX_PCA_ADDR                0x77
426 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
427
428 /* I2C bus multiplexer */
429 #define I2C_MUX_CH_DEFAULT      0x8
430 #define I2C_MUX_CH_DIU          0xC
431
432 /* LDI/DVI Encoder for display */
433 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
434 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
435
436 /*
437  * RTC configuration
438  */
439 #define RTC
440 #define CONFIG_RTC_DS3231               1
441 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
442
443 /*
444  * eSPI - Enhanced SPI
445  */
446 #define CONFIG_SF_DEFAULT_SPEED         10000000
447 #define CONFIG_SF_DEFAULT_MODE          0
448
449 /*
450  * General PCI
451  * Memory space is mapped 1-1, but I/O space must start from 0.
452  */
453
454 #ifdef CONFIG_PCI
455 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
456 #ifdef CONFIG_PCIE1
457 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
458 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
459 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
460 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
461 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
462 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
463 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
464 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
465 #endif
466
467 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
468 #ifdef CONFIG_PCIE2
469 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
470 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
471 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
472 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
473 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
474 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
475 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
476 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
477 #endif
478
479 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
480 #ifdef CONFIG_PCIE3
481 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
482 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
483 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
484 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
485 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
486 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
487 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
488 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
489 #endif
490
491 /* controller 4, Base address 203000 */
492 #ifdef CONFIG_PCIE4
493 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
494 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
495 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
496 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
497 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
498 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
499 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
500 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
501 #endif
502
503 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
504 #endif  /* CONFIG_PCI */
505
506 /* SATA */
507 #define CONFIG_FSL_SATA_V2
508 #ifdef CONFIG_FSL_SATA_V2
509 #define CONFIG_LIBATA
510 #define CONFIG_FSL_SATA
511
512 #define CONFIG_SYS_SATA_MAX_DEVICE      2
513 #define CONFIG_SATA1
514 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
515 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
516 #define CONFIG_SATA2
517 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
518 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
519
520 #define CONFIG_LBA48
521 #define CONFIG_CMD_SATA
522 #endif
523
524 /*
525 * USB
526 */
527 #define CONFIG_HAS_FSL_DR_USB
528
529 #ifdef CONFIG_HAS_FSL_DR_USB
530 #ifdef CONFIG_USB_EHCI_HCD
531 #define CONFIG_USB_EHCI_FSL
532 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
533 #endif
534 #endif
535
536 #ifdef CONFIG_MMC
537 #define CONFIG_FSL_ESDHC
538 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
539 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
540 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
541 #endif
542
543 /* Qman/Bman */
544 #ifndef CONFIG_NOBQFMAN
545 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
546 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
547 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
548 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
549 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
550 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
551 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
552 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
553 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
554 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
555                                         CONFIG_SYS_BMAN_CENA_SIZE)
556 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
557 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
558 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
559 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
560 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
561 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
562 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
563 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
564 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
565 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
566 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
567                                         CONFIG_SYS_QMAN_CENA_SIZE)
568 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
569 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
570
571 #define CONFIG_SYS_DPAA_FMAN
572 #define CONFIG_SYS_DPAA_PME
573
574 #define CONFIG_QE
575 #define CONFIG_U_QE
576 /* Default address of microcode for the Linux Fman driver */
577 #if defined(CONFIG_SPIFLASH)
578 /*
579  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
580  * env, so we got 0x110000.
581  */
582 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
583 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
584 #elif defined(CONFIG_SDCARD)
585 /*
586  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
587  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
588  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
589  */
590 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
591 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
592 #elif defined(CONFIG_NAND)
593 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
594 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
595 #else
596 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
597 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
598 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
599 #endif
600 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
601 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
602 #endif /* CONFIG_NOBQFMAN */
603
604 #ifdef CONFIG_SYS_DPAA_FMAN
605 #define CONFIG_FMAN_ENET
606 #define CONFIG_PHYLIB_10G
607 #define CONFIG_PHY_VITESSE
608 #define CONFIG_PHY_REALTEK
609 #define CONFIG_PHY_TERANETICS
610 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
611 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
612 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
613 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
614 #endif
615
616 #ifdef CONFIG_FMAN_ENET
617 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
618 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
619
620 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
621 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
622 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
623 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
624
625 #define CONFIG_MII              /* MII PHY management */
626 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
627 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
628 #endif
629
630 /* Enable VSC9953 L2 Switch driver */
631 #define CONFIG_VSC9953
632 #define CONFIG_CMD_ETHSW
633 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x14
634 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x18
635
636 /*
637  * Dynamic MTD Partition support with mtdparts
638  */
639 #ifdef CONFIG_MTD_NOR_FLASH
640 #define CONFIG_MTD_DEVICE
641 #define CONFIG_MTD_PARTITIONS
642 #define CONFIG_CMD_MTDPARTS
643 #define CONFIG_FLASH_CFI_MTD
644 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
645                         "spi0=spife110000.0"
646 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
647                                 "128k(dtb),96m(fs),-(user);"\
648                                 "fff800000.flash:2m(uboot),9m(kernel),"\
649                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
650                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
651 #endif
652
653 /*
654  * Environment
655  */
656 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
657 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
658
659 /*
660  * Command line configuration.
661  */
662 #define CONFIG_CMD_ERRATA
663 #define CONFIG_CMD_IRQ
664 #define CONFIG_CMD_REGINFO
665
666 #ifdef CONFIG_PCI
667 #define CONFIG_CMD_PCI
668 #endif
669
670 /* Hash command with SHA acceleration supported in hardware */
671 #ifdef CONFIG_FSL_CAAM
672 #define CONFIG_CMD_HASH
673 #endif
674
675 /*
676  * Miscellaneous configurable options
677  */
678 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
679 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
680 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
681 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
682 #ifdef CONFIG_CMD_KGDB
683 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
684 #else
685 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
686 #endif
687 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
688 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
689 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
690
691 /*
692  * For booting Linux, the board info and command line data
693  * have to be in the first 64 MB of memory, since this is
694  * the maximum mapped by the Linux kernel during initialization.
695  */
696 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
697 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
698
699 #ifdef CONFIG_CMD_KGDB
700 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
701 #endif
702
703 /*
704  * Environment Configuration
705  */
706 #define CONFIG_ROOTPATH         "/opt/nfsroot"
707 #define CONFIG_BOOTFILE         "uImage"
708 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
709
710 /* default location for tftp and bootm */
711 #define CONFIG_LOADADDR         1000000
712
713 #define __USB_PHY_TYPE  utmi
714
715 #define CONFIG_EXTRA_ENV_SETTINGS                               \
716         "hwconfig=fsl_ddr:bank_intlv=auto;"                     \
717         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
718         "netdev=eth0\0"                                         \
719         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
720         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
721         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
722         "tftpflash=tftpboot $loadaddr $uboot && "               \
723         "protect off $ubootaddr +$filesize && "                 \
724         "erase $ubootaddr +$filesize && "                       \
725         "cp.b $loadaddr $ubootaddr $filesize && "               \
726         "protect on $ubootaddr +$filesize && "                  \
727         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
728         "consoledev=ttyS0\0"                                    \
729         "ramdiskaddr=2000000\0"                                 \
730         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
731         "fdtaddr=1e00000\0"                                     \
732         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
733         "bdev=sda3\0"
734
735 #define CONFIG_LINUX                       \
736         "setenv bootargs root=/dev/ram rw "            \
737         "console=$consoledev,$baudrate $othbootargs;"  \
738         "setenv ramdiskaddr 0x02000000;"               \
739         "setenv fdtaddr 0x00c00000;"                   \
740         "setenv loadaddr 0x1000000;"                   \
741         "bootm $loadaddr $ramdiskaddr $fdtaddr"
742
743 #define CONFIG_HDBOOT                                   \
744         "setenv bootargs root=/dev/$bdev rw "           \
745         "console=$consoledev,$baudrate $othbootargs;"   \
746         "tftp $loadaddr $bootfile;"                     \
747         "tftp $fdtaddr $fdtfile;"                       \
748         "bootm $loadaddr - $fdtaddr"
749
750 #define CONFIG_NFSBOOTCOMMAND                   \
751         "setenv bootargs root=/dev/nfs rw "     \
752         "nfsroot=$serverip:$rootpath "          \
753         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
754         "console=$consoledev,$baudrate $othbootargs;"   \
755         "tftp $loadaddr $bootfile;"             \
756         "tftp $fdtaddr $fdtfile;"               \
757         "bootm $loadaddr - $fdtaddr"
758
759 #define CONFIG_RAMBOOTCOMMAND                           \
760         "setenv bootargs root=/dev/ram rw "             \
761         "console=$consoledev,$baudrate $othbootargs;"   \
762         "tftp $ramdiskaddr $ramdiskfile;"               \
763         "tftp $loadaddr $bootfile;"                     \
764         "tftp $fdtaddr $fdtfile;"                       \
765         "bootm $loadaddr $ramdiskaddr $fdtaddr"
766
767 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
768
769 #include <asm/fsl_secure_boot.h>
770
771 #endif  /* __CONFIG_H */