1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T1024/T1023 RDB board configuration file
14 #include <linux/stringify.h>
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
20 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
21 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
23 #ifdef CONFIG_RAMBOOT_PBL
24 #define RESET_VECTOR_OFFSET 0x27FFC
25 #define BOOT_PAGE_OFFSET 0x27000
27 #ifdef CONFIG_MTD_RAW_NAND
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
31 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
32 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
36 #ifdef CONFIG_SPIFLASH
37 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
43 #ifndef CONFIG_SPL_BUILD
44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
51 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
52 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
54 #ifndef CONFIG_SPL_BUILD
55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
59 #endif /* CONFIG_RAMBOOT_PBL */
61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
65 /* PCIe Boot - Master */
66 #define CONFIG_SRIO_PCIE_BOOT_MASTER
68 * for slave u-boot IMAGE instored in master memory space,
69 * PHYS must be aligned based on the SIZE
71 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
72 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
73 #ifdef CONFIG_PHYS_64BIT
74 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
75 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
77 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
78 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
81 * for slave UCODE and ENV instored in master memory space,
82 * PHYS must be aligned based on the SIZE
84 #ifdef CONFIG_PHYS_64BIT
85 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
86 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
88 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
89 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
91 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
92 /* slave core release by master*/
93 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
94 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
96 /* PCIe Boot - Slave */
97 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
98 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
99 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
100 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
101 /* Set 1M boot space for PCIe boot */
102 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
103 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
104 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
105 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
109 * These can be toggled for performance analysis, otherwise use default.
111 #define CONFIG_SYS_CACHE_STASHING
112 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
113 #ifdef CONFIG_DDR_ECC
114 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
118 * Config the L3 Cache as L3 SRAM
120 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
121 #define CONFIG_SYS_L3_SIZE (256 << 10)
122 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
123 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
124 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
125 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
126 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_SYS_DCSRBAR 0xf0000000
130 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
134 #define CONFIG_SYS_I2C_EEPROM_NXID
135 #define CONFIG_SYS_EEPROM_BUS_NUM 0
140 #define CONFIG_VERY_BIG_RAM
141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143 #if defined(CONFIG_TARGET_T1024RDB)
144 #define CONFIG_SYS_SPD_BUS_NUM 0
145 #define SPD_EEPROM_ADDRESS 0x51
146 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
147 #elif defined(CONFIG_TARGET_T1023RDB)
148 #define CONFIG_SYS_DDR_RAW_TIMING
149 #define CONFIG_SYS_SDRAM_SIZE 2048
155 #define CONFIG_SYS_FLASH_BASE 0xe8000000
156 #ifdef CONFIG_PHYS_64BIT
157 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
159 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
162 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
163 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
164 CSPR_PORT_SIZE_16 | \
167 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
169 /* NOR Flash Timing Params */
170 #if defined(CONFIG_TARGET_T1024RDB)
171 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
172 #elif defined(CONFIG_TARGET_T1023RDB)
173 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
174 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
176 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
177 FTIM0_NOR_TEADC(0x5) | \
178 FTIM0_NOR_TEAHC(0x5))
179 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
180 FTIM1_NOR_TRAD_NOR(0x1A) |\
181 FTIM1_NOR_TSEQRAD_NOR(0x13))
182 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
183 FTIM2_NOR_TCH(0x4) | \
184 FTIM2_NOR_TWPH(0x0E) | \
186 #define CONFIG_SYS_NOR_FTIM3 0x0
188 #define CONFIG_SYS_FLASH_QUIET_TEST
189 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
195 #define CONFIG_SYS_FLASH_EMPTY_INFO
196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
198 #ifdef CONFIG_TARGET_T1024RDB
200 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
201 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
202 #define CONFIG_SYS_CSPR2_EXT (0xf)
203 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
207 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
208 #define CONFIG_SYS_CSOR2 0x0
210 /* CPLD Timing parameters for IFC CS2 */
211 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
212 FTIM0_GPCM_TEADC(0x0e) | \
213 FTIM0_GPCM_TEAHC(0x0e))
214 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
215 FTIM1_GPCM_TRAD(0x1f))
216 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
217 FTIM2_GPCM_TCH(0x8) | \
218 FTIM2_GPCM_TWP(0x1f))
219 #define CONFIG_SYS_CS2_FTIM3 0x0
222 /* NAND Flash on IFC */
223 #define CONFIG_SYS_NAND_BASE 0xff800000
224 #ifdef CONFIG_PHYS_64BIT
225 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
227 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
229 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
230 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
231 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
232 | CSPR_MSEL_NAND /* MSEL = NAND */ \
234 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
236 #if defined(CONFIG_TARGET_T1024RDB)
237 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
238 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
239 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
240 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
241 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
242 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
243 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
244 #elif defined(CONFIG_TARGET_T1023RDB)
245 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
246 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
247 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
248 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
249 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
250 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
251 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
254 /* ONFI NAND Flash mode0 Timing Params */
255 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
256 FTIM0_NAND_TWP(0x18) | \
257 FTIM0_NAND_TWCHT(0x07) | \
258 FTIM0_NAND_TWH(0x0a))
259 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
260 FTIM1_NAND_TWBE(0x39) | \
261 FTIM1_NAND_TRR(0x0e) | \
262 FTIM1_NAND_TRP(0x18))
263 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
264 FTIM2_NAND_TREH(0x0a) | \
265 FTIM2_NAND_TWHRE(0x1e))
266 #define CONFIG_SYS_NAND_FTIM3 0x0
268 #define CONFIG_SYS_NAND_DDR_LAW 11
269 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
270 #define CONFIG_SYS_MAX_NAND_DEVICE 1
272 #if defined(CONFIG_MTD_RAW_NAND)
273 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
274 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
275 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
276 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
277 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
278 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
279 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
280 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
281 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
282 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
283 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
284 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
285 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
286 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
287 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
288 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
291 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
292 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
293 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
294 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
295 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
296 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
297 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
298 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
299 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
300 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
301 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
302 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
303 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
304 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
305 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
308 #if defined(CONFIG_RAMBOOT_PBL)
309 #define CONFIG_SYS_RAMBOOT
312 #define CONFIG_HWCONFIG
314 /* define to use L1 as initial stack */
315 #define CONFIG_L1_INIT_RAM
316 #define CONFIG_SYS_INIT_RAM_LOCK
317 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
318 #ifdef CONFIG_PHYS_64BIT
319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
320 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
321 /* The assembler doesn't like typecast */
322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
323 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
324 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
328 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
330 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
332 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
334 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
337 #define CONFIG_SYS_NS16550_SERIAL
338 #define CONFIG_SYS_NS16550_REG_SIZE 1
339 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
341 #define CONFIG_SYS_BAUDRATE_TABLE \
342 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
344 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
345 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
346 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
347 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
351 #define I2C_PCA6408_BUS_NUM 1
352 #define I2C_PCA6408_ADDR 0x20
354 /* I2C bus multiplexer */
355 #define I2C_MUX_CH_DEFAULT 0x8
361 #define CONFIG_RTC_DS1337 1
362 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
365 * eSPI - Enhanced SPI
370 * Memory space is mapped 1-1, but I/O space must start from 0.
372 #define CONFIG_PCIE1 /* PCIE controller 1 */
373 #define CONFIG_PCIE2 /* PCIE controller 2 */
374 #define CONFIG_PCIE3 /* PCIE controller 3 */
377 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
379 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
380 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
381 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
385 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
387 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
388 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
389 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
390 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
393 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
395 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
396 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
397 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
398 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
401 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
402 #endif /* CONFIG_PCI */
407 #define CONFIG_HAS_FSL_DR_USB
409 #ifdef CONFIG_HAS_FSL_DR_USB
410 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
417 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
421 #ifndef CONFIG_NOBQFMAN
422 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
423 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
424 #ifdef CONFIG_PHYS_64BIT
425 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
427 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
429 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
430 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
431 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
432 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
433 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
434 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
435 CONFIG_SYS_BMAN_CENA_SIZE)
436 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
437 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
438 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
439 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
443 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
445 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
446 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
447 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
448 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
449 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
450 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
451 CONFIG_SYS_QMAN_CENA_SIZE)
452 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
453 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
455 #define CONFIG_SYS_DPAA_FMAN
457 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
458 #endif /* CONFIG_NOBQFMAN */
460 #ifdef CONFIG_SYS_DPAA_FMAN
461 #if defined(CONFIG_TARGET_T1024RDB)
462 #define RGMII_PHY1_ADDR 0x2
463 #define RGMII_PHY2_ADDR 0x6
464 #define SGMII_AQR_PHY_ADDR 0x2
465 #define FM1_10GEC1_PHY_ADDR 0x1
466 #elif defined(CONFIG_TARGET_T1023RDB)
467 #define RGMII_PHY1_ADDR 0x1
468 #define SGMII_RTK_PHY_ADDR 0x3
469 #define SGMII_AQR_PHY_ADDR 0x2
474 * Dynamic MTD Partition support with mtdparts
480 #define CONFIG_LOADS_ECHO /* echo on for serial download */
481 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
484 * Miscellaneous configurable options
488 * For booting Linux, the board info and command line data
489 * have to be in the first 64 MB of memory, since this is
490 * the maximum mapped by the Linux kernel during initialization.
492 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
493 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
496 * Environment Configuration
498 #define CONFIG_ROOTPATH "/opt/nfsroot"
499 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
500 #define __USB_PHY_TYPE utmi
502 #ifdef CONFIG_ARCH_T1024
503 #define ARCH_EXTRA_ENV_SETTINGS \
504 "bank_intlv=cs0_cs1\0" \
505 "ramdiskfile=t1024rdb/ramdisk.uboot\0" \
506 "fdtfile=t1024rdb/t1024rdb.dtb\0"
508 #define ARCH_EXTRA_ENV_SETTINGS \
509 "bank_intlv=null\0" \
510 "ramdiskfile=t1023rdb/ramdisk.uboot\0" \
511 "fdtfile=t1023rdb/t1023rdb.dtb\0"
514 #define CONFIG_EXTRA_ENV_SETTINGS \
515 ARCH_EXTRA_ENV_SETTINGS \
516 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
517 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
518 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
519 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
520 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
522 "tftpflash=tftpboot $loadaddr $uboot && " \
523 "protect off $ubootaddr +$filesize && " \
524 "erase $ubootaddr +$filesize && " \
525 "cp.b $loadaddr $ubootaddr $filesize && " \
526 "protect on $ubootaddr +$filesize && " \
527 "cmp.b $loadaddr $ubootaddr $filesize\0" \
528 "consoledev=ttyS0\0" \
529 "ramdiskaddr=2000000\0" \
530 "fdtaddr=1e00000\0" \
533 #include <asm/fsl_secure_boot.h>
535 #endif /* __T1024RDB_H */