1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T1024/T1023 RDB board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
16 #define CONFIG_ENABLE_36BIT_PHYS
18 #ifdef CONFIG_PHYS_64BIT
19 #define CONFIG_ADDR_MAP 1
20 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #define CONFIG_ENV_OVERWRITE
28 /* support deep sleep */
29 #ifdef CONFIG_ARCH_T1024
30 #define CONFIG_DEEP_SLEEP
33 #ifdef CONFIG_RAMBOOT_PBL
34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
35 #define CONFIG_SPL_FLUSH_IMAGE
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
40 #ifdef CONFIG_SPL_BUILD
41 #define CONFIG_SPL_SKIP_RELOCATE
42 #define CONFIG_SPL_COMMON_INIT_DDR
43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #ifdef CONFIG_MTD_RAW_NAND
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51 #if defined(CONFIG_TARGET_T1024RDB)
52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
53 #elif defined(CONFIG_TARGET_T1023RDB)
54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
58 #ifdef CONFIG_SPIFLASH
59 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
65 #ifndef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
68 #if defined(CONFIG_TARGET_T1024RDB)
69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
70 #elif defined(CONFIG_TARGET_T1023RDB)
71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
79 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
81 #ifndef CONFIG_SPL_BUILD
82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
84 #if defined(CONFIG_TARGET_T1024RDB)
85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
86 #elif defined(CONFIG_TARGET_T1023RDB)
87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
91 #endif /* CONFIG_RAMBOOT_PBL */
93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
97 /* PCIe Boot - Master */
98 #define CONFIG_SRIO_PCIE_BOOT_MASTER
100 * for slave u-boot IMAGE instored in master memory space,
101 * PHYS must be aligned based on the SIZE
103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
113 * for slave UCODE and ENV instored in master memory space,
114 * PHYS must be aligned based on the SIZE
116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
124 /* slave core release by master*/
125 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
126 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
128 /* PCIe Boot - Slave */
129 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
131 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
132 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
133 /* Set 1M boot space for PCIe boot */
134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
135 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
136 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
137 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
140 #if defined(CONFIG_SPIFLASH)
141 #elif defined(CONFIG_SDCARD)
142 #define CONFIG_SYS_MMC_ENV_DEV 0
146 unsigned long get_board_sys_clk(void);
147 unsigned long get_board_ddr_clk(void);
150 #define CONFIG_SYS_CLK_FREQ 100000000
151 #define CONFIG_DDR_CLK_FREQ 100000000
154 * These can be toggled for performance analysis, otherwise use default.
156 #define CONFIG_SYS_CACHE_STASHING
157 #define CONFIG_BACKSIDE_L2_CACHE
158 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
159 #define CONFIG_BTB /* toggle branch predition */
160 #define CONFIG_DDR_ECC
161 #ifdef CONFIG_DDR_ECC
162 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
163 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
167 * Config the L3 Cache as L3 SRAM
169 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
170 #define CONFIG_SYS_L3_SIZE (256 << 10)
171 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
172 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
173 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
174 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
175 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
177 #ifdef CONFIG_PHYS_64BIT
178 #define CONFIG_SYS_DCSRBAR 0xf0000000
179 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
183 #define CONFIG_ID_EEPROM
184 #define CONFIG_SYS_I2C_EEPROM_NXID
185 #define CONFIG_SYS_EEPROM_BUS_NUM 0
186 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
187 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
194 #define CONFIG_VERY_BIG_RAM
195 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
196 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
197 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
198 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
199 #if defined(CONFIG_TARGET_T1024RDB)
200 #define CONFIG_DDR_SPD
201 #define CONFIG_SYS_SPD_BUS_NUM 0
202 #define SPD_EEPROM_ADDRESS 0x51
203 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
204 #elif defined(CONFIG_TARGET_T1023RDB)
205 #define CONFIG_SYS_DDR_RAW_TIMING
206 #define CONFIG_SYS_SDRAM_SIZE 2048
212 #define CONFIG_SYS_FLASH_BASE 0xe8000000
213 #ifdef CONFIG_PHYS_64BIT
214 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
216 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
219 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
220 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
221 CSPR_PORT_SIZE_16 | \
224 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
226 /* NOR Flash Timing Params */
227 #if defined(CONFIG_TARGET_T1024RDB)
228 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
229 #elif defined(CONFIG_TARGET_T1023RDB)
230 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
231 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
233 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
234 FTIM0_NOR_TEADC(0x5) | \
235 FTIM0_NOR_TEAHC(0x5))
236 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
237 FTIM1_NOR_TRAD_NOR(0x1A) |\
238 FTIM1_NOR_TSEQRAD_NOR(0x13))
239 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
240 FTIM2_NOR_TCH(0x4) | \
241 FTIM2_NOR_TWPH(0x0E) | \
243 #define CONFIG_SYS_NOR_FTIM3 0x0
245 #define CONFIG_SYS_FLASH_QUIET_TEST
246 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
248 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
249 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
250 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
251 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
253 #define CONFIG_SYS_FLASH_EMPTY_INFO
254 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
256 #ifdef CONFIG_TARGET_T1024RDB
258 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
259 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
260 #define CONFIG_SYS_CSPR2_EXT (0xf)
261 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
265 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
266 #define CONFIG_SYS_CSOR2 0x0
268 /* CPLD Timing parameters for IFC CS2 */
269 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
270 FTIM0_GPCM_TEADC(0x0e) | \
271 FTIM0_GPCM_TEAHC(0x0e))
272 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
273 FTIM1_GPCM_TRAD(0x1f))
274 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
275 FTIM2_GPCM_TCH(0x8) | \
276 FTIM2_GPCM_TWP(0x1f))
277 #define CONFIG_SYS_CS2_FTIM3 0x0
280 /* NAND Flash on IFC */
281 #define CONFIG_NAND_FSL_IFC
282 #define CONFIG_SYS_NAND_BASE 0xff800000
283 #ifdef CONFIG_PHYS_64BIT
284 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
286 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
288 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
289 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
290 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
291 | CSPR_MSEL_NAND /* MSEL = NAND */ \
293 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
295 #if defined(CONFIG_TARGET_T1024RDB)
296 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
297 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
298 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
299 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
300 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
301 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
302 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
303 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
304 #elif defined(CONFIG_TARGET_T1023RDB)
305 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
306 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
307 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
308 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
309 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
310 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
311 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
312 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
315 #define CONFIG_SYS_NAND_ONFI_DETECTION
316 /* ONFI NAND Flash mode0 Timing Params */
317 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
318 FTIM0_NAND_TWP(0x18) | \
319 FTIM0_NAND_TWCHT(0x07) | \
320 FTIM0_NAND_TWH(0x0a))
321 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
322 FTIM1_NAND_TWBE(0x39) | \
323 FTIM1_NAND_TRR(0x0e) | \
324 FTIM1_NAND_TRP(0x18))
325 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
326 FTIM2_NAND_TREH(0x0a) | \
327 FTIM2_NAND_TWHRE(0x1e))
328 #define CONFIG_SYS_NAND_FTIM3 0x0
330 #define CONFIG_SYS_NAND_DDR_LAW 11
331 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
332 #define CONFIG_SYS_MAX_NAND_DEVICE 1
334 #if defined(CONFIG_MTD_RAW_NAND)
335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
352 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
353 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
354 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
355 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
356 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
357 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
358 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
359 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
360 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
370 #ifdef CONFIG_SPL_BUILD
371 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
376 #if defined(CONFIG_RAMBOOT_PBL)
377 #define CONFIG_SYS_RAMBOOT
380 #define CONFIG_HWCONFIG
382 /* define to use L1 as initial stack */
383 #define CONFIG_L1_INIT_RAM
384 #define CONFIG_SYS_INIT_RAM_LOCK
385 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
386 #ifdef CONFIG_PHYS_64BIT
387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
389 /* The assembler doesn't like typecast */
390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
391 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
392 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
398 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
400 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
401 GENERATED_GBL_DATA_SIZE)
402 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
404 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
405 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
408 #define CONFIG_SYS_NS16550_SERIAL
409 #define CONFIG_SYS_NS16550_REG_SIZE 1
410 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
412 #define CONFIG_SYS_BAUDRATE_TABLE \
413 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
415 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
416 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
417 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
418 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
421 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
422 #ifdef CONFIG_FSL_DIU_FB
423 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
424 #define CONFIG_VIDEO_LOGO
425 #define CONFIG_VIDEO_BMP_LOGO
426 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
428 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
429 * disable empty flash sector detection, which is I/O-intensive.
431 #undef CONFIG_SYS_FLASH_EMPTY_INFO
435 #ifndef CONFIG_DM_I2C
436 #define CONFIG_SYS_I2C
437 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
438 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
439 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
440 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
441 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
442 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
444 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
445 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
448 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
449 #define I2C_PCA6408_BUS_NUM 1
450 #define I2C_PCA6408_ADDR 0x20
452 /* I2C bus multiplexer */
453 #define I2C_MUX_CH_DEFAULT 0x8
459 #define CONFIG_RTC_DS1337 1
460 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
463 * eSPI - Enhanced SPI
468 * Memory space is mapped 1-1, but I/O space must start from 0.
470 #define CONFIG_PCIE1 /* PCIE controller 1 */
471 #define CONFIG_PCIE2 /* PCIE controller 2 */
472 #define CONFIG_PCIE3 /* PCIE controller 3 */
473 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
476 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
478 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
479 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
480 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
481 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
484 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
486 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
487 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
488 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
489 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
492 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
494 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
495 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
496 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
497 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
500 #if !defined(CONFIG_DM_PCI)
501 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
502 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
503 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
504 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
506 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
507 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
508 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
509 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
510 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
511 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
512 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
513 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
514 #define CONFIG_PCI_INDIRECT_BRIDGE
517 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
518 #endif /* CONFIG_PCI */
523 #define CONFIG_HAS_FSL_DR_USB
525 #ifdef CONFIG_HAS_FSL_DR_USB
526 #define CONFIG_USB_EHCI_FSL
527 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
534 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
538 #ifndef CONFIG_NOBQFMAN
539 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
540 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
541 #ifdef CONFIG_PHYS_64BIT
542 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
544 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
546 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
547 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
548 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
549 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
550 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
551 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
552 CONFIG_SYS_BMAN_CENA_SIZE)
553 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
554 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
555 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
556 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
557 #ifdef CONFIG_PHYS_64BIT
558 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
560 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
562 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
563 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
564 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
565 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
566 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
567 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
568 CONFIG_SYS_QMAN_CENA_SIZE)
569 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
570 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
572 #define CONFIG_SYS_DPAA_FMAN
574 /* Default address of microcode for the Linux FMan driver */
575 #if defined(CONFIG_SPIFLASH)
577 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
578 * env, so we got 0x110000.
580 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
581 #define CONFIG_SYS_QE_FW_ADDR 0x130000
582 #elif defined(CONFIG_SDCARD)
584 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
585 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
586 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
588 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
589 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
590 #elif defined(CONFIG_MTD_RAW_NAND)
591 #if defined(CONFIG_TARGET_T1024RDB)
592 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
593 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
594 #elif defined(CONFIG_TARGET_T1023RDB)
595 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
596 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
598 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
600 * Slave has no ucode locally, it can fetch this from remote. When implementing
601 * in two corenet boards, slave's ucode could be stored in master's memory
602 * space, the address can be mapped from slave TLB->slave LAW->
603 * slave SRIO or PCIE outbound window->master inbound window->
604 * master LAW->the ucode address in master's memory space.
606 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
608 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
609 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
611 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
612 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
613 #endif /* CONFIG_NOBQFMAN */
615 #ifdef CONFIG_SYS_DPAA_FMAN
616 #if defined(CONFIG_TARGET_T1024RDB)
617 #define RGMII_PHY1_ADDR 0x2
618 #define RGMII_PHY2_ADDR 0x6
619 #define SGMII_AQR_PHY_ADDR 0x2
620 #define FM1_10GEC1_PHY_ADDR 0x1
621 #elif defined(CONFIG_TARGET_T1023RDB)
622 #define RGMII_PHY1_ADDR 0x1
623 #define SGMII_RTK_PHY_ADDR 0x3
624 #define SGMII_AQR_PHY_ADDR 0x2
628 #ifdef CONFIG_FMAN_ENET
629 #define CONFIG_ETHPRIME "FM1@DTSEC4"
633 * Dynamic MTD Partition support with mtdparts
639 #define CONFIG_LOADS_ECHO /* echo on for serial download */
640 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
643 * Miscellaneous configurable options
645 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
648 * For booting Linux, the board info and command line data
649 * have to be in the first 64 MB of memory, since this is
650 * the maximum mapped by the Linux kernel during initialization.
652 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
653 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
655 #ifdef CONFIG_CMD_KGDB
656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
660 * Environment Configuration
662 #define CONFIG_ROOTPATH "/opt/nfsroot"
663 #define CONFIG_BOOTFILE "uImage"
664 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
665 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
666 #define __USB_PHY_TYPE utmi
668 #ifdef CONFIG_ARCH_T1024
669 #define CONFIG_BOARDNAME t1024rdb
670 #define BANK_INTLV cs0_cs1
672 #define CONFIG_BOARDNAME t1023rdb
673 #define BANK_INTLV null
676 #define CONFIG_EXTRA_ENV_SETTINGS \
677 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
678 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
679 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
680 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
681 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
682 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
684 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
685 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
687 "tftpflash=tftpboot $loadaddr $uboot && " \
688 "protect off $ubootaddr +$filesize && " \
689 "erase $ubootaddr +$filesize && " \
690 "cp.b $loadaddr $ubootaddr $filesize && " \
691 "protect on $ubootaddr +$filesize && " \
692 "cmp.b $loadaddr $ubootaddr $filesize\0" \
693 "consoledev=ttyS0\0" \
694 "ramdiskaddr=2000000\0" \
695 "fdtaddr=1e00000\0" \
698 #define CONFIG_LINUX \
699 "setenv bootargs root=/dev/ram rw " \
700 "console=$consoledev,$baudrate $othbootargs;" \
701 "setenv ramdiskaddr 0x02000000;" \
702 "setenv fdtaddr 0x00c00000;" \
703 "setenv loadaddr 0x1000000;" \
704 "bootm $loadaddr $ramdiskaddr $fdtaddr"
706 #define CONFIG_NFSBOOTCOMMAND \
707 "setenv bootargs root=/dev/nfs rw " \
708 "nfsroot=$serverip:$rootpath " \
709 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
710 "console=$consoledev,$baudrate $othbootargs;" \
711 "tftp $loadaddr $bootfile;" \
712 "tftp $fdtaddr $fdtfile;" \
713 "bootm $loadaddr - $fdtaddr"
715 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
717 #include <asm/fsl_secure_boot.h>
719 #endif /* __T1024RDB_H */