include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 RDB board configuration file
   8  */
   9
  10 #ifndef __T1024RDB_H
  11 #define __T1024RDB_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 /* support deep sleep */
  28 #ifdef CONFIG_ARCH_T1024
  29 #define CONFIG_DEEP_SLEEP
  30 #endif
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_SKIP_RELOCATE
  41 #define CONFIG_SPL_COMMON_INIT_DDR
  42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 #endif
  44
  45 #ifdef CONFIG_NAND
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  50 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  51 #if defined(CONFIG_TARGET_T1024RDB)
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  53 #elif defined(CONFIG_TARGET_T1023RDB)
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_SPIFLASH
  59 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  65 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  66 #ifndef CONFIG_SPL_BUILD
  67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  68 #endif
  69 #if defined(CONFIG_TARGET_T1024RDB)
  70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  71 #elif defined(CONFIG_TARGET_T1023RDB)
  72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  73 #endif
  74 #endif
  75
  76 #ifdef CONFIG_SDCARD
  77 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  78 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  79 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  80 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  81 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  82 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  83 #ifndef CONFIG_SPL_BUILD
  84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  85 #endif
  86 #if defined(CONFIG_TARGET_T1024RDB)
  87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  88 #elif defined(CONFIG_TARGET_T1023RDB)
  89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  90 #endif
  91 #endif
  92
  93 #endif /* CONFIG_RAMBOOT_PBL */
  94
  95 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  96 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  97 #endif
  98
  99 /* PCIe Boot - Master */
 100 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 101 /*
 102  * for slave u-boot IMAGE instored in master memory space,
 103  * PHYS must be aligned based on the SIZE
 104  */
 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 107 #ifdef CONFIG_PHYS_64BIT
 108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 110 #else
 111 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 113 #endif
 114 /*
 115  * for slave UCODE and ENV instored in master memory space,
 116  * PHYS must be aligned based on the SIZE
 117  */
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 121 #else
 122 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 124 #endif
 125 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 126 /* slave core release by master*/
 127 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 128 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 129
 130 /* PCIe Boot - Slave */
 131 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 132 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 133 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 134                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 135 /* Set 1M boot space for PCIe boot */
 136 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 137 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 138                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 139 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 140 #endif
 141
 142 #if defined(CONFIG_SPIFLASH)
 143 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 144 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 145 #if defined(CONFIG_TARGET_T1024RDB)
 146 #define CONFIG_ENV_SECT_SIZE            0x10000
 147 #elif defined(CONFIG_TARGET_T1023RDB)
 148 #define CONFIG_ENV_SECT_SIZE            0x40000
 149 #endif
 150 #elif defined(CONFIG_SDCARD)
 151 #define CONFIG_SYS_MMC_ENV_DEV          0
 152 #define CONFIG_ENV_SIZE                 0x2000
 153 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 154 #elif defined(CONFIG_NAND)
 155 #define CONFIG_ENV_SIZE                 0x2000
 156 #if defined(CONFIG_TARGET_T1024RDB)
 157 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 158 #elif defined(CONFIG_TARGET_T1023RDB)
 159 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 160 #endif
 161 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 162 #define CONFIG_ENV_ADDR         0xffe20000
 163 #define CONFIG_ENV_SIZE         0x2000
 164 #elif defined(CONFIG_ENV_IS_NOWHERE)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #else
 167 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 168 #define CONFIG_ENV_SIZE         0x2000
 169 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 170 #endif
 171
 172 #ifndef __ASSEMBLY__
 173 unsigned long get_board_sys_clk(void);
 174 unsigned long get_board_ddr_clk(void);
 175 #endif
 176
 177 #define CONFIG_SYS_CLK_FREQ     100000000
 178 #define CONFIG_DDR_CLK_FREQ     100000000
 179
 180 /*
 181  * These can be toggled for performance analysis, otherwise use default.
 182  */
 183 #define CONFIG_SYS_CACHE_STASHING
 184 #define CONFIG_BACKSIDE_L2_CACHE
 185 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 186 #define CONFIG_BTB                      /* toggle branch predition */
 187 #define CONFIG_DDR_ECC
 188 #ifdef CONFIG_DDR_ECC
 189 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 190 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 191 #endif
 192
 193 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 194 #define CONFIG_SYS_MEMTEST_END          0x00400000
 195
 196 /*
 197  *  Config the L3 Cache as L3 SRAM
 198  */
 199 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 200 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 201 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 202 #ifdef CONFIG_RAMBOOT_PBL
 203 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 204 #endif
 205 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 206 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 207 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 208
 209 #ifdef CONFIG_PHYS_64BIT
 210 #define CONFIG_SYS_DCSRBAR              0xf0000000
 211 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 212 #endif
 213
 214 /* EEPROM */
 215 #define CONFIG_ID_EEPROM
 216 #define CONFIG_SYS_I2C_EEPROM_NXID
 217 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 218 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 222
 223 /*
 224  * DDR Setup
 225  */
 226 #define CONFIG_VERY_BIG_RAM
 227 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 228 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 229 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 230 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 231 #if defined(CONFIG_TARGET_T1024RDB)
 232 #define CONFIG_DDR_SPD
 233 #define CONFIG_SYS_SPD_BUS_NUM  0
 234 #define SPD_EEPROM_ADDRESS      0x51
 235 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 236 #elif defined(CONFIG_TARGET_T1023RDB)
 237 #define CONFIG_SYS_DDR_RAW_TIMING
 238 #define CONFIG_SYS_SDRAM_SIZE   2048
 239 #endif
 240
 241 /*
 242  * IFC Definitions
 243  */
 244 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 245 #ifdef CONFIG_PHYS_64BIT
 246 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 247 #else
 248 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 249 #endif
 250
 251 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 252 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 253                                 CSPR_PORT_SIZE_16 | \
 254                                 CSPR_MSEL_NOR | \
 255                                 CSPR_V)
 256 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 257
 258 /* NOR Flash Timing Params */
 259 #if defined(CONFIG_TARGET_T1024RDB)
 260 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 261 #elif defined(CONFIG_TARGET_T1023RDB)
 262 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 263                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 264 #endif
 265 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 266                                 FTIM0_NOR_TEADC(0x5) | \
 267                                 FTIM0_NOR_TEAHC(0x5))
 268 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 269                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 270                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 271 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 272                                 FTIM2_NOR_TCH(0x4) | \
 273                                 FTIM2_NOR_TWPH(0x0E) | \
 274                                 FTIM2_NOR_TWP(0x1c))
 275 #define CONFIG_SYS_NOR_FTIM3    0x0
 276
 277 #define CONFIG_SYS_FLASH_QUIET_TEST
 278 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 279
 280 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 281 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 282 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 283 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 284
 285 #define CONFIG_SYS_FLASH_EMPTY_INFO
 286 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 287
 288 #ifdef CONFIG_TARGET_T1024RDB
 289 /* CPLD on IFC */
 290 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 291 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 292 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 293 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 294                                                 | CSPR_PORT_SIZE_8 \
 295                                                 | CSPR_MSEL_GPCM \
 296                                                 | CSPR_V)
 297 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 298 #define CONFIG_SYS_CSOR2                0x0
 299
 300 /* CPLD Timing parameters for IFC CS2 */
 301 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 302                                                 FTIM0_GPCM_TEADC(0x0e) | \
 303                                                 FTIM0_GPCM_TEAHC(0x0e))
 304 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 305                                                 FTIM1_GPCM_TRAD(0x1f))
 306 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 307                                                 FTIM2_GPCM_TCH(0x8) | \
 308                                                 FTIM2_GPCM_TWP(0x1f))
 309 #define CONFIG_SYS_CS2_FTIM3            0x0
 310 #endif
 311
 312 /* NAND Flash on IFC */
 313 #define CONFIG_NAND_FSL_IFC
 314 #define CONFIG_SYS_NAND_BASE            0xff800000
 315 #ifdef CONFIG_PHYS_64BIT
 316 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 317 #else
 318 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 319 #endif
 320 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 321 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 322                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 323                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 324                                 | CSPR_V)
 325 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 326
 327 #if defined(CONFIG_TARGET_T1024RDB)
 328 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 329                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 330                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 331                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 332                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 333                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 334                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 335 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 336 #elif defined(CONFIG_TARGET_T1023RDB)
 337 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 338                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 339                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 340                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 341                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 342                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 343                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 344 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 345 #endif
 346
 347 #define CONFIG_SYS_NAND_ONFI_DETECTION
 348 /* ONFI NAND Flash mode0 Timing Params */
 349 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 350                                         FTIM0_NAND_TWP(0x18)   | \
 351                                         FTIM0_NAND_TWCHT(0x07) | \
 352                                         FTIM0_NAND_TWH(0x0a))
 353 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 354                                         FTIM1_NAND_TWBE(0x39)  | \
 355                                         FTIM1_NAND_TRR(0x0e)   | \
 356                                         FTIM1_NAND_TRP(0x18))
 357 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 358                                         FTIM2_NAND_TREH(0x0a) | \
 359                                         FTIM2_NAND_TWHRE(0x1e))
 360 #define CONFIG_SYS_NAND_FTIM3           0x0
 361
 362 #define CONFIG_SYS_NAND_DDR_LAW         11
 363 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 364 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 365
 366 #if defined(CONFIG_NAND)
 367 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 368 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 369 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 370 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 371 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 372 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 373 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 374 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 375 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 376 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 377 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 378 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 379 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 380 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 381 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 382 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 383 #else
 384 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 385 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 386 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 387 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 388 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 389 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 390 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 391 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 392 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 393 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 394 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 395 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 396 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 397 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 398 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 399 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 400 #endif
 401
 402 #ifdef CONFIG_SPL_BUILD
 403 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 404 #else
 405 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 406 #endif
 407
 408 #if defined(CONFIG_RAMBOOT_PBL)
 409 #define CONFIG_SYS_RAMBOOT
 410 #endif
 411
 412 #define CONFIG_HWCONFIG
 413
 414 /* define to use L1 as initial stack */
 415 #define CONFIG_L1_INIT_RAM
 416 #define CONFIG_SYS_INIT_RAM_LOCK
 417 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 418 #ifdef CONFIG_PHYS_64BIT
 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 421 /* The assembler doesn't like typecast */
 422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 423         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 424           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 425 #else
 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 429 #endif
 430 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 431
 432 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 433                                         GENERATED_GBL_DATA_SIZE)
 434 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 435
 436 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 437 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 438
 439 /* Serial Port */
 440 #define CONFIG_SYS_NS16550_SERIAL
 441 #define CONFIG_SYS_NS16550_REG_SIZE     1
 442 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 443
 444 #define CONFIG_SYS_BAUDRATE_TABLE       \
 445         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 446
 447 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 448 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 449 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 450 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 451
 452 /* Video */
 453 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 454 #ifdef CONFIG_FSL_DIU_FB
 455 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 456 #define CONFIG_VIDEO_LOGO
 457 #define CONFIG_VIDEO_BMP_LOGO
 458 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 459 /*
 460  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 461  * disable empty flash sector detection, which is I/O-intensive.
 462  */
 463 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 464 #endif
 465
 466 /* I2C */
 467 #define CONFIG_SYS_I2C
 468 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 469 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 470 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 471 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 472 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 473 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 474 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 475
 476 #define I2C_PCA6408_BUS_NUM             1
 477 #define I2C_PCA6408_ADDR                0x20
 478
 479 /* I2C bus multiplexer */
 480 #define I2C_MUX_CH_DEFAULT      0x8
 481
 482 /*
 483  * RTC configuration
 484  */
 485 #define RTC
 486 #define CONFIG_RTC_DS1337       1
 487 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 488
 489 /*
 490  * eSPI - Enhanced SPI
 491  */
 492
 493 /*
 494  * General PCIe
 495  * Memory space is mapped 1-1, but I/O space must start from 0.
 496  */
 497 #define CONFIG_PCIE1            /* PCIE controller 1 */
 498 #define CONFIG_PCIE2            /* PCIE controller 2 */
 499 #define CONFIG_PCIE3            /* PCIE controller 3 */
 500 #ifdef CONFIG_ARCH_T1040
 501 #define CONFIG_PCIE4            /* PCIE controller 4 */
 502 #endif
 503 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 504 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 505 #define CONFIG_PCI_INDIRECT_BRIDGE
 506
 507 #ifdef CONFIG_PCI
 508 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 509 #ifdef CONFIG_PCIE1
 510 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 511 #ifdef CONFIG_PHYS_64BIT
 512 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 513 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 514 #else
 515 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 516 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 517 #endif
 518 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 519 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 520 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 521 #ifdef CONFIG_PHYS_64BIT
 522 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 523 #else
 524 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 525 #endif
 526 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 527 #endif
 528
 529 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 530 #ifdef CONFIG_PCIE2
 531 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 532 #ifdef CONFIG_PHYS_64BIT
 533 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 534 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 535 #else
 536 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 537 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 538 #endif
 539 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 540 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 541 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 542 #ifdef CONFIG_PHYS_64BIT
 543 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 544 #else
 545 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 546 #endif
 547 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 548 #endif
 549
 550 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 551 #ifdef CONFIG_PCIE3
 552 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 553 #ifdef CONFIG_PHYS_64BIT
 554 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 555 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 556 #else
 557 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 558 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 559 #endif
 560 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 561 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 562 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 563 #ifdef CONFIG_PHYS_64BIT
 564 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 565 #else
 566 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 567 #endif
 568 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 569 #endif
 570
 571 /* controller 4, Base address 203000, to be removed */
 572 #ifdef CONFIG_PCIE4
 573 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 574 #ifdef CONFIG_PHYS_64BIT
 575 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 576 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 577 #else
 578 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 579 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 580 #endif
 581 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 582 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 583 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 584 #ifdef CONFIG_PHYS_64BIT
 585 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 586 #else
 587 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 588 #endif
 589 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 590 #endif
 591
 592 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 593 #endif  /* CONFIG_PCI */
 594
 595 /*
 596  * USB
 597  */
 598 #define CONFIG_HAS_FSL_DR_USB
 599
 600 #ifdef CONFIG_HAS_FSL_DR_USB
 601 #define CONFIG_USB_EHCI_FSL
 602 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 603 #endif
 604
 605 /*
 606  * SDHC
 607  */
 608 #ifdef CONFIG_MMC
 609 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 610 #endif
 611
 612 /* Qman/Bman */
 613 #ifndef CONFIG_NOBQFMAN
 614 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 615 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 616 #ifdef CONFIG_PHYS_64BIT
 617 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 618 #else
 619 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 620 #endif
 621 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 622 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 623 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 624 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 625 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 626 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 627                                         CONFIG_SYS_BMAN_CENA_SIZE)
 628 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 629 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 630 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 631 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 632 #ifdef CONFIG_PHYS_64BIT
 633 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 634 #else
 635 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 636 #endif
 637 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 638 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 639 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 640 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 641 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 642 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 643                                         CONFIG_SYS_QMAN_CENA_SIZE)
 644 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 645 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 646
 647 #define CONFIG_SYS_DPAA_FMAN
 648
 649 /* Default address of microcode for the Linux FMan driver */
 650 #if defined(CONFIG_SPIFLASH)
 651 /*
 652  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 653  * env, so we got 0x110000.
 654  */
 655 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 656 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 657 #elif defined(CONFIG_SDCARD)
 658 /*
 659  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 660  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 661  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 662  */
 663 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 664 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 665 #elif defined(CONFIG_NAND)
 666 #if defined(CONFIG_TARGET_T1024RDB)
 667 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 668 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 669 #elif defined(CONFIG_TARGET_T1023RDB)
 670 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 671 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 672 #endif
 673 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 674 /*
 675  * Slave has no ucode locally, it can fetch this from remote. When implementing
 676  * in two corenet boards, slave's ucode could be stored in master's memory
 677  * space, the address can be mapped from slave TLB->slave LAW->
 678  * slave SRIO or PCIE outbound window->master inbound window->
 679  * master LAW->the ucode address in master's memory space.
 680  */
 681 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 682 #else
 683 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 684 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 685 #endif
 686 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 687 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 688 #endif /* CONFIG_NOBQFMAN */
 689
 690 #ifdef CONFIG_SYS_DPAA_FMAN
 691 #define CONFIG_PHY_REALTEK
 692 #if defined(CONFIG_TARGET_T1024RDB)
 693 #define RGMII_PHY1_ADDR         0x2
 694 #define RGMII_PHY2_ADDR         0x6
 695 #define SGMII_AQR_PHY_ADDR      0x2
 696 #define FM1_10GEC1_PHY_ADDR     0x1
 697 #elif defined(CONFIG_TARGET_T1023RDB)
 698 #define RGMII_PHY1_ADDR         0x1
 699 #define SGMII_RTK_PHY_ADDR      0x3
 700 #define SGMII_AQR_PHY_ADDR      0x2
 701 #endif
 702 #endif
 703
 704 #ifdef CONFIG_FMAN_ENET
 705 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 706 #endif
 707
 708 /*
 709  * Dynamic MTD Partition support with mtdparts
 710  */
 711
 712 /*
 713  * Environment
 714  */
 715 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 716 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 717
 718 /*
 719  * Miscellaneous configurable options
 720  */
 721 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 722
 723 /*
 724  * For booting Linux, the board info and command line data
 725  * have to be in the first 64 MB of memory, since this is
 726  * the maximum mapped by the Linux kernel during initialization.
 727  */
 728 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 729 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 730
 731 #ifdef CONFIG_CMD_KGDB
 732 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 733 #endif
 734
 735 /*
 736  * Environment Configuration
 737  */
 738 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 739 #define CONFIG_BOOTFILE         "uImage"
 740 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 741 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 742 #define __USB_PHY_TYPE          utmi
 743
 744 #ifdef CONFIG_ARCH_T1024
 745 #define CONFIG_BOARDNAME t1024rdb
 746 #define BANK_INTLV cs0_cs1
 747 #else
 748 #define CONFIG_BOARDNAME t1023rdb
 749 #define BANK_INTLV  null
 750 #endif
 751
 752 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 753         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 754         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 755         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 756         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 757         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 758         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 759         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 760         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 761         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 762         "netdev=eth0\0"                                         \
 763         "tftpflash=tftpboot $loadaddr $uboot && "               \
 764         "protect off $ubootaddr +$filesize && "                 \
 765         "erase $ubootaddr +$filesize && "                       \
 766         "cp.b $loadaddr $ubootaddr $filesize && "               \
 767         "protect on $ubootaddr +$filesize && "                  \
 768         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 769         "consoledev=ttyS0\0"                                    \
 770         "ramdiskaddr=2000000\0"                                 \
 771         "fdtaddr=1e00000\0"                                     \
 772         "bdev=sda3\0"
 773
 774 #define CONFIG_LINUX                                    \
 775         "setenv bootargs root=/dev/ram rw "             \
 776         "console=$consoledev,$baudrate $othbootargs;"   \
 777         "setenv ramdiskaddr 0x02000000;"                \
 778         "setenv fdtaddr 0x00c00000;"                    \
 779         "setenv loadaddr 0x1000000;"                    \
 780         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 781
 782 #define CONFIG_NFSBOOTCOMMAND                   \
 783         "setenv bootargs root=/dev/nfs rw "     \
 784         "nfsroot=$serverip:$rootpath "          \
 785         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 786         "console=$consoledev,$baudrate $othbootargs;"   \
 787         "tftp $loadaddr $bootfile;"             \
 788         "tftp $fdtaddr $fdtfile;"               \
 789         "bootm $loadaddr - $fdtaddr"
 790
 791 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 792
 793 #include <asm/fsl_secure_boot.h>
 794
 795 #endif  /* __T1024RDB_H */