include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 #ifdef CONFIG_RAMBOOT_PBL
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26
  27 #ifdef CONFIG_MTD_RAW_NAND
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  30 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  39 #endif
  40
  41 #ifdef CONFIG_SDCARD
  42 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  43 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  44 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  45 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  46 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  47 #endif
  48
  49 #endif /* CONFIG_RAMBOOT_PBL */
  50
  51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  52 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  53 #endif
  54
  55 /* PCIe Boot - Master */
  56 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  57 /*
  58  * for slave u-boot IMAGE instored in master memory space,
  59  * PHYS must be aligned based on the SIZE
  60  */
  61 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  62 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  63 #ifdef CONFIG_PHYS_64BIT
  64 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  65 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  66 #else
  67 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  68 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  69 #endif
  70 /*
  71  * for slave UCODE and ENV instored in master memory space,
  72  * PHYS must be aligned based on the SIZE
  73  */
  74 #ifdef CONFIG_PHYS_64BIT
  75 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  76 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  77 #else
  78 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  79 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  80 #endif
  81 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
  82 /* slave core release by master*/
  83 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
  84 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
  85
  86 /* PCIe Boot - Slave */
  87 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  88 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  89 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  90                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  91 /* Set 1M boot space for PCIe boot */
  92 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
  94                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  95 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  96 #endif
  97
  98 /*
  99  * These can be toggled for performance analysis, otherwise use default.
 100  */
 101 #define CONFIG_SYS_CACHE_STASHING
 102 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 103 #ifdef CONFIG_DDR_ECC
 104 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 105 #endif
 106
 107 /*
 108  *  Config the L3 Cache as L3 SRAM
 109  */
 110 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 111 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 112 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 113
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define CONFIG_SYS_DCSRBAR              0xf0000000
 116 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 117 #endif
 118
 119 /* EEPROM */
 120 #define CONFIG_SYS_I2C_EEPROM_NXID
 121 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 122
 123 /*
 124  * DDR Setup
 125  */
 126 #define CONFIG_VERY_BIG_RAM
 127 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 128 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 129 #if defined(CONFIG_TARGET_T1024RDB)
 130 #define CONFIG_SYS_SPD_BUS_NUM  0
 131 #define SPD_EEPROM_ADDRESS      0x51
 132 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 133 #elif defined(CONFIG_TARGET_T1023RDB)
 134 #define CONFIG_SYS_DDR_RAW_TIMING
 135 #define CONFIG_SYS_SDRAM_SIZE   2048
 136 #endif
 137
 138 /*
 139  * IFC Definitions
 140  */
 141 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 144 #else
 145 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 146 #endif
 147
 148 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 149 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 150                                 CSPR_PORT_SIZE_16 | \
 151                                 CSPR_MSEL_NOR | \
 152                                 CSPR_V)
 153 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 154
 155 /* NOR Flash Timing Params */
 156 #if defined(CONFIG_TARGET_T1024RDB)
 157 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 158 #elif defined(CONFIG_TARGET_T1023RDB)
 159 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 160                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 161 #endif
 162 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 163                                 FTIM0_NOR_TEADC(0x5) | \
 164                                 FTIM0_NOR_TEAHC(0x5))
 165 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 166                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 167                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 168 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 169                                 FTIM2_NOR_TCH(0x4) | \
 170                                 FTIM2_NOR_TWPH(0x0E) | \
 171                                 FTIM2_NOR_TWP(0x1c))
 172 #define CONFIG_SYS_NOR_FTIM3    0x0
 173
 174 #define CONFIG_SYS_FLASH_QUIET_TEST
 175 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 176
 177 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 178 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 179 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 180
 181 #define CONFIG_SYS_FLASH_EMPTY_INFO
 182 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 183
 184 #ifdef CONFIG_TARGET_T1024RDB
 185 /* CPLD on IFC */
 186 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 187 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 188 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 189 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 190                                                 | CSPR_PORT_SIZE_8 \
 191                                                 | CSPR_MSEL_GPCM \
 192                                                 | CSPR_V)
 193 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 194 #define CONFIG_SYS_CSOR2                0x0
 195
 196 /* CPLD Timing parameters for IFC CS2 */
 197 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 198                                                 FTIM0_GPCM_TEADC(0x0e) | \
 199                                                 FTIM0_GPCM_TEAHC(0x0e))
 200 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 201                                                 FTIM1_GPCM_TRAD(0x1f))
 202 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 203                                                 FTIM2_GPCM_TCH(0x8) | \
 204                                                 FTIM2_GPCM_TWP(0x1f))
 205 #define CONFIG_SYS_CS2_FTIM3            0x0
 206 #endif
 207
 208 /* NAND Flash on IFC */
 209 #define CONFIG_SYS_NAND_BASE            0xff800000
 210 #ifdef CONFIG_PHYS_64BIT
 211 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 212 #else
 213 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 214 #endif
 215 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 216 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 217                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 218                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 219                                 | CSPR_V)
 220 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 221
 222 #if defined(CONFIG_TARGET_T1024RDB)
 223 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 224                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 225                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 226                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 227                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 228                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 229                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 230 #elif defined(CONFIG_TARGET_T1023RDB)
 231 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 232                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 233                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 234                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 235                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 236                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 237                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 238 #endif
 239
 240 /* ONFI NAND Flash mode0 Timing Params */
 241 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 242                                         FTIM0_NAND_TWP(0x18)   | \
 243                                         FTIM0_NAND_TWCHT(0x07) | \
 244                                         FTIM0_NAND_TWH(0x0a))
 245 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 246                                         FTIM1_NAND_TWBE(0x39)  | \
 247                                         FTIM1_NAND_TRR(0x0e)   | \
 248                                         FTIM1_NAND_TRP(0x18))
 249 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 250                                         FTIM2_NAND_TREH(0x0a) | \
 251                                         FTIM2_NAND_TWHRE(0x1e))
 252 #define CONFIG_SYS_NAND_FTIM3           0x0
 253
 254 #define CONFIG_SYS_NAND_DDR_LAW         11
 255 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 256 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 257
 258 #if defined(CONFIG_MTD_RAW_NAND)
 259 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 260 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 261 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 262 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 263 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 264 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 265 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 266 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 267 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 268 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 269 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 270 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 271 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 272 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 273 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 274 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 275 #else
 276 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 277 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 278 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 279 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 280 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 281 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 282 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 283 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 284 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 285 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 286 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 287 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 288 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 289 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 290 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 291 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 292 #endif
 293
 294 #if defined(CONFIG_RAMBOOT_PBL)
 295 #define CONFIG_SYS_RAMBOOT
 296 #endif
 297
 298 #define CONFIG_HWCONFIG
 299
 300 /* define to use L1 as initial stack */
 301 #define CONFIG_L1_INIT_RAM
 302 #define CONFIG_SYS_INIT_RAM_LOCK
 303 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 304 #ifdef CONFIG_PHYS_64BIT
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 307 /* The assembler doesn't like typecast */
 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 309         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 310           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 311 #else
 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 315 #endif
 316 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 317
 318 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 319
 320 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 321
 322 /* Serial Port */
 323 #define CONFIG_SYS_NS16550_SERIAL
 324 #define CONFIG_SYS_NS16550_REG_SIZE     1
 325 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 326
 327 #define CONFIG_SYS_BAUDRATE_TABLE       \
 328         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 329
 330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 332 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 333 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 334
 335 /* I2C */
 336
 337 #define I2C_PCA6408_BUS_NUM             1
 338 #define I2C_PCA6408_ADDR                0x20
 339
 340 /* I2C bus multiplexer */
 341 #define I2C_MUX_CH_DEFAULT      0x8
 342
 343 /*
 344  * RTC configuration
 345  */
 346 #define RTC
 347 #define CONFIG_RTC_DS1337       1
 348 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 349
 350 /*
 351  * eSPI - Enhanced SPI
 352  */
 353
 354 /*
 355  * General PCIe
 356  * Memory space is mapped 1-1, but I/O space must start from 0.
 357  */
 358 #define CONFIG_PCIE1            /* PCIE controller 1 */
 359 #define CONFIG_PCIE2            /* PCIE controller 2 */
 360 #define CONFIG_PCIE3            /* PCIE controller 3 */
 361
 362 #ifdef CONFIG_PCI
 363 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 364 #ifdef CONFIG_PCIE1
 365 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 366 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 367 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 368 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 369 #endif
 370
 371 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 372 #ifdef CONFIG_PCIE2
 373 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 374 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 375 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 376 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 377 #endif
 378
 379 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 380 #ifdef CONFIG_PCIE3
 381 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 382 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 383 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 384 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 385 #endif
 386
 387 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 388 #endif  /* CONFIG_PCI */
 389
 390 /*
 391  * USB
 392  */
 393
 394 /*
 395  * SDHC
 396  */
 397 #ifdef CONFIG_MMC
 398 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 399 #endif
 400
 401 /* Qman/Bman */
 402 #ifndef CONFIG_NOBQFMAN
 403 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 404 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 405 #ifdef CONFIG_PHYS_64BIT
 406 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 407 #else
 408 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 409 #endif
 410 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 411 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 412 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 413 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 414 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 415 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 416                                         CONFIG_SYS_BMAN_CENA_SIZE)
 417 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 418 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 419 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 420 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 421 #ifdef CONFIG_PHYS_64BIT
 422 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 423 #else
 424 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 425 #endif
 426 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 427 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 428 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 429 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 430 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 431 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 432                                         CONFIG_SYS_QMAN_CENA_SIZE)
 433 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 434 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 435
 436 #define CONFIG_SYS_DPAA_FMAN
 437
 438 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 439 #endif /* CONFIG_NOBQFMAN */
 440
 441 #ifdef CONFIG_SYS_DPAA_FMAN
 442 #if defined(CONFIG_TARGET_T1024RDB)
 443 #define RGMII_PHY1_ADDR         0x2
 444 #define RGMII_PHY2_ADDR         0x6
 445 #define SGMII_AQR_PHY_ADDR      0x2
 446 #define FM1_10GEC1_PHY_ADDR     0x1
 447 #elif defined(CONFIG_TARGET_T1023RDB)
 448 #define RGMII_PHY1_ADDR         0x1
 449 #define SGMII_RTK_PHY_ADDR      0x3
 450 #define SGMII_AQR_PHY_ADDR      0x2
 451 #endif
 452 #endif
 453
 454 /*
 455  * Dynamic MTD Partition support with mtdparts
 456  */
 457
 458 /*
 459  * Environment
 460  */
 461 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 462 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 463
 464 /*
 465  * Miscellaneous configurable options
 466  */
 467
 468 /*
 469  * For booting Linux, the board info and command line data
 470  * have to be in the first 64 MB of memory, since this is
 471  * the maximum mapped by the Linux kernel during initialization.
 472  */
 473 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 474 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 475
 476 /*
 477  * Environment Configuration
 478  */
 479 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 480 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 481 #define __USB_PHY_TYPE          utmi
 482
 483 #ifdef CONFIG_ARCH_T1024
 484 #define ARCH_EXTRA_ENV_SETTINGS \
 485         "bank_intlv=cs0_cs1\0"                  \
 486         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 487         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 488 #else
 489 #define ARCH_EXTRA_ENV_SETTINGS \
 490         "bank_intlv=null\0"                     \
 491         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 492         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 493 #endif
 494
 495 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 496         ARCH_EXTRA_ENV_SETTINGS                                 \
 497         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 498         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 499         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 500         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 501         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 502         "netdev=eth0\0"                                         \
 503         "tftpflash=tftpboot $loadaddr $uboot && "               \
 504         "protect off $ubootaddr +$filesize && "                 \
 505         "erase $ubootaddr +$filesize && "                       \
 506         "cp.b $loadaddr $ubootaddr $filesize && "               \
 507         "protect on $ubootaddr +$filesize && "                  \
 508         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 509         "consoledev=ttyS0\0"                                    \
 510         "ramdiskaddr=2000000\0"                                 \
 511         "fdtaddr=1e00000\0"                                     \
 512         "bdev=sda3\0"
 513
 514 #include <asm/fsl_secure_boot.h>
 515
 516 #endif  /* __T1024RDB_H */