1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T1024/T1023 RDB board configuration file
14 #include <linux/stringify.h>
16 /* High Level Configuration Options */
18 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
20 #ifdef CONFIG_RAMBOOT_PBL
21 #define RESET_VECTOR_OFFSET 0x27FFC
22 #define BOOT_PAGE_OFFSET 0x27000
24 #ifdef CONFIG_MTD_RAW_NAND
25 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
26 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
27 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
30 #ifdef CONFIG_SPIFLASH
31 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
39 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
40 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
41 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
42 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
43 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
46 #endif /* CONFIG_RAMBOOT_PBL */
48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 /* PCIe Boot - Master */
53 #define CONFIG_SRIO_PCIE_BOOT_MASTER
55 * for slave u-boot IMAGE instored in master memory space,
56 * PHYS must be aligned based on the SIZE
58 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
59 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
60 #ifdef CONFIG_PHYS_64BIT
61 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
62 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
64 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
65 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
68 * for slave UCODE and ENV instored in master memory space,
69 * PHYS must be aligned based on the SIZE
71 #ifdef CONFIG_PHYS_64BIT
72 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
73 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
75 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
76 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
78 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
79 /* slave core release by master*/
80 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
81 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
83 /* PCIe Boot - Slave */
84 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
85 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
86 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
87 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
88 /* Set 1M boot space for PCIe boot */
89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
91 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
96 * These can be toggled for performance analysis, otherwise use default.
98 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
100 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
104 * Config the L3 Cache as L3 SRAM
106 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
107 #define CONFIG_SYS_L3_SIZE (256 << 10)
108 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
110 #ifdef CONFIG_PHYS_64BIT
111 #define CONFIG_SYS_DCSRBAR 0xf0000000
112 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
116 #define CONFIG_SYS_I2C_EEPROM_NXID
117 #define CONFIG_SYS_EEPROM_BUS_NUM 0
122 #define CONFIG_VERY_BIG_RAM
123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
125 #if defined(CONFIG_TARGET_T1024RDB)
126 #define SPD_EEPROM_ADDRESS 0x51
127 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
128 #elif defined(CONFIG_TARGET_T1023RDB)
129 #define CONFIG_SYS_SDRAM_SIZE 2048
135 #define CONFIG_SYS_FLASH_BASE 0xe8000000
136 #ifdef CONFIG_PHYS_64BIT
137 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
139 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
142 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
143 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
144 CSPR_PORT_SIZE_16 | \
147 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
149 /* NOR Flash Timing Params */
150 #if defined(CONFIG_TARGET_T1024RDB)
151 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
152 #elif defined(CONFIG_TARGET_T1023RDB)
153 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
154 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
156 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
157 FTIM0_NOR_TEADC(0x5) | \
158 FTIM0_NOR_TEAHC(0x5))
159 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
160 FTIM1_NOR_TRAD_NOR(0x1A) |\
161 FTIM1_NOR_TSEQRAD_NOR(0x13))
162 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
163 FTIM2_NOR_TCH(0x4) | \
164 FTIM2_NOR_TWPH(0x0E) | \
166 #define CONFIG_SYS_NOR_FTIM3 0x0
168 #define CONFIG_SYS_FLASH_QUIET_TEST
169 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
171 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
175 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
177 #ifdef CONFIG_TARGET_T1024RDB
179 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
180 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
181 #define CONFIG_SYS_CSPR2_EXT (0xf)
182 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
186 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
187 #define CONFIG_SYS_CSOR2 0x0
189 /* CPLD Timing parameters for IFC CS2 */
190 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
191 FTIM0_GPCM_TEADC(0x0e) | \
192 FTIM0_GPCM_TEAHC(0x0e))
193 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
194 FTIM1_GPCM_TRAD(0x1f))
195 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
196 FTIM2_GPCM_TCH(0x8) | \
197 FTIM2_GPCM_TWP(0x1f))
198 #define CONFIG_SYS_CS2_FTIM3 0x0
201 /* NAND Flash on IFC */
202 #define CONFIG_SYS_NAND_BASE 0xff800000
203 #ifdef CONFIG_PHYS_64BIT
204 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
206 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
208 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
209 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
210 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
211 | CSPR_MSEL_NAND /* MSEL = NAND */ \
213 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
215 #if defined(CONFIG_TARGET_T1024RDB)
216 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
217 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
218 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
219 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
220 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
221 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
222 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
223 #elif defined(CONFIG_TARGET_T1023RDB)
224 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
225 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
226 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
227 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
228 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
229 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
230 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
233 /* ONFI NAND Flash mode0 Timing Params */
234 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
235 FTIM0_NAND_TWP(0x18) | \
236 FTIM0_NAND_TWCHT(0x07) | \
237 FTIM0_NAND_TWH(0x0a))
238 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
239 FTIM1_NAND_TWBE(0x39) | \
240 FTIM1_NAND_TRR(0x0e) | \
241 FTIM1_NAND_TRP(0x18))
242 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
243 FTIM2_NAND_TREH(0x0a) | \
244 FTIM2_NAND_TWHRE(0x1e))
245 #define CONFIG_SYS_NAND_FTIM3 0x0
247 #define CONFIG_SYS_NAND_DDR_LAW 11
248 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
249 #define CONFIG_SYS_MAX_NAND_DEVICE 1
251 #if defined(CONFIG_MTD_RAW_NAND)
252 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
253 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
254 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
255 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
256 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
257 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
258 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
259 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
260 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
261 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
262 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
263 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
264 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
265 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
266 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
267 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
269 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
270 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
271 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
272 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
273 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
274 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
275 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
276 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
277 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
279 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
280 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
281 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
282 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
283 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
284 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
287 #define CONFIG_HWCONFIG
289 /* define to use L1 as initial stack */
290 #define CONFIG_L1_INIT_RAM
291 #define CONFIG_SYS_INIT_RAM_LOCK
292 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
293 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
296 /* The assembler doesn't like typecast */
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
298 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
299 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
305 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
307 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
309 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
312 #define CONFIG_SYS_NS16550_SERIAL
313 #define CONFIG_SYS_NS16550_REG_SIZE 1
314 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
316 #define CONFIG_SYS_BAUDRATE_TABLE \
317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
321 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
322 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
326 #define I2C_PCA6408_BUS_NUM 1
327 #define I2C_PCA6408_ADDR 0x20
329 /* I2C bus multiplexer */
330 #define I2C_MUX_CH_DEFAULT 0x8
336 #define CONFIG_RTC_DS1337 1
337 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
340 * eSPI - Enhanced SPI
345 * Memory space is mapped 1-1, but I/O space must start from 0.
349 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
351 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
352 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
353 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
354 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
357 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
359 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
360 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
361 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
362 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
365 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
367 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
368 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
369 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
370 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
372 #endif /* CONFIG_PCI */
382 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
386 #ifndef CONFIG_NOBQFMAN
387 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
388 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
389 #ifdef CONFIG_PHYS_64BIT
390 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
392 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
394 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
395 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
396 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
397 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
398 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
399 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
400 CONFIG_SYS_BMAN_CENA_SIZE)
401 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
402 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
403 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
404 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
405 #ifdef CONFIG_PHYS_64BIT
406 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
408 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
410 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
411 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
412 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
413 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
414 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
415 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
416 CONFIG_SYS_QMAN_CENA_SIZE)
417 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
418 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
420 #define CONFIG_SYS_DPAA_FMAN
422 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
423 #endif /* CONFIG_NOBQFMAN */
425 #ifdef CONFIG_SYS_DPAA_FMAN
426 #if defined(CONFIG_TARGET_T1024RDB)
427 #define RGMII_PHY1_ADDR 0x2
428 #define RGMII_PHY2_ADDR 0x6
429 #define SGMII_AQR_PHY_ADDR 0x2
430 #define FM1_10GEC1_PHY_ADDR 0x1
431 #elif defined(CONFIG_TARGET_T1023RDB)
432 #define RGMII_PHY1_ADDR 0x1
433 #define SGMII_RTK_PHY_ADDR 0x3
434 #define SGMII_AQR_PHY_ADDR 0x2
439 * Dynamic MTD Partition support with mtdparts
445 #define CONFIG_LOADS_ECHO /* echo on for serial download */
446 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
449 * Miscellaneous configurable options
453 * For booting Linux, the board info and command line data
454 * have to be in the first 64 MB of memory, since this is
455 * the maximum mapped by the Linux kernel during initialization.
457 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
460 * Environment Configuration
462 #define CONFIG_ROOTPATH "/opt/nfsroot"
463 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
464 #define __USB_PHY_TYPE utmi
466 #ifdef CONFIG_ARCH_T1024
467 #define ARCH_EXTRA_ENV_SETTINGS \
468 "bank_intlv=cs0_cs1\0" \
469 "ramdiskfile=t1024rdb/ramdisk.uboot\0" \
470 "fdtfile=t1024rdb/t1024rdb.dtb\0"
472 #define ARCH_EXTRA_ENV_SETTINGS \
473 "bank_intlv=null\0" \
474 "ramdiskfile=t1023rdb/ramdisk.uboot\0" \
475 "fdtfile=t1023rdb/t1023rdb.dtb\0"
478 #define CONFIG_EXTRA_ENV_SETTINGS \
479 ARCH_EXTRA_ENV_SETTINGS \
480 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
481 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
482 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
483 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
484 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
486 "tftpflash=tftpboot $loadaddr $uboot && " \
487 "protect off $ubootaddr +$filesize && " \
488 "erase $ubootaddr +$filesize && " \
489 "cp.b $loadaddr $ubootaddr $filesize && " \
490 "protect on $ubootaddr +$filesize && " \
491 "cmp.b $loadaddr $ubootaddr $filesize\0" \
492 "consoledev=ttyS0\0" \
493 "ramdiskaddr=2000000\0" \
494 "fdtaddr=1e00000\0" \
497 #include <asm/fsl_secure_boot.h>
499 #endif /* __T1024RDB_H */