include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 /* support deep sleep */
  24 #ifdef CONFIG_ARCH_T1024
  25 #define CONFIG_DEEP_SLEEP
  26 #endif
  27
  28 #ifdef CONFIG_RAMBOOT_PBL
  29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  30 #define CONFIG_SPL_FLUSH_IMAGE
  31 #define CONFIG_SPL_PAD_TO               0x40000
  32 #define CONFIG_SPL_MAX_SIZE             0x28000
  33 #define RESET_VECTOR_OFFSET             0x27FFC
  34 #define BOOT_PAGE_OFFSET                0x27000
  35 #ifdef CONFIG_SPL_BUILD
  36 #define CONFIG_SPL_SKIP_RELOCATE
  37 #define CONFIG_SPL_COMMON_INIT_DDR
  38 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  39 #endif
  40
  41 #ifdef CONFIG_MTD_RAW_NAND
  42 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  43 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  44 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  45 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  46 #if defined(CONFIG_TARGET_T1024RDB)
  47 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  48 #elif defined(CONFIG_TARGET_T1023RDB)
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  50 #endif
  51 #endif
  52
  53 #ifdef CONFIG_SPIFLASH
  54 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  55 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  60 #ifndef CONFIG_SPL_BUILD
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #endif
  63 #if defined(CONFIG_TARGET_T1024RDB)
  64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  65 #elif defined(CONFIG_TARGET_T1023RDB)
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  67 #endif
  68 #endif
  69
  70 #ifdef CONFIG_SDCARD
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  72 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  73 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  74 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  75 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #if defined(CONFIG_TARGET_T1024RDB)
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  81 #elif defined(CONFIG_TARGET_T1023RDB)
  82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  83 #endif
  84 #endif
  85
  86 #endif /* CONFIG_RAMBOOT_PBL */
  87
  88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  89 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  90 #endif
  91
  92 /* PCIe Boot - Master */
  93 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  94 /*
  95  * for slave u-boot IMAGE instored in master memory space,
  96  * PHYS must be aligned based on the SIZE
  97  */
  98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  99 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 103 #else
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 106 #endif
 107 /*
 108  * for slave UCODE and ENV instored in master memory space,
 109  * PHYS must be aligned based on the SIZE
 110  */
 111 #ifdef CONFIG_PHYS_64BIT
 112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 113 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 114 #else
 115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 117 #endif
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 119 /* slave core release by master*/
 120 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 121 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 122
 123 /* PCIe Boot - Slave */
 124 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 126 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 127                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 128 /* Set 1M boot space for PCIe boot */
 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 131                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 132 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 133 #endif
 134
 135 #if defined(CONFIG_SPIFLASH)
 136 #elif defined(CONFIG_SDCARD)
 137 #define CONFIG_SYS_MMC_ENV_DEV          0
 138 #endif
 139
 140 #ifndef __ASSEMBLY__
 141 unsigned long get_board_sys_clk(void);
 142 unsigned long get_board_ddr_clk(void);
 143 #endif
 144
 145 #define CONFIG_SYS_CLK_FREQ     100000000
 146 #define CONFIG_DDR_CLK_FREQ     100000000
 147
 148 /*
 149  * These can be toggled for performance analysis, otherwise use default.
 150  */
 151 #define CONFIG_SYS_CACHE_STASHING
 152 #define CONFIG_BACKSIDE_L2_CACHE
 153 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 154 #define CONFIG_BTB                      /* toggle branch predition */
 155 #define CONFIG_DDR_ECC
 156 #ifdef CONFIG_DDR_ECC
 157 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 158 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 159 #endif
 160
 161 /*
 162  *  Config the L3 Cache as L3 SRAM
 163  */
 164 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 165 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 166 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 167 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 168 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 169 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 170 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 171
 172 #ifdef CONFIG_PHYS_64BIT
 173 #define CONFIG_SYS_DCSRBAR              0xf0000000
 174 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 175 #endif
 176
 177 /* EEPROM */
 178 #define CONFIG_ID_EEPROM
 179 #define CONFIG_SYS_I2C_EEPROM_NXID
 180 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 185
 186 /*
 187  * DDR Setup
 188  */
 189 #define CONFIG_VERY_BIG_RAM
 190 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 191 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 192 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 193 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 194 #if defined(CONFIG_TARGET_T1024RDB)
 195 #define CONFIG_DDR_SPD
 196 #define CONFIG_SYS_SPD_BUS_NUM  0
 197 #define SPD_EEPROM_ADDRESS      0x51
 198 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 199 #elif defined(CONFIG_TARGET_T1023RDB)
 200 #define CONFIG_SYS_DDR_RAW_TIMING
 201 #define CONFIG_SYS_SDRAM_SIZE   2048
 202 #endif
 203
 204 /*
 205  * IFC Definitions
 206  */
 207 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 208 #ifdef CONFIG_PHYS_64BIT
 209 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 210 #else
 211 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 212 #endif
 213
 214 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 215 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 216                                 CSPR_PORT_SIZE_16 | \
 217                                 CSPR_MSEL_NOR | \
 218                                 CSPR_V)
 219 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 220
 221 /* NOR Flash Timing Params */
 222 #if defined(CONFIG_TARGET_T1024RDB)
 223 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 224 #elif defined(CONFIG_TARGET_T1023RDB)
 225 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 226                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 227 #endif
 228 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 229                                 FTIM0_NOR_TEADC(0x5) | \
 230                                 FTIM0_NOR_TEAHC(0x5))
 231 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 232                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 233                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 234 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 235                                 FTIM2_NOR_TCH(0x4) | \
 236                                 FTIM2_NOR_TWPH(0x0E) | \
 237                                 FTIM2_NOR_TWP(0x1c))
 238 #define CONFIG_SYS_NOR_FTIM3    0x0
 239
 240 #define CONFIG_SYS_FLASH_QUIET_TEST
 241 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 242
 243 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 244 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 245 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 246 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 247
 248 #define CONFIG_SYS_FLASH_EMPTY_INFO
 249 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 250
 251 #ifdef CONFIG_TARGET_T1024RDB
 252 /* CPLD on IFC */
 253 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 254 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 255 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 256 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 257                                                 | CSPR_PORT_SIZE_8 \
 258                                                 | CSPR_MSEL_GPCM \
 259                                                 | CSPR_V)
 260 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 261 #define CONFIG_SYS_CSOR2                0x0
 262
 263 /* CPLD Timing parameters for IFC CS2 */
 264 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 265                                                 FTIM0_GPCM_TEADC(0x0e) | \
 266                                                 FTIM0_GPCM_TEAHC(0x0e))
 267 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 268                                                 FTIM1_GPCM_TRAD(0x1f))
 269 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 270                                                 FTIM2_GPCM_TCH(0x8) | \
 271                                                 FTIM2_GPCM_TWP(0x1f))
 272 #define CONFIG_SYS_CS2_FTIM3            0x0
 273 #endif
 274
 275 /* NAND Flash on IFC */
 276 #define CONFIG_NAND_FSL_IFC
 277 #define CONFIG_SYS_NAND_BASE            0xff800000
 278 #ifdef CONFIG_PHYS_64BIT
 279 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 280 #else
 281 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 282 #endif
 283 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 284 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 285                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 286                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 287                                 | CSPR_V)
 288 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 289
 290 #if defined(CONFIG_TARGET_T1024RDB)
 291 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 292                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 293                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 294                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 295                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 296                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 297                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 298 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 299 #elif defined(CONFIG_TARGET_T1023RDB)
 300 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 301                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 302                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 303                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 304                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 305                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 306                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 307 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 308 #endif
 309
 310 #define CONFIG_SYS_NAND_ONFI_DETECTION
 311 /* ONFI NAND Flash mode0 Timing Params */
 312 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 313                                         FTIM0_NAND_TWP(0x18)   | \
 314                                         FTIM0_NAND_TWCHT(0x07) | \
 315                                         FTIM0_NAND_TWH(0x0a))
 316 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 317                                         FTIM1_NAND_TWBE(0x39)  | \
 318                                         FTIM1_NAND_TRR(0x0e)   | \
 319                                         FTIM1_NAND_TRP(0x18))
 320 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 321                                         FTIM2_NAND_TREH(0x0a) | \
 322                                         FTIM2_NAND_TWHRE(0x1e))
 323 #define CONFIG_SYS_NAND_FTIM3           0x0
 324
 325 #define CONFIG_SYS_NAND_DDR_LAW         11
 326 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 327 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 328
 329 #if defined(CONFIG_MTD_RAW_NAND)
 330 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 331 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 332 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 333 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 334 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 335 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 336 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 337 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 338 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 339 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 340 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 341 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 342 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 343 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 344 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 345 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 346 #else
 347 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 348 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 349 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 350 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 351 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 352 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 353 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 354 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 355 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 356 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 357 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 358 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 359 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 360 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 361 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 362 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 363 #endif
 364
 365 #ifdef CONFIG_SPL_BUILD
 366 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 367 #else
 368 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 369 #endif
 370
 371 #if defined(CONFIG_RAMBOOT_PBL)
 372 #define CONFIG_SYS_RAMBOOT
 373 #endif
 374
 375 #define CONFIG_HWCONFIG
 376
 377 /* define to use L1 as initial stack */
 378 #define CONFIG_L1_INIT_RAM
 379 #define CONFIG_SYS_INIT_RAM_LOCK
 380 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 381 #ifdef CONFIG_PHYS_64BIT
 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 384 /* The assembler doesn't like typecast */
 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 386         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 387           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 388 #else
 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 392 #endif
 393 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 394
 395 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 396                                         GENERATED_GBL_DATA_SIZE)
 397 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 398
 399 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 400 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 401
 402 /* Serial Port */
 403 #define CONFIG_SYS_NS16550_SERIAL
 404 #define CONFIG_SYS_NS16550_REG_SIZE     1
 405 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 406
 407 #define CONFIG_SYS_BAUDRATE_TABLE       \
 408         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 409
 410 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 411 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 412 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 413 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 414
 415 /* Video */
 416 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 417 #ifdef CONFIG_FSL_DIU_FB
 418 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 419 #define CONFIG_VIDEO_LOGO
 420 #define CONFIG_VIDEO_BMP_LOGO
 421 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 422 /*
 423  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 424  * disable empty flash sector detection, which is I/O-intensive.
 425  */
 426 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 427 #endif
 428
 429 /* I2C */
 430 #ifndef CONFIG_DM_I2C
 431 #define CONFIG_SYS_I2C
 432 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 433 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 434 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 435 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 436 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 437 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 438 #else
 439 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 440 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 441 #endif
 442
 443 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 444 #define I2C_PCA6408_BUS_NUM             1
 445 #define I2C_PCA6408_ADDR                0x20
 446
 447 /* I2C bus multiplexer */
 448 #define I2C_MUX_CH_DEFAULT      0x8
 449
 450 /*
 451  * RTC configuration
 452  */
 453 #define RTC
 454 #define CONFIG_RTC_DS1337       1
 455 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 456
 457 /*
 458  * eSPI - Enhanced SPI
 459  */
 460
 461 /*
 462  * General PCIe
 463  * Memory space is mapped 1-1, but I/O space must start from 0.
 464  */
 465 #define CONFIG_PCIE1            /* PCIE controller 1 */
 466 #define CONFIG_PCIE2            /* PCIE controller 2 */
 467 #define CONFIG_PCIE3            /* PCIE controller 3 */
 468 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 469
 470 #ifdef CONFIG_PCI
 471 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 472 #ifdef CONFIG_PCIE1
 473 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 474 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 475 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 476 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 477 #endif
 478
 479 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 480 #ifdef CONFIG_PCIE2
 481 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 482 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 483 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 484 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 485 #endif
 486
 487 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 488 #ifdef CONFIG_PCIE3
 489 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 490 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 491 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 492 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 493 #endif
 494
 495 #if !defined(CONFIG_DM_PCI)
 496 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 497 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 498 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 499 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 500 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 501 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 502 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 503 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 504 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 505 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 506 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 507 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 508 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 509 #define CONFIG_PCI_INDIRECT_BRIDGE
 510 #endif
 511
 512 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 513 #endif  /* CONFIG_PCI */
 514
 515 /*
 516  * USB
 517  */
 518 #define CONFIG_HAS_FSL_DR_USB
 519
 520 #ifdef CONFIG_HAS_FSL_DR_USB
 521 #define CONFIG_USB_EHCI_FSL
 522 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 523 #endif
 524
 525 /*
 526  * SDHC
 527  */
 528 #ifdef CONFIG_MMC
 529 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 530 #endif
 531
 532 /* Qman/Bman */
 533 #ifndef CONFIG_NOBQFMAN
 534 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 535 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 536 #ifdef CONFIG_PHYS_64BIT
 537 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 538 #else
 539 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 540 #endif
 541 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 542 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 543 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 544 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 545 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 546 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 547                                         CONFIG_SYS_BMAN_CENA_SIZE)
 548 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 549 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 550 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 551 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 552 #ifdef CONFIG_PHYS_64BIT
 553 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 554 #else
 555 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 556 #endif
 557 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 558 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 559 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 560 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 561 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 562 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 563                                         CONFIG_SYS_QMAN_CENA_SIZE)
 564 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 565 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 566
 567 #define CONFIG_SYS_DPAA_FMAN
 568
 569 /* Default address of microcode for the Linux FMan driver */
 570 #if defined(CONFIG_SPIFLASH)
 571 /*
 572  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 573  * env, so we got 0x110000.
 574  */
 575 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 576 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 577 #elif defined(CONFIG_SDCARD)
 578 /*
 579  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 580  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 581  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 582  */
 583 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 584 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 585 #elif defined(CONFIG_MTD_RAW_NAND)
 586 #if defined(CONFIG_TARGET_T1024RDB)
 587 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 588 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 589 #elif defined(CONFIG_TARGET_T1023RDB)
 590 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 591 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 592 #endif
 593 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 594 /*
 595  * Slave has no ucode locally, it can fetch this from remote. When implementing
 596  * in two corenet boards, slave's ucode could be stored in master's memory
 597  * space, the address can be mapped from slave TLB->slave LAW->
 598  * slave SRIO or PCIE outbound window->master inbound window->
 599  * master LAW->the ucode address in master's memory space.
 600  */
 601 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 602 #else
 603 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 604 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 605 #endif
 606 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 607 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 608 #endif /* CONFIG_NOBQFMAN */
 609
 610 #ifdef CONFIG_SYS_DPAA_FMAN
 611 #if defined(CONFIG_TARGET_T1024RDB)
 612 #define RGMII_PHY1_ADDR         0x2
 613 #define RGMII_PHY2_ADDR         0x6
 614 #define SGMII_AQR_PHY_ADDR      0x2
 615 #define FM1_10GEC1_PHY_ADDR     0x1
 616 #elif defined(CONFIG_TARGET_T1023RDB)
 617 #define RGMII_PHY1_ADDR         0x1
 618 #define SGMII_RTK_PHY_ADDR      0x3
 619 #define SGMII_AQR_PHY_ADDR      0x2
 620 #endif
 621 #endif
 622
 623 #ifdef CONFIG_FMAN_ENET
 624 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 625 #endif
 626
 627 /*
 628  * Dynamic MTD Partition support with mtdparts
 629  */
 630
 631 /*
 632  * Environment
 633  */
 634 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 635 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 636
 637 /*
 638  * Miscellaneous configurable options
 639  */
 640 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 641
 642 /*
 643  * For booting Linux, the board info and command line data
 644  * have to be in the first 64 MB of memory, since this is
 645  * the maximum mapped by the Linux kernel during initialization.
 646  */
 647 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 648 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 649
 650 #ifdef CONFIG_CMD_KGDB
 651 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 652 #endif
 653
 654 /*
 655  * Environment Configuration
 656  */
 657 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 658 #define CONFIG_BOOTFILE         "uImage"
 659 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 660 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 661 #define __USB_PHY_TYPE          utmi
 662
 663 #ifdef CONFIG_ARCH_T1024
 664 #define CONFIG_BOARDNAME t1024rdb
 665 #define BANK_INTLV cs0_cs1
 666 #else
 667 #define CONFIG_BOARDNAME t1023rdb
 668 #define BANK_INTLV  null
 669 #endif
 670
 671 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 672         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 673         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 674         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 675         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 676         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 677         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 678         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 679         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 680         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 681         "netdev=eth0\0"                                         \
 682         "tftpflash=tftpboot $loadaddr $uboot && "               \
 683         "protect off $ubootaddr +$filesize && "                 \
 684         "erase $ubootaddr +$filesize && "                       \
 685         "cp.b $loadaddr $ubootaddr $filesize && "               \
 686         "protect on $ubootaddr +$filesize && "                  \
 687         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 688         "consoledev=ttyS0\0"                                    \
 689         "ramdiskaddr=2000000\0"                                 \
 690         "fdtaddr=1e00000\0"                                     \
 691         "bdev=sda3\0"
 692
 693 #define CONFIG_LINUX                                    \
 694         "setenv bootargs root=/dev/ram rw "             \
 695         "console=$consoledev,$baudrate $othbootargs;"   \
 696         "setenv ramdiskaddr 0x02000000;"                \
 697         "setenv fdtaddr 0x00c00000;"                    \
 698         "setenv loadaddr 0x1000000;"                    \
 699         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 700
 701 #define CONFIG_NFSBOOTCOMMAND                   \
 702         "setenv bootargs root=/dev/nfs rw "     \
 703         "nfsroot=$serverip:$rootpath "          \
 704         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 705         "console=$consoledev,$baudrate $othbootargs;"   \
 706         "tftp $loadaddr $bootfile;"             \
 707         "tftp $fdtaddr $fdtfile;"               \
 708         "bootm $loadaddr - $fdtaddr"
 709
 710 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 711
 712 #include <asm/fsl_secure_boot.h>
 713
 714 #endif  /* __T1024RDB_H */