1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T1024/T1023 RDB board configuration file
14 #include <linux/stringify.h>
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
20 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
21 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
23 #define CONFIG_ENV_OVERWRITE
25 /* support deep sleep */
26 #ifdef CONFIG_ARCH_T1024
27 #define CONFIG_DEEP_SLEEP
30 #ifdef CONFIG_RAMBOOT_PBL
31 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_PAD_TO 0x40000
34 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SPL_SKIP_RELOCATE
39 #define CONFIG_SPL_COMMON_INIT_DDR
40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43 #ifdef CONFIG_MTD_RAW_NAND
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
46 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
48 #if defined(CONFIG_TARGET_T1024RDB)
49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
50 #elif defined(CONFIG_TARGET_T1023RDB)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
55 #ifdef CONFIG_SPIFLASH
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
57 #define CONFIG_SPL_SPI_FLASH_MINIMAL
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
62 #ifndef CONFIG_SPL_BUILD
63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
65 #if defined(CONFIG_TARGET_T1024RDB)
66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
67 #elif defined(CONFIG_TARGET_T1023RDB)
68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
73 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
74 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
75 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
76 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
77 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
78 #ifndef CONFIG_SPL_BUILD
79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
81 #if defined(CONFIG_TARGET_T1024RDB)
82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
83 #elif defined(CONFIG_TARGET_T1023RDB)
84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
88 #endif /* CONFIG_RAMBOOT_PBL */
90 #ifndef CONFIG_RESET_VECTOR_ADDRESS
91 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
94 /* PCIe Boot - Master */
95 #define CONFIG_SRIO_PCIE_BOOT_MASTER
97 * for slave u-boot IMAGE instored in master memory space,
98 * PHYS must be aligned based on the SIZE
100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
102 #ifdef CONFIG_PHYS_64BIT
103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
110 * for slave UCODE and ENV instored in master memory space,
111 * PHYS must be aligned based on the SIZE
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
121 /* slave core release by master*/
122 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
123 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
125 /* PCIe Boot - Slave */
126 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
127 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
128 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
129 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
130 /* Set 1M boot space for PCIe boot */
131 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
132 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
133 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
134 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
137 #if defined(CONFIG_SPIFLASH)
138 #elif defined(CONFIG_SDCARD)
139 #define CONFIG_SYS_MMC_ENV_DEV 0
143 unsigned long get_board_sys_clk(void);
144 unsigned long get_board_ddr_clk(void);
147 #define CONFIG_SYS_CLK_FREQ 100000000
148 #define CONFIG_DDR_CLK_FREQ 100000000
151 * These can be toggled for performance analysis, otherwise use default.
153 #define CONFIG_SYS_CACHE_STASHING
154 #define CONFIG_BACKSIDE_L2_CACHE
155 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
156 #define CONFIG_BTB /* toggle branch predition */
157 #define CONFIG_DDR_ECC
158 #ifdef CONFIG_DDR_ECC
159 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
160 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
164 * Config the L3 Cache as L3 SRAM
166 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
167 #define CONFIG_SYS_L3_SIZE (256 << 10)
168 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
169 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
170 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
171 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
172 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
174 #ifdef CONFIG_PHYS_64BIT
175 #define CONFIG_SYS_DCSRBAR 0xf0000000
176 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
180 #define CONFIG_ID_EEPROM
181 #define CONFIG_SYS_I2C_EEPROM_NXID
182 #define CONFIG_SYS_EEPROM_BUS_NUM 0
183 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
186 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
191 #define CONFIG_VERY_BIG_RAM
192 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
193 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
194 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
195 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
196 #if defined(CONFIG_TARGET_T1024RDB)
197 #define CONFIG_DDR_SPD
198 #define CONFIG_SYS_SPD_BUS_NUM 0
199 #define SPD_EEPROM_ADDRESS 0x51
200 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
201 #elif defined(CONFIG_TARGET_T1023RDB)
202 #define CONFIG_SYS_DDR_RAW_TIMING
203 #define CONFIG_SYS_SDRAM_SIZE 2048
209 #define CONFIG_SYS_FLASH_BASE 0xe8000000
210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
216 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
217 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
218 CSPR_PORT_SIZE_16 | \
221 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
223 /* NOR Flash Timing Params */
224 #if defined(CONFIG_TARGET_T1024RDB)
225 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
226 #elif defined(CONFIG_TARGET_T1023RDB)
227 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
228 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
230 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
231 FTIM0_NOR_TEADC(0x5) | \
232 FTIM0_NOR_TEAHC(0x5))
233 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
234 FTIM1_NOR_TRAD_NOR(0x1A) |\
235 FTIM1_NOR_TSEQRAD_NOR(0x13))
236 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
237 FTIM2_NOR_TCH(0x4) | \
238 FTIM2_NOR_TWPH(0x0E) | \
240 #define CONFIG_SYS_NOR_FTIM3 0x0
242 #define CONFIG_SYS_FLASH_QUIET_TEST
243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
246 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
247 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
248 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
250 #define CONFIG_SYS_FLASH_EMPTY_INFO
251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
253 #ifdef CONFIG_TARGET_T1024RDB
255 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
256 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
257 #define CONFIG_SYS_CSPR2_EXT (0xf)
258 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
262 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
263 #define CONFIG_SYS_CSOR2 0x0
265 /* CPLD Timing parameters for IFC CS2 */
266 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
267 FTIM0_GPCM_TEADC(0x0e) | \
268 FTIM0_GPCM_TEAHC(0x0e))
269 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
270 FTIM1_GPCM_TRAD(0x1f))
271 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
272 FTIM2_GPCM_TCH(0x8) | \
273 FTIM2_GPCM_TWP(0x1f))
274 #define CONFIG_SYS_CS2_FTIM3 0x0
277 /* NAND Flash on IFC */
278 #define CONFIG_NAND_FSL_IFC
279 #define CONFIG_SYS_NAND_BASE 0xff800000
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
283 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
285 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
286 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
287 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
288 | CSPR_MSEL_NAND /* MSEL = NAND */ \
290 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
292 #if defined(CONFIG_TARGET_T1024RDB)
293 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
296 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
297 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
298 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
299 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
300 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
301 #elif defined(CONFIG_TARGET_T1023RDB)
302 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
303 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
304 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
305 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
306 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
307 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
308 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
312 #define CONFIG_SYS_NAND_ONFI_DETECTION
313 /* ONFI NAND Flash mode0 Timing Params */
314 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
315 FTIM0_NAND_TWP(0x18) | \
316 FTIM0_NAND_TWCHT(0x07) | \
317 FTIM0_NAND_TWH(0x0a))
318 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
319 FTIM1_NAND_TWBE(0x39) | \
320 FTIM1_NAND_TRR(0x0e) | \
321 FTIM1_NAND_TRP(0x18))
322 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
323 FTIM2_NAND_TREH(0x0a) | \
324 FTIM2_NAND_TWHRE(0x1e))
325 #define CONFIG_SYS_NAND_FTIM3 0x0
327 #define CONFIG_SYS_NAND_DDR_LAW 11
328 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
329 #define CONFIG_SYS_MAX_NAND_DEVICE 1
331 #if defined(CONFIG_MTD_RAW_NAND)
332 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
333 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
334 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
335 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
336 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
337 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
338 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
339 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
340 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
341 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
342 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
343 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
344 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
345 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
346 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
347 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
357 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
358 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
359 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
360 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
361 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
362 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
363 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
364 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
367 #ifdef CONFIG_SPL_BUILD
368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
370 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
373 #if defined(CONFIG_RAMBOOT_PBL)
374 #define CONFIG_SYS_RAMBOOT
377 #define CONFIG_HWCONFIG
379 /* define to use L1 as initial stack */
380 #define CONFIG_L1_INIT_RAM
381 #define CONFIG_SYS_INIT_RAM_LOCK
382 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
383 #ifdef CONFIG_PHYS_64BIT
384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
386 /* The assembler doesn't like typecast */
387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
388 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
389 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
395 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
397 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
398 GENERATED_GBL_DATA_SIZE)
399 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
401 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
402 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
405 #define CONFIG_SYS_NS16550_SERIAL
406 #define CONFIG_SYS_NS16550_REG_SIZE 1
407 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
409 #define CONFIG_SYS_BAUDRATE_TABLE \
410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
414 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
415 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
418 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
419 #ifdef CONFIG_FSL_DIU_FB
420 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
421 #define CONFIG_VIDEO_LOGO
422 #define CONFIG_VIDEO_BMP_LOGO
423 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
425 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
426 * disable empty flash sector detection, which is I/O-intensive.
428 #undef CONFIG_SYS_FLASH_EMPTY_INFO
432 #ifndef CONFIG_DM_I2C
433 #define CONFIG_SYS_I2C
434 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
435 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
436 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
437 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
438 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
441 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
442 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
445 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
446 #define I2C_PCA6408_BUS_NUM 1
447 #define I2C_PCA6408_ADDR 0x20
449 /* I2C bus multiplexer */
450 #define I2C_MUX_CH_DEFAULT 0x8
456 #define CONFIG_RTC_DS1337 1
457 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
460 * eSPI - Enhanced SPI
465 * Memory space is mapped 1-1, but I/O space must start from 0.
467 #define CONFIG_PCIE1 /* PCIE controller 1 */
468 #define CONFIG_PCIE2 /* PCIE controller 2 */
469 #define CONFIG_PCIE3 /* PCIE controller 3 */
470 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
473 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
475 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
476 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
477 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
478 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
481 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
483 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
484 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
485 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
486 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
489 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
491 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
492 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
493 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
494 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
497 #if !defined(CONFIG_DM_PCI)
498 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
499 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
500 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
501 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
502 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
503 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
504 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
505 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
506 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
507 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
508 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
509 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
510 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
511 #define CONFIG_PCI_INDIRECT_BRIDGE
514 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
515 #endif /* CONFIG_PCI */
520 #define CONFIG_HAS_FSL_DR_USB
522 #ifdef CONFIG_HAS_FSL_DR_USB
523 #define CONFIG_USB_EHCI_FSL
524 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
531 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
535 #ifndef CONFIG_NOBQFMAN
536 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
537 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
538 #ifdef CONFIG_PHYS_64BIT
539 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
541 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
543 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
544 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
545 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
546 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
547 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
548 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
549 CONFIG_SYS_BMAN_CENA_SIZE)
550 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
551 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
552 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
553 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
554 #ifdef CONFIG_PHYS_64BIT
555 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
557 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
559 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
560 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
561 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
562 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
563 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
564 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
565 CONFIG_SYS_QMAN_CENA_SIZE)
566 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
567 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
569 #define CONFIG_SYS_DPAA_FMAN
571 /* Default address of microcode for the Linux FMan driver */
572 #if defined(CONFIG_SPIFLASH)
574 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
575 * env, so we got 0x110000.
577 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
578 #define CONFIG_SYS_QE_FW_ADDR 0x130000
579 #elif defined(CONFIG_SDCARD)
581 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
582 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
583 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
585 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
586 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
587 #elif defined(CONFIG_MTD_RAW_NAND)
588 #if defined(CONFIG_TARGET_T1024RDB)
589 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
590 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
591 #elif defined(CONFIG_TARGET_T1023RDB)
592 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
593 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
595 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
597 * Slave has no ucode locally, it can fetch this from remote. When implementing
598 * in two corenet boards, slave's ucode could be stored in master's memory
599 * space, the address can be mapped from slave TLB->slave LAW->
600 * slave SRIO or PCIE outbound window->master inbound window->
601 * master LAW->the ucode address in master's memory space.
603 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
605 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
606 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
608 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
609 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
610 #endif /* CONFIG_NOBQFMAN */
612 #ifdef CONFIG_SYS_DPAA_FMAN
613 #if defined(CONFIG_TARGET_T1024RDB)
614 #define RGMII_PHY1_ADDR 0x2
615 #define RGMII_PHY2_ADDR 0x6
616 #define SGMII_AQR_PHY_ADDR 0x2
617 #define FM1_10GEC1_PHY_ADDR 0x1
618 #elif defined(CONFIG_TARGET_T1023RDB)
619 #define RGMII_PHY1_ADDR 0x1
620 #define SGMII_RTK_PHY_ADDR 0x3
621 #define SGMII_AQR_PHY_ADDR 0x2
625 #ifdef CONFIG_FMAN_ENET
626 #define CONFIG_ETHPRIME "FM1@DTSEC4"
630 * Dynamic MTD Partition support with mtdparts
636 #define CONFIG_LOADS_ECHO /* echo on for serial download */
637 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
640 * Miscellaneous configurable options
642 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
645 * For booting Linux, the board info and command line data
646 * have to be in the first 64 MB of memory, since this is
647 * the maximum mapped by the Linux kernel during initialization.
649 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
650 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
652 #ifdef CONFIG_CMD_KGDB
653 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
657 * Environment Configuration
659 #define CONFIG_ROOTPATH "/opt/nfsroot"
660 #define CONFIG_BOOTFILE "uImage"
661 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
662 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
663 #define __USB_PHY_TYPE utmi
665 #ifdef CONFIG_ARCH_T1024
666 #define CONFIG_BOARDNAME t1024rdb
667 #define BANK_INTLV cs0_cs1
669 #define CONFIG_BOARDNAME t1023rdb
670 #define BANK_INTLV null
673 #define CONFIG_EXTRA_ENV_SETTINGS \
674 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
675 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
676 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
677 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
678 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
679 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
680 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
681 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
682 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
684 "tftpflash=tftpboot $loadaddr $uboot && " \
685 "protect off $ubootaddr +$filesize && " \
686 "erase $ubootaddr +$filesize && " \
687 "cp.b $loadaddr $ubootaddr $filesize && " \
688 "protect on $ubootaddr +$filesize && " \
689 "cmp.b $loadaddr $ubootaddr $filesize\0" \
690 "consoledev=ttyS0\0" \
691 "ramdiskaddr=2000000\0" \
692 "fdtaddr=1e00000\0" \
695 #define CONFIG_LINUX \
696 "setenv bootargs root=/dev/ram rw " \
697 "console=$consoledev,$baudrate $othbootargs;" \
698 "setenv ramdiskaddr 0x02000000;" \
699 "setenv fdtaddr 0x00c00000;" \
700 "setenv loadaddr 0x1000000;" \
701 "bootm $loadaddr $ramdiskaddr $fdtaddr"
703 #define CONFIG_NFSBOOTCOMMAND \
704 "setenv bootargs root=/dev/nfs rw " \
705 "nfsroot=$serverip:$rootpath " \
706 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
707 "console=$consoledev,$baudrate $othbootargs;" \
708 "tftp $loadaddr $bootfile;" \
709 "tftp $fdtaddr $fdtfile;" \
710 "bootm $loadaddr - $fdtaddr"
712 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
714 #include <asm/fsl_secure_boot.h>
716 #endif /* __T1024RDB_H */