1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T1024/T1023 RDB board configuration file
14 #include <linux/stringify.h>
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
20 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
21 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
23 #ifdef CONFIG_RAMBOOT_PBL
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_PAD_TO 0x40000
26 #define CONFIG_SPL_MAX_SIZE 0x28000
27 #define RESET_VECTOR_OFFSET 0x27FFC
28 #define BOOT_PAGE_OFFSET 0x27000
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SPL_SKIP_RELOCATE
31 #define CONFIG_SPL_COMMON_INIT_DDR
32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
35 #ifdef CONFIG_MTD_RAW_NAND
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
38 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
41 #ifdef CONFIG_SPIFLASH
42 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
43 #define CONFIG_SPL_SPI_FLASH_MINIMAL
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
48 #ifndef CONFIG_SPL_BUILD
49 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
54 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
55 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
56 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
57 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
58 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
59 #ifndef CONFIG_SPL_BUILD
60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
64 #endif /* CONFIG_RAMBOOT_PBL */
66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
67 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
70 /* PCIe Boot - Master */
71 #define CONFIG_SRIO_PCIE_BOOT_MASTER
73 * for slave u-boot IMAGE instored in master memory space,
74 * PHYS must be aligned based on the SIZE
76 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
77 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
78 #ifdef CONFIG_PHYS_64BIT
79 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
80 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
83 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
86 * for slave UCODE and ENV instored in master memory space,
87 * PHYS must be aligned based on the SIZE
89 #ifdef CONFIG_PHYS_64BIT
90 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
91 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
93 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
94 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
96 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
97 /* slave core release by master*/
98 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
99 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
101 /* PCIe Boot - Slave */
102 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
103 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
104 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
105 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
106 /* Set 1M boot space for PCIe boot */
107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
108 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
109 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
110 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
114 * These can be toggled for performance analysis, otherwise use default.
116 #define CONFIG_SYS_CACHE_STASHING
117 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
123 * Config the L3 Cache as L3 SRAM
125 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
126 #define CONFIG_SYS_L3_SIZE (256 << 10)
127 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
128 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
129 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
130 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
131 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_SYS_DCSRBAR 0xf0000000
135 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
139 #define CONFIG_SYS_I2C_EEPROM_NXID
140 #define CONFIG_SYS_EEPROM_BUS_NUM 0
145 #define CONFIG_VERY_BIG_RAM
146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
149 #if defined(CONFIG_TARGET_T1024RDB)
150 #define CONFIG_SYS_SPD_BUS_NUM 0
151 #define SPD_EEPROM_ADDRESS 0x51
152 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
153 #elif defined(CONFIG_TARGET_T1023RDB)
154 #define CONFIG_SYS_DDR_RAW_TIMING
155 #define CONFIG_SYS_SDRAM_SIZE 2048
161 #define CONFIG_SYS_FLASH_BASE 0xe8000000
162 #ifdef CONFIG_PHYS_64BIT
163 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
165 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
168 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
169 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
170 CSPR_PORT_SIZE_16 | \
173 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
175 /* NOR Flash Timing Params */
176 #if defined(CONFIG_TARGET_T1024RDB)
177 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
178 #elif defined(CONFIG_TARGET_T1023RDB)
179 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
180 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
182 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
183 FTIM0_NOR_TEADC(0x5) | \
184 FTIM0_NOR_TEAHC(0x5))
185 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
186 FTIM1_NOR_TRAD_NOR(0x1A) |\
187 FTIM1_NOR_TSEQRAD_NOR(0x13))
188 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
189 FTIM2_NOR_TCH(0x4) | \
190 FTIM2_NOR_TWPH(0x0E) | \
192 #define CONFIG_SYS_NOR_FTIM3 0x0
194 #define CONFIG_SYS_FLASH_QUIET_TEST
195 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
197 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
198 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
201 #define CONFIG_SYS_FLASH_EMPTY_INFO
202 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
204 #ifdef CONFIG_TARGET_T1024RDB
206 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
207 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
208 #define CONFIG_SYS_CSPR2_EXT (0xf)
209 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
213 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
214 #define CONFIG_SYS_CSOR2 0x0
216 /* CPLD Timing parameters for IFC CS2 */
217 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
218 FTIM0_GPCM_TEADC(0x0e) | \
219 FTIM0_GPCM_TEAHC(0x0e))
220 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
221 FTIM1_GPCM_TRAD(0x1f))
222 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
223 FTIM2_GPCM_TCH(0x8) | \
224 FTIM2_GPCM_TWP(0x1f))
225 #define CONFIG_SYS_CS2_FTIM3 0x0
228 /* NAND Flash on IFC */
229 #define CONFIG_SYS_NAND_BASE 0xff800000
230 #ifdef CONFIG_PHYS_64BIT
231 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
233 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
235 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
236 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
237 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
238 | CSPR_MSEL_NAND /* MSEL = NAND */ \
240 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
242 #if defined(CONFIG_TARGET_T1024RDB)
243 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
244 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
245 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
246 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
247 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
248 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
249 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
250 #elif defined(CONFIG_TARGET_T1023RDB)
251 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
252 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
253 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
254 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
255 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
256 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
257 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
260 /* ONFI NAND Flash mode0 Timing Params */
261 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
262 FTIM0_NAND_TWP(0x18) | \
263 FTIM0_NAND_TWCHT(0x07) | \
264 FTIM0_NAND_TWH(0x0a))
265 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
266 FTIM1_NAND_TWBE(0x39) | \
267 FTIM1_NAND_TRR(0x0e) | \
268 FTIM1_NAND_TRP(0x18))
269 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
270 FTIM2_NAND_TREH(0x0a) | \
271 FTIM2_NAND_TWHRE(0x1e))
272 #define CONFIG_SYS_NAND_FTIM3 0x0
274 #define CONFIG_SYS_NAND_DDR_LAW 11
275 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
276 #define CONFIG_SYS_MAX_NAND_DEVICE 1
278 #if defined(CONFIG_MTD_RAW_NAND)
279 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
280 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
281 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
282 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
283 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
284 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
285 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
286 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
287 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
288 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
289 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
290 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
291 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
292 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
293 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
294 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
296 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
297 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
298 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
299 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
300 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
301 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
302 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
303 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
304 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
305 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
306 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
307 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
308 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
309 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
310 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
311 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
314 #ifdef CONFIG_SPL_BUILD
315 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
317 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
320 #if defined(CONFIG_RAMBOOT_PBL)
321 #define CONFIG_SYS_RAMBOOT
324 #define CONFIG_HWCONFIG
326 /* define to use L1 as initial stack */
327 #define CONFIG_L1_INIT_RAM
328 #define CONFIG_SYS_INIT_RAM_LOCK
329 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
330 #ifdef CONFIG_PHYS_64BIT
331 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
333 /* The assembler doesn't like typecast */
334 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
335 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
336 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
338 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
339 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
340 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
342 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
344 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
345 GENERATED_GBL_DATA_SIZE)
346 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
348 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
351 #define CONFIG_SYS_NS16550_SERIAL
352 #define CONFIG_SYS_NS16550_REG_SIZE 1
353 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
355 #define CONFIG_SYS_BAUDRATE_TABLE \
356 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
358 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
359 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
360 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
361 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
365 #define I2C_PCA6408_BUS_NUM 1
366 #define I2C_PCA6408_ADDR 0x20
368 /* I2C bus multiplexer */
369 #define I2C_MUX_CH_DEFAULT 0x8
375 #define CONFIG_RTC_DS1337 1
376 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
379 * eSPI - Enhanced SPI
384 * Memory space is mapped 1-1, but I/O space must start from 0.
386 #define CONFIG_PCIE1 /* PCIE controller 1 */
387 #define CONFIG_PCIE2 /* PCIE controller 2 */
388 #define CONFIG_PCIE3 /* PCIE controller 3 */
391 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
393 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
394 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
395 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
396 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
399 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
401 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
402 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
403 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
404 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
407 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
409 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
410 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
411 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
412 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
415 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
416 #endif /* CONFIG_PCI */
421 #define CONFIG_HAS_FSL_DR_USB
423 #ifdef CONFIG_HAS_FSL_DR_USB
424 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
431 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
435 #ifndef CONFIG_NOBQFMAN
436 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
437 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
441 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
443 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
444 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
445 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
446 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
447 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
448 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
449 CONFIG_SYS_BMAN_CENA_SIZE)
450 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
451 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
452 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
453 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
457 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
459 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
460 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
461 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
462 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
463 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
464 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
465 CONFIG_SYS_QMAN_CENA_SIZE)
466 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
467 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
469 #define CONFIG_SYS_DPAA_FMAN
471 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
472 #endif /* CONFIG_NOBQFMAN */
474 #ifdef CONFIG_SYS_DPAA_FMAN
475 #if defined(CONFIG_TARGET_T1024RDB)
476 #define RGMII_PHY1_ADDR 0x2
477 #define RGMII_PHY2_ADDR 0x6
478 #define SGMII_AQR_PHY_ADDR 0x2
479 #define FM1_10GEC1_PHY_ADDR 0x1
480 #elif defined(CONFIG_TARGET_T1023RDB)
481 #define RGMII_PHY1_ADDR 0x1
482 #define SGMII_RTK_PHY_ADDR 0x3
483 #define SGMII_AQR_PHY_ADDR 0x2
488 * Dynamic MTD Partition support with mtdparts
494 #define CONFIG_LOADS_ECHO /* echo on for serial download */
495 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
498 * Miscellaneous configurable options
502 * For booting Linux, the board info and command line data
503 * have to be in the first 64 MB of memory, since this is
504 * the maximum mapped by the Linux kernel during initialization.
506 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
507 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
510 * Environment Configuration
512 #define CONFIG_ROOTPATH "/opt/nfsroot"
513 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
514 #define __USB_PHY_TYPE utmi
516 #ifdef CONFIG_ARCH_T1024
517 #define ARCH_EXTRA_ENV_SETTINGS \
518 "bank_intlv=cs0_cs1\0" \
519 "ramdiskfile=t1024rdb/ramdisk.uboot\0" \
520 "fdtfile=t1024rdb/t1024rdb.dtb\0"
522 #define ARCH_EXTRA_ENV_SETTINGS \
523 "bank_intlv=null\0" \
524 "ramdiskfile=t1023rdb/ramdisk.uboot\0" \
525 "fdtfile=t1023rdb/t1023rdb.dtb\0"
528 #define CONFIG_EXTRA_ENV_SETTINGS \
529 ARCH_EXTRA_ENV_SETTINGS \
530 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
531 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
532 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
533 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
534 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
536 "tftpflash=tftpboot $loadaddr $uboot && " \
537 "protect off $ubootaddr +$filesize && " \
538 "erase $ubootaddr +$filesize && " \
539 "cp.b $loadaddr $ubootaddr $filesize && " \
540 "protect on $ubootaddr +$filesize && " \
541 "cmp.b $loadaddr $ubootaddr $filesize\0" \
542 "consoledev=ttyS0\0" \
543 "ramdiskaddr=2000000\0" \
544 "fdtaddr=1e00000\0" \
547 #include <asm/fsl_secure_boot.h>
549 #endif /* __T1024RDB_H */