powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040
[platform/kernel/u-boot.git] / include / configs / T102xRDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T1024/T1023 RDB board configuration file
8  */
9
10 #ifndef __T1024RDB_H
11 #define __T1024RDB_H
12
13 /* High Level Configuration Options */
14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
15 #define CONFIG_ENABLE_36BIT_PHYS
16
17 #ifdef CONFIG_PHYS_64BIT
18 #define CONFIG_ADDR_MAP         1
19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
20 #endif
21
22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
24
25 #define CONFIG_ENV_OVERWRITE
26
27 /* support deep sleep */
28 #ifdef CONFIG_ARCH_T1024
29 #define CONFIG_DEEP_SLEEP
30 #endif
31
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_PAD_TO               0x40000
36 #define CONFIG_SPL_MAX_SIZE             0x28000
37 #define RESET_VECTOR_OFFSET             0x27FFC
38 #define BOOT_PAGE_OFFSET                0x27000
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SPL_SKIP_RELOCATE
41 #define CONFIG_SPL_COMMON_INIT_DDR
42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43 #endif
44
45 #ifdef CONFIG_NAND
46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
48 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
50 #if defined(CONFIG_TARGET_T1024RDB)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
52 #elif defined(CONFIG_TARGET_T1023RDB)
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
54 #endif
55 #endif
56
57 #ifdef CONFIG_SPIFLASH
58 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
64 #ifndef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
66 #endif
67 #if defined(CONFIG_TARGET_T1024RDB)
68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
69 #elif defined(CONFIG_TARGET_T1023RDB)
70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
71 #endif
72 #endif
73
74 #ifdef CONFIG_SDCARD
75 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
76 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
77 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
78 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
79 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
80 #ifndef CONFIG_SPL_BUILD
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #endif
83 #if defined(CONFIG_TARGET_T1024RDB)
84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
85 #elif defined(CONFIG_TARGET_T1023RDB)
86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
87 #endif
88 #endif
89
90 #endif /* CONFIG_RAMBOOT_PBL */
91
92 #ifndef CONFIG_RESET_VECTOR_ADDRESS
93 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
94 #endif
95
96 /* PCIe Boot - Master */
97 #define CONFIG_SRIO_PCIE_BOOT_MASTER
98 /*
99  * for slave u-boot IMAGE instored in master memory space,
100  * PHYS must be aligned based on the SIZE
101  */
102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
104 #ifdef CONFIG_PHYS_64BIT
105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
107 #else
108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
110 #endif
111 /*
112  * for slave UCODE and ENV instored in master memory space,
113  * PHYS must be aligned based on the SIZE
114  */
115 #ifdef CONFIG_PHYS_64BIT
116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
118 #else
119 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
121 #endif
122 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
123 /* slave core release by master*/
124 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
125 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
126
127 /* PCIe Boot - Slave */
128 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
129 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
131                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
132 /* Set 1M boot space for PCIe boot */
133 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
135                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
136 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
137 #endif
138
139 #if defined(CONFIG_SPIFLASH)
140 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
141 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
142 #if defined(CONFIG_TARGET_T1024RDB)
143 #define CONFIG_ENV_SECT_SIZE            0x10000
144 #elif defined(CONFIG_TARGET_T1023RDB)
145 #define CONFIG_ENV_SECT_SIZE            0x40000
146 #endif
147 #elif defined(CONFIG_SDCARD)
148 #define CONFIG_SYS_MMC_ENV_DEV          0
149 #define CONFIG_ENV_SIZE                 0x2000
150 #define CONFIG_ENV_OFFSET               (512 * 0x800)
151 #elif defined(CONFIG_NAND)
152 #define CONFIG_ENV_SIZE                 0x2000
153 #if defined(CONFIG_TARGET_T1024RDB)
154 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
155 #elif defined(CONFIG_TARGET_T1023RDB)
156 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
157 #endif
158 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
159 #define CONFIG_ENV_ADDR         0xffe20000
160 #define CONFIG_ENV_SIZE         0x2000
161 #elif defined(CONFIG_ENV_IS_NOWHERE)
162 #define CONFIG_ENV_SIZE         0x2000
163 #else
164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
165 #define CONFIG_ENV_SIZE         0x2000
166 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
167 #endif
168
169 #ifndef __ASSEMBLY__
170 unsigned long get_board_sys_clk(void);
171 unsigned long get_board_ddr_clk(void);
172 #endif
173
174 #define CONFIG_SYS_CLK_FREQ     100000000
175 #define CONFIG_DDR_CLK_FREQ     100000000
176
177 /*
178  * These can be toggled for performance analysis, otherwise use default.
179  */
180 #define CONFIG_SYS_CACHE_STASHING
181 #define CONFIG_BACKSIDE_L2_CACHE
182 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
183 #define CONFIG_BTB                      /* toggle branch predition */
184 #define CONFIG_DDR_ECC
185 #ifdef CONFIG_DDR_ECC
186 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
187 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
188 #endif
189
190 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
191 #define CONFIG_SYS_MEMTEST_END          0x00400000
192
193 /*
194  *  Config the L3 Cache as L3 SRAM
195  */
196 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
197 #define CONFIG_SYS_L3_SIZE              (256 << 10)
198 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
199 #ifdef CONFIG_RAMBOOT_PBL
200 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
201 #endif
202 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
203 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
204 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
205
206 #ifdef CONFIG_PHYS_64BIT
207 #define CONFIG_SYS_DCSRBAR              0xf0000000
208 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
209 #endif
210
211 /* EEPROM */
212 #define CONFIG_ID_EEPROM
213 #define CONFIG_SYS_I2C_EEPROM_NXID
214 #define CONFIG_SYS_EEPROM_BUS_NUM       0
215 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
219
220 /*
221  * DDR Setup
222  */
223 #define CONFIG_VERY_BIG_RAM
224 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
225 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
226 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
227 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
228 #if defined(CONFIG_TARGET_T1024RDB)
229 #define CONFIG_DDR_SPD
230 #define CONFIG_SYS_SPD_BUS_NUM  0
231 #define SPD_EEPROM_ADDRESS      0x51
232 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
233 #elif defined(CONFIG_TARGET_T1023RDB)
234 #define CONFIG_SYS_DDR_RAW_TIMING
235 #define CONFIG_SYS_SDRAM_SIZE   2048
236 #endif
237
238 /*
239  * IFC Definitions
240  */
241 #define CONFIG_SYS_FLASH_BASE   0xe8000000
242 #ifdef CONFIG_PHYS_64BIT
243 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
244 #else
245 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
246 #endif
247
248 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
249 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
250                                 CSPR_PORT_SIZE_16 | \
251                                 CSPR_MSEL_NOR | \
252                                 CSPR_V)
253 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
254
255 /* NOR Flash Timing Params */
256 #if defined(CONFIG_TARGET_T1024RDB)
257 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
258 #elif defined(CONFIG_TARGET_T1023RDB)
259 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
260                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
261 #endif
262 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
263                                 FTIM0_NOR_TEADC(0x5) | \
264                                 FTIM0_NOR_TEAHC(0x5))
265 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
266                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
267                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
268 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
269                                 FTIM2_NOR_TCH(0x4) | \
270                                 FTIM2_NOR_TWPH(0x0E) | \
271                                 FTIM2_NOR_TWP(0x1c))
272 #define CONFIG_SYS_NOR_FTIM3    0x0
273
274 #define CONFIG_SYS_FLASH_QUIET_TEST
275 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
276
277 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
278 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
279 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
280 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
281
282 #define CONFIG_SYS_FLASH_EMPTY_INFO
283 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
284
285 #ifdef CONFIG_TARGET_T1024RDB
286 /* CPLD on IFC */
287 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
288 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
289 #define CONFIG_SYS_CSPR2_EXT            (0xf)
290 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
291                                                 | CSPR_PORT_SIZE_8 \
292                                                 | CSPR_MSEL_GPCM \
293                                                 | CSPR_V)
294 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
295 #define CONFIG_SYS_CSOR2                0x0
296
297 /* CPLD Timing parameters for IFC CS2 */
298 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
299                                                 FTIM0_GPCM_TEADC(0x0e) | \
300                                                 FTIM0_GPCM_TEAHC(0x0e))
301 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
302                                                 FTIM1_GPCM_TRAD(0x1f))
303 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
304                                                 FTIM2_GPCM_TCH(0x8) | \
305                                                 FTIM2_GPCM_TWP(0x1f))
306 #define CONFIG_SYS_CS2_FTIM3            0x0
307 #endif
308
309 /* NAND Flash on IFC */
310 #define CONFIG_NAND_FSL_IFC
311 #define CONFIG_SYS_NAND_BASE            0xff800000
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
314 #else
315 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
316 #endif
317 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
318 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
319                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
320                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
321                                 | CSPR_V)
322 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
323
324 #if defined(CONFIG_TARGET_T1024RDB)
325 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
326                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
327                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
328                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
329                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
330                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
331                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
332 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
333 #elif defined(CONFIG_TARGET_T1023RDB)
334 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
335                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
336                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
337                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
338                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
339                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
340                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
341 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
342 #endif
343
344 #define CONFIG_SYS_NAND_ONFI_DETECTION
345 /* ONFI NAND Flash mode0 Timing Params */
346 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
347                                         FTIM0_NAND_TWP(0x18)   | \
348                                         FTIM0_NAND_TWCHT(0x07) | \
349                                         FTIM0_NAND_TWH(0x0a))
350 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
351                                         FTIM1_NAND_TWBE(0x39)  | \
352                                         FTIM1_NAND_TRR(0x0e)   | \
353                                         FTIM1_NAND_TRP(0x18))
354 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
355                                         FTIM2_NAND_TREH(0x0a) | \
356                                         FTIM2_NAND_TWHRE(0x1e))
357 #define CONFIG_SYS_NAND_FTIM3           0x0
358
359 #define CONFIG_SYS_NAND_DDR_LAW         11
360 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
361 #define CONFIG_SYS_MAX_NAND_DEVICE      1
362
363 #if defined(CONFIG_NAND)
364 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
365 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
366 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
367 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
368 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
369 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
370 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
371 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
372 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
373 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
374 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
380 #else
381 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
382 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
383 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
384 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
385 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
386 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
387 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
388 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
389 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
390 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
391 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
392 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
393 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
394 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
395 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
396 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
397 #endif
398
399 #ifdef CONFIG_SPL_BUILD
400 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
401 #else
402 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
403 #endif
404
405 #if defined(CONFIG_RAMBOOT_PBL)
406 #define CONFIG_SYS_RAMBOOT
407 #endif
408
409 #define CONFIG_HWCONFIG
410
411 /* define to use L1 as initial stack */
412 #define CONFIG_L1_INIT_RAM
413 #define CONFIG_SYS_INIT_RAM_LOCK
414 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
415 #ifdef CONFIG_PHYS_64BIT
416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
418 /* The assembler doesn't like typecast */
419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
420         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
421           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
422 #else
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
426 #endif
427 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
428
429 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
430                                         GENERATED_GBL_DATA_SIZE)
431 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
432
433 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
434 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
435
436 /* Serial Port */
437 #define CONFIG_SYS_NS16550_SERIAL
438 #define CONFIG_SYS_NS16550_REG_SIZE     1
439 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
440
441 #define CONFIG_SYS_BAUDRATE_TABLE       \
442         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
443
444 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
445 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
446 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
447 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
448
449 /* Video */
450 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
451 #ifdef CONFIG_FSL_DIU_FB
452 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
453 #define CONFIG_VIDEO_LOGO
454 #define CONFIG_VIDEO_BMP_LOGO
455 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
456 /*
457  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
458  * disable empty flash sector detection, which is I/O-intensive.
459  */
460 #undef CONFIG_SYS_FLASH_EMPTY_INFO
461 #endif
462
463 /* I2C */
464 #define CONFIG_SYS_I2C
465 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
466 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
467 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
468 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
469 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
470 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
471 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
472
473 #define I2C_PCA6408_BUS_NUM             1
474 #define I2C_PCA6408_ADDR                0x20
475
476 /* I2C bus multiplexer */
477 #define I2C_MUX_CH_DEFAULT      0x8
478
479 /*
480  * RTC configuration
481  */
482 #define RTC
483 #define CONFIG_RTC_DS1337       1
484 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
485
486 /*
487  * eSPI - Enhanced SPI
488  */
489
490 /*
491  * General PCIe
492  * Memory space is mapped 1-1, but I/O space must start from 0.
493  */
494 #define CONFIG_PCIE1            /* PCIE controller 1 */
495 #define CONFIG_PCIE2            /* PCIE controller 2 */
496 #define CONFIG_PCIE3            /* PCIE controller 3 */
497 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
498 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
499 #define CONFIG_PCI_INDIRECT_BRIDGE
500
501 #ifdef CONFIG_PCI
502 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
503 #ifdef CONFIG_PCIE1
504 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
505 #ifdef CONFIG_PHYS_64BIT
506 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
507 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
508 #else
509 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
510 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
511 #endif
512 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
513 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
514 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
515 #ifdef CONFIG_PHYS_64BIT
516 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
517 #else
518 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
519 #endif
520 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
521 #endif
522
523 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
524 #ifdef CONFIG_PCIE2
525 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
526 #ifdef CONFIG_PHYS_64BIT
527 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
528 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
529 #else
530 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
531 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
532 #endif
533 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
534 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
535 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
536 #ifdef CONFIG_PHYS_64BIT
537 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
538 #else
539 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
540 #endif
541 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
542 #endif
543
544 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
545 #ifdef CONFIG_PCIE3
546 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
547 #ifdef CONFIG_PHYS_64BIT
548 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
549 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
550 #else
551 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
552 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
553 #endif
554 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
555 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
556 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
557 #ifdef CONFIG_PHYS_64BIT
558 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
559 #else
560 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
561 #endif
562 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
563 #endif
564
565 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
566 #endif  /* CONFIG_PCI */
567
568 /*
569  * USB
570  */
571 #define CONFIG_HAS_FSL_DR_USB
572
573 #ifdef CONFIG_HAS_FSL_DR_USB
574 #define CONFIG_USB_EHCI_FSL
575 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
576 #endif
577
578 /*
579  * SDHC
580  */
581 #ifdef CONFIG_MMC
582 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
583 #endif
584
585 /* Qman/Bman */
586 #ifndef CONFIG_NOBQFMAN
587 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
588 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
589 #ifdef CONFIG_PHYS_64BIT
590 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
591 #else
592 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
593 #endif
594 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
595 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
596 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
597 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
598 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
599 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
600                                         CONFIG_SYS_BMAN_CENA_SIZE)
601 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
602 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
603 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
604 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
605 #ifdef CONFIG_PHYS_64BIT
606 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
607 #else
608 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
609 #endif
610 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
611 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
612 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
613 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
614 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
615 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
616                                         CONFIG_SYS_QMAN_CENA_SIZE)
617 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
618 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
619
620 #define CONFIG_SYS_DPAA_FMAN
621
622 /* Default address of microcode for the Linux FMan driver */
623 #if defined(CONFIG_SPIFLASH)
624 /*
625  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
626  * env, so we got 0x110000.
627  */
628 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
629 #define CONFIG_SYS_QE_FW_ADDR   0x130000
630 #elif defined(CONFIG_SDCARD)
631 /*
632  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
633  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
634  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
635  */
636 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
637 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
638 #elif defined(CONFIG_NAND)
639 #if defined(CONFIG_TARGET_T1024RDB)
640 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
641 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
642 #elif defined(CONFIG_TARGET_T1023RDB)
643 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
644 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
645 #endif
646 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
647 /*
648  * Slave has no ucode locally, it can fetch this from remote. When implementing
649  * in two corenet boards, slave's ucode could be stored in master's memory
650  * space, the address can be mapped from slave TLB->slave LAW->
651  * slave SRIO or PCIE outbound window->master inbound window->
652  * master LAW->the ucode address in master's memory space.
653  */
654 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
655 #else
656 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
657 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
658 #endif
659 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
660 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
661 #endif /* CONFIG_NOBQFMAN */
662
663 #ifdef CONFIG_SYS_DPAA_FMAN
664 #define CONFIG_PHY_REALTEK
665 #if defined(CONFIG_TARGET_T1024RDB)
666 #define RGMII_PHY1_ADDR         0x2
667 #define RGMII_PHY2_ADDR         0x6
668 #define SGMII_AQR_PHY_ADDR      0x2
669 #define FM1_10GEC1_PHY_ADDR     0x1
670 #elif defined(CONFIG_TARGET_T1023RDB)
671 #define RGMII_PHY1_ADDR         0x1
672 #define SGMII_RTK_PHY_ADDR      0x3
673 #define SGMII_AQR_PHY_ADDR      0x2
674 #endif
675 #endif
676
677 #ifdef CONFIG_FMAN_ENET
678 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
679 #endif
680
681 /*
682  * Dynamic MTD Partition support with mtdparts
683  */
684
685 /*
686  * Environment
687  */
688 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
689 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
690
691 /*
692  * Miscellaneous configurable options
693  */
694 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
695
696 /*
697  * For booting Linux, the board info and command line data
698  * have to be in the first 64 MB of memory, since this is
699  * the maximum mapped by the Linux kernel during initialization.
700  */
701 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
702 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
703
704 #ifdef CONFIG_CMD_KGDB
705 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
706 #endif
707
708 /*
709  * Environment Configuration
710  */
711 #define CONFIG_ROOTPATH         "/opt/nfsroot"
712 #define CONFIG_BOOTFILE         "uImage"
713 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
714 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
715 #define __USB_PHY_TYPE          utmi
716
717 #ifdef CONFIG_ARCH_T1024
718 #define CONFIG_BOARDNAME t1024rdb
719 #define BANK_INTLV cs0_cs1
720 #else
721 #define CONFIG_BOARDNAME t1023rdb
722 #define BANK_INTLV  null
723 #endif
724
725 #define CONFIG_EXTRA_ENV_SETTINGS                               \
726         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
727         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
728         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
729         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
730         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
731         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
732         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
733         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
734         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
735         "netdev=eth0\0"                                         \
736         "tftpflash=tftpboot $loadaddr $uboot && "               \
737         "protect off $ubootaddr +$filesize && "                 \
738         "erase $ubootaddr +$filesize && "                       \
739         "cp.b $loadaddr $ubootaddr $filesize && "               \
740         "protect on $ubootaddr +$filesize && "                  \
741         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
742         "consoledev=ttyS0\0"                                    \
743         "ramdiskaddr=2000000\0"                                 \
744         "fdtaddr=1e00000\0"                                     \
745         "bdev=sda3\0"
746
747 #define CONFIG_LINUX                                    \
748         "setenv bootargs root=/dev/ram rw "             \
749         "console=$consoledev,$baudrate $othbootargs;"   \
750         "setenv ramdiskaddr 0x02000000;"                \
751         "setenv fdtaddr 0x00c00000;"                    \
752         "setenv loadaddr 0x1000000;"                    \
753         "bootm $loadaddr $ramdiskaddr $fdtaddr"
754
755 #define CONFIG_NFSBOOTCOMMAND                   \
756         "setenv bootargs root=/dev/nfs rw "     \
757         "nfsroot=$serverip:$rootpath "          \
758         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
759         "console=$consoledev,$baudrate $othbootargs;"   \
760         "tftp $loadaddr $bootfile;"             \
761         "tftp $fdtaddr $fdtfile;"               \
762         "bootm $loadaddr - $fdtaddr"
763
764 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
765
766 #include <asm/fsl_secure_boot.h>
767
768 #endif  /* __T1024RDB_H */