include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17
  18 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #define RESET_VECTOR_OFFSET             0x27FFC
  22 #define BOOT_PAGE_OFFSET                0x27000
  23
  24 #ifdef CONFIG_MTD_RAW_NAND
  25 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  26 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  27 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  28 #endif
  29
  30 #ifdef CONFIG_SPIFLASH
  31 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  36 #endif
  37
  38 #ifdef CONFIG_SDCARD
  39 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  40 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  41 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  42 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  43 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  44 #endif
  45
  46 #endif /* CONFIG_RAMBOOT_PBL */
  47
  48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  50 #endif
  51
  52 /* PCIe Boot - Master */
  53 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  54 /*
  55  * for slave u-boot IMAGE instored in master memory space,
  56  * PHYS must be aligned based on the SIZE
  57  */
  58 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  59 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  60 #ifdef CONFIG_PHYS_64BIT
  61 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  62 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  63 #else
  64 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  65 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  66 #endif
  67 /*
  68  * for slave UCODE and ENV instored in master memory space,
  69  * PHYS must be aligned based on the SIZE
  70  */
  71 #ifdef CONFIG_PHYS_64BIT
  72 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  73 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  74 #else
  75 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  76 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  77 #endif
  78 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
  79 /* slave core release by master*/
  80 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
  81 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
  82
  83 /* PCIe Boot - Slave */
  84 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  85 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  86 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  87                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  88 /* Set 1M boot space for PCIe boot */
  89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
  91                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  93 #endif
  94
  95 /*
  96  * These can be toggled for performance analysis, otherwise use default.
  97  */
  98 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  99 #ifdef CONFIG_DDR_ECC
 100 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 101 #endif
 102
 103 /*
 104  *  Config the L3 Cache as L3 SRAM
 105  */
 106 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 107 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 108 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 109
 110 #ifdef CONFIG_PHYS_64BIT
 111 #define CONFIG_SYS_DCSRBAR              0xf0000000
 112 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 113 #endif
 114
 115 /* EEPROM */
 116 #define CONFIG_SYS_I2C_EEPROM_NXID
 117 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 118
 119 /*
 120  * DDR Setup
 121  */
 122 #define CONFIG_VERY_BIG_RAM
 123 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 124 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 125 #if defined(CONFIG_TARGET_T1024RDB)
 126 #define SPD_EEPROM_ADDRESS      0x51
 127 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 128 #elif defined(CONFIG_TARGET_T1023RDB)
 129 #define CONFIG_SYS_SDRAM_SIZE   2048
 130 #endif
 131
 132 /*
 133  * IFC Definitions
 134  */
 135 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 136 #ifdef CONFIG_PHYS_64BIT
 137 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 138 #else
 139 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 140 #endif
 141
 142 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 143 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 144                                 CSPR_PORT_SIZE_16 | \
 145                                 CSPR_MSEL_NOR | \
 146                                 CSPR_V)
 147 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 148
 149 /* NOR Flash Timing Params */
 150 #if defined(CONFIG_TARGET_T1024RDB)
 151 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 152 #elif defined(CONFIG_TARGET_T1023RDB)
 153 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 154                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 155 #endif
 156 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 157                                 FTIM0_NOR_TEADC(0x5) | \
 158                                 FTIM0_NOR_TEAHC(0x5))
 159 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 160                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 161                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 162 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 163                                 FTIM2_NOR_TCH(0x4) | \
 164                                 FTIM2_NOR_TWPH(0x0E) | \
 165                                 FTIM2_NOR_TWP(0x1c))
 166 #define CONFIG_SYS_NOR_FTIM3    0x0
 167
 168 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 169
 170 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 171
 172 #ifdef CONFIG_TARGET_T1024RDB
 173 /* CPLD on IFC */
 174 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 175 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 176 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 177 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 178                                                 | CSPR_PORT_SIZE_8 \
 179                                                 | CSPR_MSEL_GPCM \
 180                                                 | CSPR_V)
 181 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 182 #define CONFIG_SYS_CSOR2                0x0
 183
 184 /* CPLD Timing parameters for IFC CS2 */
 185 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 186                                                 FTIM0_GPCM_TEADC(0x0e) | \
 187                                                 FTIM0_GPCM_TEAHC(0x0e))
 188 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 189                                                 FTIM1_GPCM_TRAD(0x1f))
 190 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 191                                                 FTIM2_GPCM_TCH(0x8) | \
 192                                                 FTIM2_GPCM_TWP(0x1f))
 193 #define CONFIG_SYS_CS2_FTIM3            0x0
 194 #endif
 195
 196 /* NAND Flash on IFC */
 197 #define CONFIG_SYS_NAND_BASE            0xff800000
 198 #ifdef CONFIG_PHYS_64BIT
 199 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 200 #else
 201 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 202 #endif
 203 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 204 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 205                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 206                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 207                                 | CSPR_V)
 208 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 209
 210 #if defined(CONFIG_TARGET_T1024RDB)
 211 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 212                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 213                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 214                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 215                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 216                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 217                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 218 #elif defined(CONFIG_TARGET_T1023RDB)
 219 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 220                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 221                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 222                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 223                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 224                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 225                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 226 #endif
 227
 228 /* ONFI NAND Flash mode0 Timing Params */
 229 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 230                                         FTIM0_NAND_TWP(0x18)   | \
 231                                         FTIM0_NAND_TWCHT(0x07) | \
 232                                         FTIM0_NAND_TWH(0x0a))
 233 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 234                                         FTIM1_NAND_TWBE(0x39)  | \
 235                                         FTIM1_NAND_TRR(0x0e)   | \
 236                                         FTIM1_NAND_TRP(0x18))
 237 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 238                                         FTIM2_NAND_TREH(0x0a) | \
 239                                         FTIM2_NAND_TWHRE(0x1e))
 240 #define CONFIG_SYS_NAND_FTIM3           0x0
 241
 242 #define CONFIG_SYS_NAND_DDR_LAW         11
 243 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 244 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 245
 246 #if defined(CONFIG_MTD_RAW_NAND)
 247 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 248 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 249 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 250 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 251 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 252 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 253 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 254 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 255 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 256 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 257 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 258 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 259 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 260 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 261 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 262 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 263 #else
 264 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 265 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 266 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 273 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 274 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 275 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 276 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 277 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 278 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 279 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 280 #endif
 281
 282 #define CONFIG_HWCONFIG
 283
 284 /* define to use L1 as initial stack */
 285 #define CONFIG_L1_INIT_RAM
 286 #define CONFIG_SYS_INIT_RAM_LOCK
 287 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 288 #ifdef CONFIG_PHYS_64BIT
 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 291 /* The assembler doesn't like typecast */
 292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 293         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 294           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 295 #else
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 299 #endif
 300 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 301
 302 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 303
 304 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 305
 306 /* Serial Port */
 307 #define CONFIG_SYS_NS16550_SERIAL
 308 #define CONFIG_SYS_NS16550_REG_SIZE     1
 309 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 310
 311 #define CONFIG_SYS_BAUDRATE_TABLE       \
 312         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 313
 314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 316 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 317 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 318
 319 /* I2C */
 320
 321 #define I2C_PCA6408_BUS_NUM             1
 322 #define I2C_PCA6408_ADDR                0x20
 323
 324 /* I2C bus multiplexer */
 325 #define I2C_MUX_CH_DEFAULT      0x8
 326
 327 /*
 328  * RTC configuration
 329  */
 330 #define RTC
 331 #define CONFIG_RTC_DS1337       1
 332 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 333
 334 /*
 335  * eSPI - Enhanced SPI
 336  */
 337
 338 /*
 339  * General PCIe
 340  * Memory space is mapped 1-1, but I/O space must start from 0.
 341  */
 342
 343 #ifdef CONFIG_PCI
 344 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 345 #ifdef CONFIG_PCIE1
 346 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 347 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 348 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 349 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 350 #endif
 351
 352 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 353 #ifdef CONFIG_PCIE2
 354 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 355 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 356 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 357 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 358 #endif
 359
 360 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 361 #ifdef CONFIG_PCIE3
 362 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 363 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 364 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 365 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 366 #endif
 367 #endif  /* CONFIG_PCI */
 368
 369 /*
 370  * USB
 371  */
 372
 373 /*
 374  * SDHC
 375  */
 376 #ifdef CONFIG_MMC
 377 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 378 #endif
 379
 380 /* Qman/Bman */
 381 #ifndef CONFIG_NOBQFMAN
 382 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 383 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 384 #ifdef CONFIG_PHYS_64BIT
 385 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 386 #else
 387 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 388 #endif
 389 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 390 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 391 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 392 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 393 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 394 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 395                                         CONFIG_SYS_BMAN_CENA_SIZE)
 396 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 397 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 398 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 399 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 400 #ifdef CONFIG_PHYS_64BIT
 401 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 402 #else
 403 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 404 #endif
 405 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 406 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 407 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 408 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 409 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 410 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 411                                         CONFIG_SYS_QMAN_CENA_SIZE)
 412 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 413 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 414
 415 #define CONFIG_SYS_DPAA_FMAN
 416
 417 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 418 #endif /* CONFIG_NOBQFMAN */
 419
 420 #ifdef CONFIG_SYS_DPAA_FMAN
 421 #if defined(CONFIG_TARGET_T1024RDB)
 422 #define RGMII_PHY1_ADDR         0x2
 423 #define RGMII_PHY2_ADDR         0x6
 424 #define SGMII_AQR_PHY_ADDR      0x2
 425 #define FM1_10GEC1_PHY_ADDR     0x1
 426 #elif defined(CONFIG_TARGET_T1023RDB)
 427 #define RGMII_PHY1_ADDR         0x1
 428 #define SGMII_RTK_PHY_ADDR      0x3
 429 #define SGMII_AQR_PHY_ADDR      0x2
 430 #endif
 431 #endif
 432
 433 /*
 434  * Dynamic MTD Partition support with mtdparts
 435  */
 436
 437 /*
 438  * Environment
 439  */
 440 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 441 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 442
 443 /*
 444  * Miscellaneous configurable options
 445  */
 446
 447 /*
 448  * For booting Linux, the board info and command line data
 449  * have to be in the first 64 MB of memory, since this is
 450  * the maximum mapped by the Linux kernel during initialization.
 451  */
 452 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 453
 454 /*
 455  * Environment Configuration
 456  */
 457 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 458 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 459 #define __USB_PHY_TYPE          utmi
 460
 461 #ifdef CONFIG_ARCH_T1024
 462 #define ARCH_EXTRA_ENV_SETTINGS \
 463         "bank_intlv=cs0_cs1\0"                  \
 464         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 465         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 466 #else
 467 #define ARCH_EXTRA_ENV_SETTINGS \
 468         "bank_intlv=null\0"                     \
 469         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 470         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 471 #endif
 472
 473 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 474         ARCH_EXTRA_ENV_SETTINGS                                 \
 475         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 476         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 477         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 478         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 479         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 480         "netdev=eth0\0"                                         \
 481         "tftpflash=tftpboot $loadaddr $uboot && "               \
 482         "protect off $ubootaddr +$filesize && "                 \
 483         "erase $ubootaddr +$filesize && "                       \
 484         "cp.b $loadaddr $ubootaddr $filesize && "               \
 485         "protect on $ubootaddr +$filesize && "                  \
 486         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 487         "consoledev=ttyS0\0"                                    \
 488         "ramdiskaddr=2000000\0"                                 \
 489         "fdtaddr=1e00000\0"                                     \
 490         "bdev=sda3\0"
 491
 492 #include <asm/fsl_secure_boot.h>
 493
 494 #endif  /* __T1024RDB_H */