Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / T102xRDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T1024/T1023 RDB board configuration file
8  */
9
10 #ifndef __T1024RDB_H
11 #define __T1024RDB_H
12
13 /* High Level Configuration Options */
14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
15 #define CONFIG_ENABLE_36BIT_PHYS
16
17 #ifdef CONFIG_PHYS_64BIT
18 #define CONFIG_ADDR_MAP         1
19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
20 #endif
21
22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
24
25 #define CONFIG_ENV_OVERWRITE
26
27 /* support deep sleep */
28 #ifdef CONFIG_ARCH_T1024
29 #define CONFIG_DEEP_SLEEP
30 #endif
31
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_PAD_TO               0x40000
36 #define CONFIG_SPL_MAX_SIZE             0x28000
37 #define RESET_VECTOR_OFFSET             0x27FFC
38 #define BOOT_PAGE_OFFSET                0x27000
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SPL_SKIP_RELOCATE
41 #define CONFIG_SPL_COMMON_INIT_DDR
42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43 #endif
44
45 #ifdef CONFIG_NAND
46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
48 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
50 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
51 #if defined(CONFIG_TARGET_T1024RDB)
52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
53 #elif defined(CONFIG_TARGET_T1023RDB)
54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
55 #endif
56 #define CONFIG_SPL_NAND_BOOT
57 #endif
58
59 #ifdef CONFIG_SPIFLASH
60 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
61 #define CONFIG_SPL_SPI_FLASH_MINIMAL
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
66 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
67 #ifndef CONFIG_SPL_BUILD
68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
69 #endif
70 #if defined(CONFIG_TARGET_T1024RDB)
71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
72 #elif defined(CONFIG_TARGET_T1023RDB)
73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
74 #endif
75 #define CONFIG_SPL_SPI_BOOT
76 #endif
77
78 #ifdef CONFIG_SDCARD
79 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
80 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
81 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
82 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
83 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
84 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
85 #ifndef CONFIG_SPL_BUILD
86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
87 #endif
88 #if defined(CONFIG_TARGET_T1024RDB)
89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
90 #elif defined(CONFIG_TARGET_T1023RDB)
91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
92 #endif
93 #define CONFIG_SPL_MMC_BOOT
94 #endif
95
96 #endif /* CONFIG_RAMBOOT_PBL */
97
98 #ifndef CONFIG_RESET_VECTOR_ADDRESS
99 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
100 #endif
101
102 /* PCIe Boot - Master */
103 #define CONFIG_SRIO_PCIE_BOOT_MASTER
104 /*
105  * for slave u-boot IMAGE instored in master memory space,
106  * PHYS must be aligned based on the SIZE
107  */
108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
110 #ifdef CONFIG_PHYS_64BIT
111 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
113 #else
114 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
116 #endif
117 /*
118  * for slave UCODE and ENV instored in master memory space,
119  * PHYS must be aligned based on the SIZE
120  */
121 #ifdef CONFIG_PHYS_64BIT
122 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
124 #else
125 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
127 #endif
128 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
129 /* slave core release by master*/
130 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
131 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
132
133 /* PCIe Boot - Slave */
134 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
135 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
137                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
138 /* Set 1M boot space for PCIe boot */
139 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
141                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
142 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
143 #endif
144
145 #if defined(CONFIG_SPIFLASH)
146 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
147 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
148 #if defined(CONFIG_TARGET_T1024RDB)
149 #define CONFIG_ENV_SECT_SIZE            0x10000
150 #elif defined(CONFIG_TARGET_T1023RDB)
151 #define CONFIG_ENV_SECT_SIZE            0x40000
152 #endif
153 #elif defined(CONFIG_SDCARD)
154 #define CONFIG_SYS_MMC_ENV_DEV          0
155 #define CONFIG_ENV_SIZE                 0x2000
156 #define CONFIG_ENV_OFFSET               (512 * 0x800)
157 #elif defined(CONFIG_NAND)
158 #define CONFIG_ENV_SIZE                 0x2000
159 #if defined(CONFIG_TARGET_T1024RDB)
160 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
161 #elif defined(CONFIG_TARGET_T1023RDB)
162 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
163 #endif
164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
165 #define CONFIG_ENV_ADDR         0xffe20000
166 #define CONFIG_ENV_SIZE         0x2000
167 #elif defined(CONFIG_ENV_IS_NOWHERE)
168 #define CONFIG_ENV_SIZE         0x2000
169 #else
170 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
171 #define CONFIG_ENV_SIZE         0x2000
172 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
173 #endif
174
175 #ifndef __ASSEMBLY__
176 unsigned long get_board_sys_clk(void);
177 unsigned long get_board_ddr_clk(void);
178 #endif
179
180 #define CONFIG_SYS_CLK_FREQ     100000000
181 #define CONFIG_DDR_CLK_FREQ     100000000
182
183 /*
184  * These can be toggled for performance analysis, otherwise use default.
185  */
186 #define CONFIG_SYS_CACHE_STASHING
187 #define CONFIG_BACKSIDE_L2_CACHE
188 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
189 #define CONFIG_BTB                      /* toggle branch predition */
190 #define CONFIG_DDR_ECC
191 #ifdef CONFIG_DDR_ECC
192 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
193 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
194 #endif
195
196 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
197 #define CONFIG_SYS_MEMTEST_END          0x00400000
198
199 /*
200  *  Config the L3 Cache as L3 SRAM
201  */
202 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
203 #define CONFIG_SYS_L3_SIZE              (256 << 10)
204 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
205 #ifdef CONFIG_RAMBOOT_PBL
206 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
207 #endif
208 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
209 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
210 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
211
212 #ifdef CONFIG_PHYS_64BIT
213 #define CONFIG_SYS_DCSRBAR              0xf0000000
214 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
215 #endif
216
217 /* EEPROM */
218 #define CONFIG_ID_EEPROM
219 #define CONFIG_SYS_I2C_EEPROM_NXID
220 #define CONFIG_SYS_EEPROM_BUS_NUM       0
221 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
225
226 /*
227  * DDR Setup
228  */
229 #define CONFIG_VERY_BIG_RAM
230 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
231 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
232 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
233 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
234 #if defined(CONFIG_TARGET_T1024RDB)
235 #define CONFIG_DDR_SPD
236 #define CONFIG_SYS_SPD_BUS_NUM  0
237 #define SPD_EEPROM_ADDRESS      0x51
238 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
239 #elif defined(CONFIG_TARGET_T1023RDB)
240 #define CONFIG_SYS_DDR_RAW_TIMING
241 #define CONFIG_SYS_SDRAM_SIZE   2048
242 #endif
243
244 /*
245  * IFC Definitions
246  */
247 #define CONFIG_SYS_FLASH_BASE   0xe8000000
248 #ifdef CONFIG_PHYS_64BIT
249 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
250 #else
251 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
252 #endif
253
254 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
255 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
256                                 CSPR_PORT_SIZE_16 | \
257                                 CSPR_MSEL_NOR | \
258                                 CSPR_V)
259 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
260
261 /* NOR Flash Timing Params */
262 #if defined(CONFIG_TARGET_T1024RDB)
263 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
264 #elif defined(CONFIG_TARGET_T1023RDB)
265 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
266                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
267 #endif
268 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
269                                 FTIM0_NOR_TEADC(0x5) | \
270                                 FTIM0_NOR_TEAHC(0x5))
271 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
272                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
273                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
274 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
275                                 FTIM2_NOR_TCH(0x4) | \
276                                 FTIM2_NOR_TWPH(0x0E) | \
277                                 FTIM2_NOR_TWP(0x1c))
278 #define CONFIG_SYS_NOR_FTIM3    0x0
279
280 #define CONFIG_SYS_FLASH_QUIET_TEST
281 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
282
283 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
284 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
285 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
286 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
287
288 #define CONFIG_SYS_FLASH_EMPTY_INFO
289 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
290
291 #ifdef CONFIG_TARGET_T1024RDB
292 /* CPLD on IFC */
293 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
294 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
295 #define CONFIG_SYS_CSPR2_EXT            (0xf)
296 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
297                                                 | CSPR_PORT_SIZE_8 \
298                                                 | CSPR_MSEL_GPCM \
299                                                 | CSPR_V)
300 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
301 #define CONFIG_SYS_CSOR2                0x0
302
303 /* CPLD Timing parameters for IFC CS2 */
304 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
305                                                 FTIM0_GPCM_TEADC(0x0e) | \
306                                                 FTIM0_GPCM_TEAHC(0x0e))
307 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
308                                                 FTIM1_GPCM_TRAD(0x1f))
309 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
310                                                 FTIM2_GPCM_TCH(0x8) | \
311                                                 FTIM2_GPCM_TWP(0x1f))
312 #define CONFIG_SYS_CS2_FTIM3            0x0
313 #endif
314
315 /* NAND Flash on IFC */
316 #define CONFIG_NAND_FSL_IFC
317 #define CONFIG_SYS_NAND_BASE            0xff800000
318 #ifdef CONFIG_PHYS_64BIT
319 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
320 #else
321 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
322 #endif
323 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
324 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
325                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
326                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
327                                 | CSPR_V)
328 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
329
330 #if defined(CONFIG_TARGET_T1024RDB)
331 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
332                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
333                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
334                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
335                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
336                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
337                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
338 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
339 #elif defined(CONFIG_TARGET_T1023RDB)
340 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
341                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
342                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
343                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
344                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
345                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
346                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
347 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
348 #endif
349
350 #define CONFIG_SYS_NAND_ONFI_DETECTION
351 /* ONFI NAND Flash mode0 Timing Params */
352 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
353                                         FTIM0_NAND_TWP(0x18)   | \
354                                         FTIM0_NAND_TWCHT(0x07) | \
355                                         FTIM0_NAND_TWH(0x0a))
356 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
357                                         FTIM1_NAND_TWBE(0x39)  | \
358                                         FTIM1_NAND_TRR(0x0e)   | \
359                                         FTIM1_NAND_TRP(0x18))
360 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
361                                         FTIM2_NAND_TREH(0x0a) | \
362                                         FTIM2_NAND_TWHRE(0x1e))
363 #define CONFIG_SYS_NAND_FTIM3           0x0
364
365 #define CONFIG_SYS_NAND_DDR_LAW         11
366 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
367 #define CONFIG_SYS_MAX_NAND_DEVICE      1
368
369 #if defined(CONFIG_NAND)
370 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
371 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
372 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
373 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
374 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
375 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
376 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
377 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
378 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
379 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
380 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
381 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
382 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
383 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
384 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
385 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
386 #else
387 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
388 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
389 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
390 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
391 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
392 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
393 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
394 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
395 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
396 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
397 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
398 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
399 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
400 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
401 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
402 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
403 #endif
404
405 #ifdef CONFIG_SPL_BUILD
406 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
407 #else
408 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
409 #endif
410
411 #if defined(CONFIG_RAMBOOT_PBL)
412 #define CONFIG_SYS_RAMBOOT
413 #endif
414
415 #define CONFIG_HWCONFIG
416
417 /* define to use L1 as initial stack */
418 #define CONFIG_L1_INIT_RAM
419 #define CONFIG_SYS_INIT_RAM_LOCK
420 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
421 #ifdef CONFIG_PHYS_64BIT
422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
424 /* The assembler doesn't like typecast */
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
426         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
427           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
428 #else
429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
432 #endif
433 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
434
435 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
436                                         GENERATED_GBL_DATA_SIZE)
437 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
438
439 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
440 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
441
442 /* Serial Port */
443 #define CONFIG_SYS_NS16550_SERIAL
444 #define CONFIG_SYS_NS16550_REG_SIZE     1
445 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
446
447 #define CONFIG_SYS_BAUDRATE_TABLE       \
448         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
449
450 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
451 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
452 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
453 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
454
455 /* Video */
456 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
457 #ifdef CONFIG_FSL_DIU_FB
458 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
459 #define CONFIG_VIDEO_LOGO
460 #define CONFIG_VIDEO_BMP_LOGO
461 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
462 /*
463  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
464  * disable empty flash sector detection, which is I/O-intensive.
465  */
466 #undef CONFIG_SYS_FLASH_EMPTY_INFO
467 #endif
468
469 /* I2C */
470 #define CONFIG_SYS_I2C
471 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
472 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
473 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
474 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
475 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
476 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
477 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
478
479 #define I2C_PCA6408_BUS_NUM             1
480 #define I2C_PCA6408_ADDR                0x20
481
482 /* I2C bus multiplexer */
483 #define I2C_MUX_CH_DEFAULT      0x8
484
485 /*
486  * RTC configuration
487  */
488 #define RTC
489 #define CONFIG_RTC_DS1337       1
490 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
491
492 /*
493  * eSPI - Enhanced SPI
494  */
495
496 /*
497  * General PCIe
498  * Memory space is mapped 1-1, but I/O space must start from 0.
499  */
500 #define CONFIG_PCIE1            /* PCIE controller 1 */
501 #define CONFIG_PCIE2            /* PCIE controller 2 */
502 #define CONFIG_PCIE3            /* PCIE controller 3 */
503 #ifdef CONFIG_ARCH_T1040
504 #define CONFIG_PCIE4            /* PCIE controller 4 */
505 #endif
506 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
507 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
508 #define CONFIG_PCI_INDIRECT_BRIDGE
509
510 #ifdef CONFIG_PCI
511 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
512 #ifdef CONFIG_PCIE1
513 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
514 #ifdef CONFIG_PHYS_64BIT
515 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
516 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
517 #else
518 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
519 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
520 #endif
521 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
522 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
523 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
524 #ifdef CONFIG_PHYS_64BIT
525 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
526 #else
527 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
528 #endif
529 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
530 #endif
531
532 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
533 #ifdef CONFIG_PCIE2
534 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
535 #ifdef CONFIG_PHYS_64BIT
536 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
537 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
538 #else
539 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
540 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
541 #endif
542 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
543 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
544 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
545 #ifdef CONFIG_PHYS_64BIT
546 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
547 #else
548 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
549 #endif
550 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
551 #endif
552
553 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
554 #ifdef CONFIG_PCIE3
555 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
556 #ifdef CONFIG_PHYS_64BIT
557 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
558 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
559 #else
560 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
561 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
562 #endif
563 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
564 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
565 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
566 #ifdef CONFIG_PHYS_64BIT
567 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
568 #else
569 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
570 #endif
571 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
572 #endif
573
574 /* controller 4, Base address 203000, to be removed */
575 #ifdef CONFIG_PCIE4
576 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
577 #ifdef CONFIG_PHYS_64BIT
578 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
579 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
580 #else
581 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
582 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
583 #endif
584 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
585 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
586 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
587 #ifdef CONFIG_PHYS_64BIT
588 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
589 #else
590 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
591 #endif
592 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
593 #endif
594
595 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
596 #endif  /* CONFIG_PCI */
597
598 /*
599  * USB
600  */
601 #define CONFIG_HAS_FSL_DR_USB
602
603 #ifdef CONFIG_HAS_FSL_DR_USB
604 #define CONFIG_USB_EHCI_FSL
605 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
606 #endif
607
608 /*
609  * SDHC
610  */
611 #ifdef CONFIG_MMC
612 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
613 #endif
614
615 /* Qman/Bman */
616 #ifndef CONFIG_NOBQFMAN
617 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
618 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
619 #ifdef CONFIG_PHYS_64BIT
620 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
621 #else
622 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
623 #endif
624 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
625 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
626 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
627 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
628 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
629 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
630                                         CONFIG_SYS_BMAN_CENA_SIZE)
631 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
632 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
633 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
634 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
635 #ifdef CONFIG_PHYS_64BIT
636 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
637 #else
638 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
639 #endif
640 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
641 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
642 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
643 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
644 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
645 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
646                                         CONFIG_SYS_QMAN_CENA_SIZE)
647 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
648 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
649
650 #define CONFIG_SYS_DPAA_FMAN
651
652 #ifdef CONFIG_TARGET_T1024RDB
653 #define CONFIG_QE
654 #endif
655 /* Default address of microcode for the Linux FMan driver */
656 #if defined(CONFIG_SPIFLASH)
657 /*
658  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
659  * env, so we got 0x110000.
660  */
661 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
662 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
663 #define CONFIG_SYS_QE_FW_ADDR   0x130000
664 #elif defined(CONFIG_SDCARD)
665 /*
666  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
667  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
668  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
669  */
670 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
671 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
672 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
673 #elif defined(CONFIG_NAND)
674 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
675 #if defined(CONFIG_TARGET_T1024RDB)
676 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
677 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
678 #elif defined(CONFIG_TARGET_T1023RDB)
679 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
680 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
681 #endif
682 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
683 /*
684  * Slave has no ucode locally, it can fetch this from remote. When implementing
685  * in two corenet boards, slave's ucode could be stored in master's memory
686  * space, the address can be mapped from slave TLB->slave LAW->
687  * slave SRIO or PCIE outbound window->master inbound window->
688  * master LAW->the ucode address in master's memory space.
689  */
690 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
691 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
692 #else
693 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
694 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
695 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
696 #endif
697 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
698 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
699 #endif /* CONFIG_NOBQFMAN */
700
701 #ifdef CONFIG_SYS_DPAA_FMAN
702 #define CONFIG_FMAN_ENET
703 #define CONFIG_PHY_REALTEK
704 #if defined(CONFIG_TARGET_T1024RDB)
705 #define RGMII_PHY1_ADDR         0x2
706 #define RGMII_PHY2_ADDR         0x6
707 #define SGMII_AQR_PHY_ADDR      0x2
708 #define FM1_10GEC1_PHY_ADDR     0x1
709 #elif defined(CONFIG_TARGET_T1023RDB)
710 #define RGMII_PHY1_ADDR         0x1
711 #define SGMII_RTK_PHY_ADDR      0x3
712 #define SGMII_AQR_PHY_ADDR      0x2
713 #endif
714 #endif
715
716 #ifdef CONFIG_FMAN_ENET
717 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
718 #endif
719
720 /*
721  * Dynamic MTD Partition support with mtdparts
722  */
723
724 /*
725  * Environment
726  */
727 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
728 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
729
730 /*
731  * Miscellaneous configurable options
732  */
733 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
734
735 /*
736  * For booting Linux, the board info and command line data
737  * have to be in the first 64 MB of memory, since this is
738  * the maximum mapped by the Linux kernel during initialization.
739  */
740 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
741 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
742
743 #ifdef CONFIG_CMD_KGDB
744 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
745 #endif
746
747 /*
748  * Environment Configuration
749  */
750 #define CONFIG_ROOTPATH         "/opt/nfsroot"
751 #define CONFIG_BOOTFILE         "uImage"
752 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
753 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
754 #define __USB_PHY_TYPE          utmi
755
756 #ifdef CONFIG_ARCH_T1024
757 #define CONFIG_BOARDNAME t1024rdb
758 #define BANK_INTLV cs0_cs1
759 #else
760 #define CONFIG_BOARDNAME t1023rdb
761 #define BANK_INTLV  null
762 #endif
763
764 #define CONFIG_EXTRA_ENV_SETTINGS                               \
765         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
766         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
767         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
768         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
769         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
770         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
771         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
772         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
773         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
774         "netdev=eth0\0"                                         \
775         "tftpflash=tftpboot $loadaddr $uboot && "               \
776         "protect off $ubootaddr +$filesize && "                 \
777         "erase $ubootaddr +$filesize && "                       \
778         "cp.b $loadaddr $ubootaddr $filesize && "               \
779         "protect on $ubootaddr +$filesize && "                  \
780         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
781         "consoledev=ttyS0\0"                                    \
782         "ramdiskaddr=2000000\0"                                 \
783         "fdtaddr=1e00000\0"                                     \
784         "bdev=sda3\0"
785
786 #define CONFIG_LINUX                                    \
787         "setenv bootargs root=/dev/ram rw "             \
788         "console=$consoledev,$baudrate $othbootargs;"   \
789         "setenv ramdiskaddr 0x02000000;"                \
790         "setenv fdtaddr 0x00c00000;"                    \
791         "setenv loadaddr 0x1000000;"                    \
792         "bootm $loadaddr $ramdiskaddr $fdtaddr"
793
794 #define CONFIG_NFSBOOTCOMMAND                   \
795         "setenv bootargs root=/dev/nfs rw "     \
796         "nfsroot=$serverip:$rootpath "          \
797         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
798         "console=$consoledev,$baudrate $othbootargs;"   \
799         "tftp $loadaddr $bootfile;"             \
800         "tftp $fdtaddr $fdtfile;"               \
801         "bootm $loadaddr - $fdtaddr"
802
803 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
804
805 #include <asm/fsl_secure_boot.h>
806
807 #endif  /* __T1024RDB_H */