1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T1024/T1023 RDB board configuration file
14 #include <linux/stringify.h>
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
20 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
21 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
23 /* support deep sleep */
24 #ifdef CONFIG_ARCH_T1024
25 #define CONFIG_DEEP_SLEEP
28 #ifdef CONFIG_RAMBOOT_PBL
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_PAD_TO 0x40000
31 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40 #ifdef CONFIG_MTD_RAW_NAND
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
46 #ifdef CONFIG_SPIFLASH
47 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
48 #define CONFIG_SPL_SPI_FLASH_MINIMAL
49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
53 #ifndef CONFIG_SPL_BUILD
54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
59 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
60 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
61 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
62 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
63 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
64 #ifndef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
69 #endif /* CONFIG_RAMBOOT_PBL */
71 #ifndef CONFIG_RESET_VECTOR_ADDRESS
72 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
75 /* PCIe Boot - Master */
76 #define CONFIG_SRIO_PCIE_BOOT_MASTER
78 * for slave u-boot IMAGE instored in master memory space,
79 * PHYS must be aligned based on the SIZE
81 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
85 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
87 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
91 * for slave UCODE and ENV instored in master memory space,
92 * PHYS must be aligned based on the SIZE
94 #ifdef CONFIG_PHYS_64BIT
95 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
96 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
98 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
99 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
101 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
102 /* slave core release by master*/
103 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
104 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
106 /* PCIe Boot - Slave */
107 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
108 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
109 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
110 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
111 /* Set 1M boot space for PCIe boot */
112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
114 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
115 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
119 * These can be toggled for performance analysis, otherwise use default.
121 #define CONFIG_SYS_CACHE_STASHING
122 #define CONFIG_BACKSIDE_L2_CACHE
123 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
124 #define CONFIG_BTB /* toggle branch predition */
125 #ifdef CONFIG_DDR_ECC
126 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
130 * Config the L3 Cache as L3 SRAM
132 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
133 #define CONFIG_SYS_L3_SIZE (256 << 10)
134 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
135 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
136 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
137 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
138 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_DCSRBAR 0xf0000000
142 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
146 #define CONFIG_SYS_I2C_EEPROM_NXID
147 #define CONFIG_SYS_EEPROM_BUS_NUM 0
152 #define CONFIG_VERY_BIG_RAM
153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
155 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
156 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
157 #if defined(CONFIG_TARGET_T1024RDB)
158 #define CONFIG_SYS_SPD_BUS_NUM 0
159 #define SPD_EEPROM_ADDRESS 0x51
160 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
161 #elif defined(CONFIG_TARGET_T1023RDB)
162 #define CONFIG_SYS_DDR_RAW_TIMING
163 #define CONFIG_SYS_SDRAM_SIZE 2048
169 #define CONFIG_SYS_FLASH_BASE 0xe8000000
170 #ifdef CONFIG_PHYS_64BIT
171 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
177 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 CSPR_PORT_SIZE_16 | \
181 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
183 /* NOR Flash Timing Params */
184 #if defined(CONFIG_TARGET_T1024RDB)
185 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
186 #elif defined(CONFIG_TARGET_T1023RDB)
187 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
188 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
190 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
191 FTIM0_NOR_TEADC(0x5) | \
192 FTIM0_NOR_TEAHC(0x5))
193 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
194 FTIM1_NOR_TRAD_NOR(0x1A) |\
195 FTIM1_NOR_TSEQRAD_NOR(0x13))
196 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
197 FTIM2_NOR_TCH(0x4) | \
198 FTIM2_NOR_TWPH(0x0E) | \
200 #define CONFIG_SYS_NOR_FTIM3 0x0
202 #define CONFIG_SYS_FLASH_QUIET_TEST
203 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
205 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
210 #define CONFIG_SYS_FLASH_EMPTY_INFO
211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
213 #ifdef CONFIG_TARGET_T1024RDB
215 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
216 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
217 #define CONFIG_SYS_CSPR2_EXT (0xf)
218 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
222 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
223 #define CONFIG_SYS_CSOR2 0x0
225 /* CPLD Timing parameters for IFC CS2 */
226 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
227 FTIM0_GPCM_TEADC(0x0e) | \
228 FTIM0_GPCM_TEAHC(0x0e))
229 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
230 FTIM1_GPCM_TRAD(0x1f))
231 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
232 FTIM2_GPCM_TCH(0x8) | \
233 FTIM2_GPCM_TWP(0x1f))
234 #define CONFIG_SYS_CS2_FTIM3 0x0
237 /* NAND Flash on IFC */
238 #define CONFIG_SYS_NAND_BASE 0xff800000
239 #ifdef CONFIG_PHYS_64BIT
240 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
242 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
244 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
245 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
246 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
247 | CSPR_MSEL_NAND /* MSEL = NAND */ \
249 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
251 #if defined(CONFIG_TARGET_T1024RDB)
252 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
253 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
254 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
255 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
256 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
257 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
258 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
259 #elif defined(CONFIG_TARGET_T1023RDB)
260 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
261 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
262 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
263 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
264 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
265 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
266 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
269 /* ONFI NAND Flash mode0 Timing Params */
270 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
271 FTIM0_NAND_TWP(0x18) | \
272 FTIM0_NAND_TWCHT(0x07) | \
273 FTIM0_NAND_TWH(0x0a))
274 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
275 FTIM1_NAND_TWBE(0x39) | \
276 FTIM1_NAND_TRR(0x0e) | \
277 FTIM1_NAND_TRP(0x18))
278 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
279 FTIM2_NAND_TREH(0x0a) | \
280 FTIM2_NAND_TWHRE(0x1e))
281 #define CONFIG_SYS_NAND_FTIM3 0x0
283 #define CONFIG_SYS_NAND_DDR_LAW 11
284 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
285 #define CONFIG_SYS_MAX_NAND_DEVICE 1
287 #if defined(CONFIG_MTD_RAW_NAND)
288 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
289 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
290 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
291 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
292 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
293 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
294 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
295 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
296 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
297 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
298 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
299 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
300 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
301 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
302 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
303 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
305 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
306 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
307 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
308 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
309 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
310 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
311 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
312 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
313 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
314 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
315 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
316 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
317 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
318 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
319 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
320 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
323 #ifdef CONFIG_SPL_BUILD
324 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
326 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
329 #if defined(CONFIG_RAMBOOT_PBL)
330 #define CONFIG_SYS_RAMBOOT
333 #define CONFIG_HWCONFIG
335 /* define to use L1 as initial stack */
336 #define CONFIG_L1_INIT_RAM
337 #define CONFIG_SYS_INIT_RAM_LOCK
338 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
339 #ifdef CONFIG_PHYS_64BIT
340 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
341 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
342 /* The assembler doesn't like typecast */
343 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
344 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
345 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
347 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
348 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
351 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
353 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
354 GENERATED_GBL_DATA_SIZE)
355 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
357 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
360 #define CONFIG_SYS_NS16550_SERIAL
361 #define CONFIG_SYS_NS16550_REG_SIZE 1
362 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
364 #define CONFIG_SYS_BAUDRATE_TABLE \
365 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
367 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
368 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
369 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
370 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
373 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
374 #ifdef CONFIG_FSL_DIU_FB
375 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
376 #define CONFIG_VIDEO_BMP_LOGO
377 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
379 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
380 * disable empty flash sector detection, which is I/O-intensive.
382 #undef CONFIG_SYS_FLASH_EMPTY_INFO
387 #define I2C_PCA6408_BUS_NUM 1
388 #define I2C_PCA6408_ADDR 0x20
390 /* I2C bus multiplexer */
391 #define I2C_MUX_CH_DEFAULT 0x8
397 #define CONFIG_RTC_DS1337 1
398 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
401 * eSPI - Enhanced SPI
406 * Memory space is mapped 1-1, but I/O space must start from 0.
408 #define CONFIG_PCIE1 /* PCIE controller 1 */
409 #define CONFIG_PCIE2 /* PCIE controller 2 */
410 #define CONFIG_PCIE3 /* PCIE controller 3 */
413 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
415 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
416 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
417 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
421 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
423 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
424 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
425 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
429 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
431 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
432 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
433 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
434 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
437 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
438 #endif /* CONFIG_PCI */
443 #define CONFIG_HAS_FSL_DR_USB
445 #ifdef CONFIG_HAS_FSL_DR_USB
446 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
453 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
457 #ifndef CONFIG_NOBQFMAN
458 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
459 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
460 #ifdef CONFIG_PHYS_64BIT
461 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
463 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
465 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
466 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
467 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
468 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
469 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
470 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
471 CONFIG_SYS_BMAN_CENA_SIZE)
472 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
473 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
474 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
475 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
479 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
481 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
482 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
483 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
484 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
485 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
486 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
487 CONFIG_SYS_QMAN_CENA_SIZE)
488 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
489 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
491 #define CONFIG_SYS_DPAA_FMAN
493 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
494 #endif /* CONFIG_NOBQFMAN */
496 #ifdef CONFIG_SYS_DPAA_FMAN
497 #if defined(CONFIG_TARGET_T1024RDB)
498 #define RGMII_PHY1_ADDR 0x2
499 #define RGMII_PHY2_ADDR 0x6
500 #define SGMII_AQR_PHY_ADDR 0x2
501 #define FM1_10GEC1_PHY_ADDR 0x1
502 #elif defined(CONFIG_TARGET_T1023RDB)
503 #define RGMII_PHY1_ADDR 0x1
504 #define SGMII_RTK_PHY_ADDR 0x3
505 #define SGMII_AQR_PHY_ADDR 0x2
509 #ifdef CONFIG_FMAN_ENET
510 #define CONFIG_ETHPRIME "FM1@DTSEC4"
514 * Dynamic MTD Partition support with mtdparts
520 #define CONFIG_LOADS_ECHO /* echo on for serial download */
521 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
524 * Miscellaneous configurable options
528 * For booting Linux, the board info and command line data
529 * have to be in the first 64 MB of memory, since this is
530 * the maximum mapped by the Linux kernel during initialization.
532 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
533 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
536 * Environment Configuration
538 #define CONFIG_ROOTPATH "/opt/nfsroot"
539 #define CONFIG_BOOTFILE "uImage"
540 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
541 #define __USB_PHY_TYPE utmi
543 #ifdef CONFIG_ARCH_T1024
544 #define CONFIG_BOARDNAME t1024rdb
545 #define BANK_INTLV cs0_cs1
547 #define CONFIG_BOARDNAME t1023rdb
548 #define BANK_INTLV null
551 #define CONFIG_EXTRA_ENV_SETTINGS \
552 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
553 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
554 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
555 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
556 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
557 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
558 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
559 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
560 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
562 "tftpflash=tftpboot $loadaddr $uboot && " \
563 "protect off $ubootaddr +$filesize && " \
564 "erase $ubootaddr +$filesize && " \
565 "cp.b $loadaddr $ubootaddr $filesize && " \
566 "protect on $ubootaddr +$filesize && " \
567 "cmp.b $loadaddr $ubootaddr $filesize\0" \
568 "consoledev=ttyS0\0" \
569 "ramdiskaddr=2000000\0" \
570 "fdtaddr=1e00000\0" \
573 #include <asm/fsl_secure_boot.h>
575 #endif /* __T1024RDB_H */