include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 #ifdef CONFIG_RAMBOOT_PBL
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 #define CONFIG_SPL_MAX_SIZE             0x28000
  27 #define RESET_VECTOR_OFFSET             0x27FFC
  28 #define BOOT_PAGE_OFFSET                0x27000
  29 #ifdef CONFIG_SPL_BUILD
  30 #define CONFIG_SPL_SKIP_RELOCATE
  31 #define CONFIG_SPL_COMMON_INIT_DDR
  32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  33 #endif
  34
  35 #ifdef CONFIG_MTD_RAW_NAND
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  37 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  38 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  39 #endif
  40
  41 #ifdef CONFIG_SPIFLASH
  42 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  43 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  48 #ifndef CONFIG_SPL_BUILD
  49 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  50 #endif
  51 #endif
  52
  53 #ifdef CONFIG_SDCARD
  54 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  55 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  56 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  57 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  58 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  59 #ifndef CONFIG_SPL_BUILD
  60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  61 #endif
  62 #endif
  63
  64 #endif /* CONFIG_RAMBOOT_PBL */
  65
  66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  67 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  68 #endif
  69
  70 /* PCIe Boot - Master */
  71 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  72 /*
  73  * for slave u-boot IMAGE instored in master memory space,
  74  * PHYS must be aligned based on the SIZE
  75  */
  76 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  77 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  80 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  81 #else
  82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  83 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  84 #endif
  85 /*
  86  * for slave UCODE and ENV instored in master memory space,
  87  * PHYS must be aligned based on the SIZE
  88  */
  89 #ifdef CONFIG_PHYS_64BIT
  90 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  91 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  92 #else
  93 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  94 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  95 #endif
  96 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
  97 /* slave core release by master*/
  98 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
  99 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 100
 101 /* PCIe Boot - Slave */
 102 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 103 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 104 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 105                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 106 /* Set 1M boot space for PCIe boot */
 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 108 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 109                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 111 #endif
 112
 113 /*
 114  * These can be toggled for performance analysis, otherwise use default.
 115  */
 116 #define CONFIG_SYS_CACHE_STASHING
 117 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 118 #ifdef CONFIG_DDR_ECC
 119 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 120 #endif
 121
 122 /*
 123  *  Config the L3 Cache as L3 SRAM
 124  */
 125 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 126 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 127 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 128 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 129 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 130 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 131 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 132
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_SYS_DCSRBAR              0xf0000000
 135 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 136 #endif
 137
 138 /* EEPROM */
 139 #define CONFIG_SYS_I2C_EEPROM_NXID
 140 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 141
 142 /*
 143  * DDR Setup
 144  */
 145 #define CONFIG_VERY_BIG_RAM
 146 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 147 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 148 #if defined(CONFIG_TARGET_T1024RDB)
 149 #define CONFIG_SYS_SPD_BUS_NUM  0
 150 #define SPD_EEPROM_ADDRESS      0x51
 151 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 152 #elif defined(CONFIG_TARGET_T1023RDB)
 153 #define CONFIG_SYS_DDR_RAW_TIMING
 154 #define CONFIG_SYS_SDRAM_SIZE   2048
 155 #endif
 156
 157 /*
 158  * IFC Definitions
 159  */
 160 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 161 #ifdef CONFIG_PHYS_64BIT
 162 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 163 #else
 164 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 165 #endif
 166
 167 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 168 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 169                                 CSPR_PORT_SIZE_16 | \
 170                                 CSPR_MSEL_NOR | \
 171                                 CSPR_V)
 172 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 173
 174 /* NOR Flash Timing Params */
 175 #if defined(CONFIG_TARGET_T1024RDB)
 176 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 177 #elif defined(CONFIG_TARGET_T1023RDB)
 178 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 179                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 180 #endif
 181 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 182                                 FTIM0_NOR_TEADC(0x5) | \
 183                                 FTIM0_NOR_TEAHC(0x5))
 184 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 185                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 186                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 187 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 188                                 FTIM2_NOR_TCH(0x4) | \
 189                                 FTIM2_NOR_TWPH(0x0E) | \
 190                                 FTIM2_NOR_TWP(0x1c))
 191 #define CONFIG_SYS_NOR_FTIM3    0x0
 192
 193 #define CONFIG_SYS_FLASH_QUIET_TEST
 194 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 195
 196 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 197 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 198 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 199
 200 #define CONFIG_SYS_FLASH_EMPTY_INFO
 201 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 202
 203 #ifdef CONFIG_TARGET_T1024RDB
 204 /* CPLD on IFC */
 205 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 206 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 207 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 208 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 209                                                 | CSPR_PORT_SIZE_8 \
 210                                                 | CSPR_MSEL_GPCM \
 211                                                 | CSPR_V)
 212 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 213 #define CONFIG_SYS_CSOR2                0x0
 214
 215 /* CPLD Timing parameters for IFC CS2 */
 216 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 217                                                 FTIM0_GPCM_TEADC(0x0e) | \
 218                                                 FTIM0_GPCM_TEAHC(0x0e))
 219 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 220                                                 FTIM1_GPCM_TRAD(0x1f))
 221 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 222                                                 FTIM2_GPCM_TCH(0x8) | \
 223                                                 FTIM2_GPCM_TWP(0x1f))
 224 #define CONFIG_SYS_CS2_FTIM3            0x0
 225 #endif
 226
 227 /* NAND Flash on IFC */
 228 #define CONFIG_SYS_NAND_BASE            0xff800000
 229 #ifdef CONFIG_PHYS_64BIT
 230 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 231 #else
 232 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 233 #endif
 234 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 235 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 236                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 237                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 238                                 | CSPR_V)
 239 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 240
 241 #if defined(CONFIG_TARGET_T1024RDB)
 242 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 243                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 244                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 245                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 246                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 247                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 248                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 249 #elif defined(CONFIG_TARGET_T1023RDB)
 250 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 251                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 252                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 253                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 254                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 255                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 256                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 257 #endif
 258
 259 /* ONFI NAND Flash mode0 Timing Params */
 260 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 261                                         FTIM0_NAND_TWP(0x18)   | \
 262                                         FTIM0_NAND_TWCHT(0x07) | \
 263                                         FTIM0_NAND_TWH(0x0a))
 264 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 265                                         FTIM1_NAND_TWBE(0x39)  | \
 266                                         FTIM1_NAND_TRR(0x0e)   | \
 267                                         FTIM1_NAND_TRP(0x18))
 268 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 269                                         FTIM2_NAND_TREH(0x0a) | \
 270                                         FTIM2_NAND_TWHRE(0x1e))
 271 #define CONFIG_SYS_NAND_FTIM3           0x0
 272
 273 #define CONFIG_SYS_NAND_DDR_LAW         11
 274 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 275 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 276
 277 #if defined(CONFIG_MTD_RAW_NAND)
 278 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 279 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 280 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 281 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 282 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 283 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 284 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 285 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 286 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 287 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 288 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 289 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 290 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 291 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 292 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 293 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 294 #else
 295 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 296 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 297 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 298 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 299 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 300 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 301 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 302 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 303 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 304 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 305 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 306 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 307 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 308 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 309 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 310 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 311 #endif
 312
 313 #if defined(CONFIG_RAMBOOT_PBL)
 314 #define CONFIG_SYS_RAMBOOT
 315 #endif
 316
 317 #define CONFIG_HWCONFIG
 318
 319 /* define to use L1 as initial stack */
 320 #define CONFIG_L1_INIT_RAM
 321 #define CONFIG_SYS_INIT_RAM_LOCK
 322 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 323 #ifdef CONFIG_PHYS_64BIT
 324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 325 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 326 /* The assembler doesn't like typecast */
 327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 328         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 329           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 330 #else
 331 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 333 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 334 #endif
 335 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 336
 337 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 338                                         GENERATED_GBL_DATA_SIZE)
 339 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 340
 341 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 342
 343 /* Serial Port */
 344 #define CONFIG_SYS_NS16550_SERIAL
 345 #define CONFIG_SYS_NS16550_REG_SIZE     1
 346 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 347
 348 #define CONFIG_SYS_BAUDRATE_TABLE       \
 349         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 350
 351 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 352 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 353 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 354 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 355
 356 /* I2C */
 357
 358 #define I2C_PCA6408_BUS_NUM             1
 359 #define I2C_PCA6408_ADDR                0x20
 360
 361 /* I2C bus multiplexer */
 362 #define I2C_MUX_CH_DEFAULT      0x8
 363
 364 /*
 365  * RTC configuration
 366  */
 367 #define RTC
 368 #define CONFIG_RTC_DS1337       1
 369 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 370
 371 /*
 372  * eSPI - Enhanced SPI
 373  */
 374
 375 /*
 376  * General PCIe
 377  * Memory space is mapped 1-1, but I/O space must start from 0.
 378  */
 379 #define CONFIG_PCIE1            /* PCIE controller 1 */
 380 #define CONFIG_PCIE2            /* PCIE controller 2 */
 381 #define CONFIG_PCIE3            /* PCIE controller 3 */
 382
 383 #ifdef CONFIG_PCI
 384 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 385 #ifdef CONFIG_PCIE1
 386 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 387 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 388 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 389 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 390 #endif
 391
 392 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 393 #ifdef CONFIG_PCIE2
 394 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 395 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 396 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 397 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 398 #endif
 399
 400 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 401 #ifdef CONFIG_PCIE3
 402 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 403 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 404 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 405 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 406 #endif
 407
 408 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 409 #endif  /* CONFIG_PCI */
 410
 411 /*
 412  * USB
 413  */
 414 #define CONFIG_HAS_FSL_DR_USB
 415
 416 #ifdef CONFIG_HAS_FSL_DR_USB
 417 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 418 #endif
 419
 420 /*
 421  * SDHC
 422  */
 423 #ifdef CONFIG_MMC
 424 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 425 #endif
 426
 427 /* Qman/Bman */
 428 #ifndef CONFIG_NOBQFMAN
 429 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 430 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 431 #ifdef CONFIG_PHYS_64BIT
 432 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 433 #else
 434 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 435 #endif
 436 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 437 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 438 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 439 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 440 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 441 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 442                                         CONFIG_SYS_BMAN_CENA_SIZE)
 443 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 444 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 445 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 446 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 447 #ifdef CONFIG_PHYS_64BIT
 448 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 449 #else
 450 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 451 #endif
 452 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 453 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 454 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 455 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 456 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 457 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 458                                         CONFIG_SYS_QMAN_CENA_SIZE)
 459 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 460 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 461
 462 #define CONFIG_SYS_DPAA_FMAN
 463
 464 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 465 #endif /* CONFIG_NOBQFMAN */
 466
 467 #ifdef CONFIG_SYS_DPAA_FMAN
 468 #if defined(CONFIG_TARGET_T1024RDB)
 469 #define RGMII_PHY1_ADDR         0x2
 470 #define RGMII_PHY2_ADDR         0x6
 471 #define SGMII_AQR_PHY_ADDR      0x2
 472 #define FM1_10GEC1_PHY_ADDR     0x1
 473 #elif defined(CONFIG_TARGET_T1023RDB)
 474 #define RGMII_PHY1_ADDR         0x1
 475 #define SGMII_RTK_PHY_ADDR      0x3
 476 #define SGMII_AQR_PHY_ADDR      0x2
 477 #endif
 478 #endif
 479
 480 /*
 481  * Dynamic MTD Partition support with mtdparts
 482  */
 483
 484 /*
 485  * Environment
 486  */
 487 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 488 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 489
 490 /*
 491  * Miscellaneous configurable options
 492  */
 493
 494 /*
 495  * For booting Linux, the board info and command line data
 496  * have to be in the first 64 MB of memory, since this is
 497  * the maximum mapped by the Linux kernel during initialization.
 498  */
 499 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 500 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 501
 502 /*
 503  * Environment Configuration
 504  */
 505 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 506 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 507 #define __USB_PHY_TYPE          utmi
 508
 509 #ifdef CONFIG_ARCH_T1024
 510 #define ARCH_EXTRA_ENV_SETTINGS \
 511         "bank_intlv=cs0_cs1\0"                  \
 512         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 513         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 514 #else
 515 #define ARCH_EXTRA_ENV_SETTINGS \
 516         "bank_intlv=null\0"                     \
 517         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 518         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 519 #endif
 520
 521 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 522         ARCH_EXTRA_ENV_SETTINGS                                 \
 523         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 524         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 525         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 526         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 527         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 528         "netdev=eth0\0"                                         \
 529         "tftpflash=tftpboot $loadaddr $uboot && "               \
 530         "protect off $ubootaddr +$filesize && "                 \
 531         "erase $ubootaddr +$filesize && "                       \
 532         "cp.b $loadaddr $ubootaddr $filesize && "               \
 533         "protect on $ubootaddr +$filesize && "                  \
 534         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 535         "consoledev=ttyS0\0"                                    \
 536         "ramdiskaddr=2000000\0"                                 \
 537         "fdtaddr=1e00000\0"                                     \
 538         "bdev=sda3\0"
 539
 540 #include <asm/fsl_secure_boot.h>
 541
 542 #endif  /* __T1024RDB_H */