include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 /* support deep sleep */
  24 #ifdef CONFIG_ARCH_T1024
  25 #define CONFIG_DEEP_SLEEP
  26 #endif
  27
  28 #ifdef CONFIG_RAMBOOT_PBL
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_PAD_TO               0x40000
  31 #define CONFIG_SPL_MAX_SIZE             0x28000
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_SKIP_RELOCATE
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  38 #endif
  39
  40 #ifdef CONFIG_MTD_RAW_NAND
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  42 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  43 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  44 #endif
  45
  46 #ifdef CONFIG_SPIFLASH
  47 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  48 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  53 #ifndef CONFIG_SPL_BUILD
  54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_SDCARD
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  60 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  61 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  62 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  63 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66 #endif
  67 #endif
  68
  69 #endif /* CONFIG_RAMBOOT_PBL */
  70
  71 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  72 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  73 #endif
  74
  75 /* PCIe Boot - Master */
  76 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  77 /*
  78  * for slave u-boot IMAGE instored in master memory space,
  79  * PHYS must be aligned based on the SIZE
  80  */
  81 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  83 #ifdef CONFIG_PHYS_64BIT
  84 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  85 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  86 #else
  87 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  89 #endif
  90 /*
  91  * for slave UCODE and ENV instored in master memory space,
  92  * PHYS must be aligned based on the SIZE
  93  */
  94 #ifdef CONFIG_PHYS_64BIT
  95 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  96 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  97 #else
  98 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  99 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 100 #endif
 101 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 102 /* slave core release by master*/
 103 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 104 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 105
 106 /* PCIe Boot - Slave */
 107 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 108 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 109 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 110                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 111 /* Set 1M boot space for PCIe boot */
 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 114                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 116 #endif
 117
 118 #define CONFIG_SYS_CLK_FREQ     100000000
 119
 120 /*
 121  * These can be toggled for performance analysis, otherwise use default.
 122  */
 123 #define CONFIG_SYS_CACHE_STASHING
 124 #define CONFIG_BACKSIDE_L2_CACHE
 125 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 126 #define CONFIG_BTB                      /* toggle branch predition */
 127 #ifdef CONFIG_DDR_ECC
 128 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 129 #endif
 130
 131 /*
 132  *  Config the L3 Cache as L3 SRAM
 133  */
 134 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 135 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 136 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 137 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 138 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 139 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 140 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 141
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_SYS_DCSRBAR              0xf0000000
 144 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 145 #endif
 146
 147 /* EEPROM */
 148 #define CONFIG_SYS_I2C_EEPROM_NXID
 149 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 150
 151 /*
 152  * DDR Setup
 153  */
 154 #define CONFIG_VERY_BIG_RAM
 155 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 156 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 157 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 158 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 159 #if defined(CONFIG_TARGET_T1024RDB)
 160 #define CONFIG_SYS_SPD_BUS_NUM  0
 161 #define SPD_EEPROM_ADDRESS      0x51
 162 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 163 #elif defined(CONFIG_TARGET_T1023RDB)
 164 #define CONFIG_SYS_DDR_RAW_TIMING
 165 #define CONFIG_SYS_SDRAM_SIZE   2048
 166 #endif
 167
 168 /*
 169  * IFC Definitions
 170  */
 171 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 172 #ifdef CONFIG_PHYS_64BIT
 173 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 174 #else
 175 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 176 #endif
 177
 178 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 179 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 180                                 CSPR_PORT_SIZE_16 | \
 181                                 CSPR_MSEL_NOR | \
 182                                 CSPR_V)
 183 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 184
 185 /* NOR Flash Timing Params */
 186 #if defined(CONFIG_TARGET_T1024RDB)
 187 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 188 #elif defined(CONFIG_TARGET_T1023RDB)
 189 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 190                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 191 #endif
 192 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 193                                 FTIM0_NOR_TEADC(0x5) | \
 194                                 FTIM0_NOR_TEAHC(0x5))
 195 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 196                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 197                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 198 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 199                                 FTIM2_NOR_TCH(0x4) | \
 200                                 FTIM2_NOR_TWPH(0x0E) | \
 201                                 FTIM2_NOR_TWP(0x1c))
 202 #define CONFIG_SYS_NOR_FTIM3    0x0
 203
 204 #define CONFIG_SYS_FLASH_QUIET_TEST
 205 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 206
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 209 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 210 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 211
 212 #define CONFIG_SYS_FLASH_EMPTY_INFO
 213 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 214
 215 #ifdef CONFIG_TARGET_T1024RDB
 216 /* CPLD on IFC */
 217 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 218 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 219 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 220 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 221                                                 | CSPR_PORT_SIZE_8 \
 222                                                 | CSPR_MSEL_GPCM \
 223                                                 | CSPR_V)
 224 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 225 #define CONFIG_SYS_CSOR2                0x0
 226
 227 /* CPLD Timing parameters for IFC CS2 */
 228 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 229                                                 FTIM0_GPCM_TEADC(0x0e) | \
 230                                                 FTIM0_GPCM_TEAHC(0x0e))
 231 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 232                                                 FTIM1_GPCM_TRAD(0x1f))
 233 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 234                                                 FTIM2_GPCM_TCH(0x8) | \
 235                                                 FTIM2_GPCM_TWP(0x1f))
 236 #define CONFIG_SYS_CS2_FTIM3            0x0
 237 #endif
 238
 239 /* NAND Flash on IFC */
 240 #define CONFIG_SYS_NAND_BASE            0xff800000
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 243 #else
 244 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 245 #endif
 246 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 247 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 248                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 249                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 250                                 | CSPR_V)
 251 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 252
 253 #if defined(CONFIG_TARGET_T1024RDB)
 254 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 255                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 256                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 257                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 258                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 259                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 260                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 261 #elif defined(CONFIG_TARGET_T1023RDB)
 262 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 263                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 264                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 265                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 266                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 267                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 268                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 269 #endif
 270
 271 /* ONFI NAND Flash mode0 Timing Params */
 272 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 273                                         FTIM0_NAND_TWP(0x18)   | \
 274                                         FTIM0_NAND_TWCHT(0x07) | \
 275                                         FTIM0_NAND_TWH(0x0a))
 276 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 277                                         FTIM1_NAND_TWBE(0x39)  | \
 278                                         FTIM1_NAND_TRR(0x0e)   | \
 279                                         FTIM1_NAND_TRP(0x18))
 280 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 281                                         FTIM2_NAND_TREH(0x0a) | \
 282                                         FTIM2_NAND_TWHRE(0x1e))
 283 #define CONFIG_SYS_NAND_FTIM3           0x0
 284
 285 #define CONFIG_SYS_NAND_DDR_LAW         11
 286 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 287 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 288
 289 #if defined(CONFIG_MTD_RAW_NAND)
 290 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 291 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 292 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 293 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 294 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 295 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 296 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 297 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 298 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 299 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 300 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 301 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 302 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 303 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 304 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 305 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 306 #else
 307 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 308 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 309 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 310 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 311 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 312 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 313 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 314 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 315 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 316 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 317 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 318 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 319 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 320 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 321 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 322 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 323 #endif
 324
 325 #ifdef CONFIG_SPL_BUILD
 326 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 327 #else
 328 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 329 #endif
 330
 331 #if defined(CONFIG_RAMBOOT_PBL)
 332 #define CONFIG_SYS_RAMBOOT
 333 #endif
 334
 335 #define CONFIG_HWCONFIG
 336
 337 /* define to use L1 as initial stack */
 338 #define CONFIG_L1_INIT_RAM
 339 #define CONFIG_SYS_INIT_RAM_LOCK
 340 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 341 #ifdef CONFIG_PHYS_64BIT
 342 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 343 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 344 /* The assembler doesn't like typecast */
 345 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 346         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 347           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 348 #else
 349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 352 #endif
 353 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 354
 355 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 356                                         GENERATED_GBL_DATA_SIZE)
 357 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 358
 359 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 360
 361 /* Serial Port */
 362 #define CONFIG_SYS_NS16550_SERIAL
 363 #define CONFIG_SYS_NS16550_REG_SIZE     1
 364 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 365
 366 #define CONFIG_SYS_BAUDRATE_TABLE       \
 367         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 368
 369 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 370 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 371 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 372 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 373
 374 /* Video */
 375 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 376 #ifdef CONFIG_FSL_DIU_FB
 377 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 378 #define CONFIG_VIDEO_LOGO
 379 #define CONFIG_VIDEO_BMP_LOGO
 380 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 381 /*
 382  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 383  * disable empty flash sector detection, which is I/O-intensive.
 384  */
 385 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 386 #endif
 387
 388 /* I2C */
 389
 390 #define I2C_PCA6408_BUS_NUM             1
 391 #define I2C_PCA6408_ADDR                0x20
 392
 393 /* I2C bus multiplexer */
 394 #define I2C_MUX_CH_DEFAULT      0x8
 395
 396 /*
 397  * RTC configuration
 398  */
 399 #define RTC
 400 #define CONFIG_RTC_DS1337       1
 401 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 402
 403 /*
 404  * eSPI - Enhanced SPI
 405  */
 406
 407 /*
 408  * General PCIe
 409  * Memory space is mapped 1-1, but I/O space must start from 0.
 410  */
 411 #define CONFIG_PCIE1            /* PCIE controller 1 */
 412 #define CONFIG_PCIE2            /* PCIE controller 2 */
 413 #define CONFIG_PCIE3            /* PCIE controller 3 */
 414
 415 #ifdef CONFIG_PCI
 416 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 417 #ifdef CONFIG_PCIE1
 418 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 419 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 420 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 421 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 422 #endif
 423
 424 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 425 #ifdef CONFIG_PCIE2
 426 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 427 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 428 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 429 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 430 #endif
 431
 432 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 433 #ifdef CONFIG_PCIE3
 434 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 435 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 436 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 437 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 438 #endif
 439
 440 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 441 #endif  /* CONFIG_PCI */
 442
 443 /*
 444  * USB
 445  */
 446 #define CONFIG_HAS_FSL_DR_USB
 447
 448 #ifdef CONFIG_HAS_FSL_DR_USB
 449 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 450 #endif
 451
 452 /*
 453  * SDHC
 454  */
 455 #ifdef CONFIG_MMC
 456 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 457 #endif
 458
 459 /* Qman/Bman */
 460 #ifndef CONFIG_NOBQFMAN
 461 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 462 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 463 #ifdef CONFIG_PHYS_64BIT
 464 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 465 #else
 466 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 467 #endif
 468 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 469 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 470 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 471 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 472 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 473 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 474                                         CONFIG_SYS_BMAN_CENA_SIZE)
 475 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 476 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 477 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 478 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 479 #ifdef CONFIG_PHYS_64BIT
 480 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 481 #else
 482 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 483 #endif
 484 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 485 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 486 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 487 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 488 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 489 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 490                                         CONFIG_SYS_QMAN_CENA_SIZE)
 491 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 492 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 493
 494 #define CONFIG_SYS_DPAA_FMAN
 495
 496 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 497 #endif /* CONFIG_NOBQFMAN */
 498
 499 #ifdef CONFIG_SYS_DPAA_FMAN
 500 #if defined(CONFIG_TARGET_T1024RDB)
 501 #define RGMII_PHY1_ADDR         0x2
 502 #define RGMII_PHY2_ADDR         0x6
 503 #define SGMII_AQR_PHY_ADDR      0x2
 504 #define FM1_10GEC1_PHY_ADDR     0x1
 505 #elif defined(CONFIG_TARGET_T1023RDB)
 506 #define RGMII_PHY1_ADDR         0x1
 507 #define SGMII_RTK_PHY_ADDR      0x3
 508 #define SGMII_AQR_PHY_ADDR      0x2
 509 #endif
 510 #endif
 511
 512 #ifdef CONFIG_FMAN_ENET
 513 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 514 #endif
 515
 516 /*
 517  * Dynamic MTD Partition support with mtdparts
 518  */
 519
 520 /*
 521  * Environment
 522  */
 523 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 524 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 525
 526 /*
 527  * Miscellaneous configurable options
 528  */
 529
 530 /*
 531  * For booting Linux, the board info and command line data
 532  * have to be in the first 64 MB of memory, since this is
 533  * the maximum mapped by the Linux kernel during initialization.
 534  */
 535 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 536 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 537
 538 /*
 539  * Environment Configuration
 540  */
 541 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 542 #define CONFIG_BOOTFILE         "uImage"
 543 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 544 #define __USB_PHY_TYPE          utmi
 545
 546 #ifdef CONFIG_ARCH_T1024
 547 #define CONFIG_BOARDNAME t1024rdb
 548 #define BANK_INTLV cs0_cs1
 549 #else
 550 #define CONFIG_BOARDNAME t1023rdb
 551 #define BANK_INTLV  null
 552 #endif
 553
 554 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 555         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 556         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 557         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 558         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 559         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 560         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 561         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 562         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 563         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 564         "netdev=eth0\0"                                         \
 565         "tftpflash=tftpboot $loadaddr $uboot && "               \
 566         "protect off $ubootaddr +$filesize && "                 \
 567         "erase $ubootaddr +$filesize && "                       \
 568         "cp.b $loadaddr $ubootaddr $filesize && "               \
 569         "protect on $ubootaddr +$filesize && "                  \
 570         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 571         "consoledev=ttyS0\0"                                    \
 572         "ramdiskaddr=2000000\0"                                 \
 573         "fdtaddr=1e00000\0"                                     \
 574         "bdev=sda3\0"
 575
 576 #include <asm/fsl_secure_boot.h>
 577
 578 #endif  /* __T1024RDB_H */