include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18
  19 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  20 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  28 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  29 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  42 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  43 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  44 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  45 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  52 #endif
  53
  54 /* PCIe Boot - Master */
  55 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  56 /*
  57  * for slave u-boot IMAGE instored in master memory space,
  58  * PHYS must be aligned based on the SIZE
  59  */
  60 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  61 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  62 #ifdef CONFIG_PHYS_64BIT
  63 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  64 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  65 #else
  66 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  67 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  68 #endif
  69 /*
  70  * for slave UCODE and ENV instored in master memory space,
  71  * PHYS must be aligned based on the SIZE
  72  */
  73 #ifdef CONFIG_PHYS_64BIT
  74 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  75 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  76 #else
  77 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  78 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  79 #endif
  80 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
  81 /* slave core release by master*/
  82 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
  83 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
  84
  85 /* PCIe Boot - Slave */
  86 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  87 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  88 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  89                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  90 /* Set 1M boot space for PCIe boot */
  91 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  92 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
  93                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  94 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  95 #endif
  96
  97 /*
  98  * These can be toggled for performance analysis, otherwise use default.
  99  */
 100 #define CONFIG_SYS_CACHE_STASHING
 101 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 102 #ifdef CONFIG_DDR_ECC
 103 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 104 #endif
 105
 106 /*
 107  *  Config the L3 Cache as L3 SRAM
 108  */
 109 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 110 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 111 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 112
 113 #ifdef CONFIG_PHYS_64BIT
 114 #define CONFIG_SYS_DCSRBAR              0xf0000000
 115 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 116 #endif
 117
 118 /* EEPROM */
 119 #define CONFIG_SYS_I2C_EEPROM_NXID
 120 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 121
 122 /*
 123  * DDR Setup
 124  */
 125 #define CONFIG_VERY_BIG_RAM
 126 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 127 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 128 #if defined(CONFIG_TARGET_T1024RDB)
 129 #define SPD_EEPROM_ADDRESS      0x51
 130 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 131 #elif defined(CONFIG_TARGET_T1023RDB)
 132 #define CONFIG_SYS_SDRAM_SIZE   2048
 133 #endif
 134
 135 /*
 136  * IFC Definitions
 137  */
 138 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 139 #ifdef CONFIG_PHYS_64BIT
 140 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 141 #else
 142 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 143 #endif
 144
 145 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 146 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 147                                 CSPR_PORT_SIZE_16 | \
 148                                 CSPR_MSEL_NOR | \
 149                                 CSPR_V)
 150 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 151
 152 /* NOR Flash Timing Params */
 153 #if defined(CONFIG_TARGET_T1024RDB)
 154 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 155 #elif defined(CONFIG_TARGET_T1023RDB)
 156 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 157                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 158 #endif
 159 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 160                                 FTIM0_NOR_TEADC(0x5) | \
 161                                 FTIM0_NOR_TEAHC(0x5))
 162 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 163                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 164                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 165 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 166                                 FTIM2_NOR_TCH(0x4) | \
 167                                 FTIM2_NOR_TWPH(0x0E) | \
 168                                 FTIM2_NOR_TWP(0x1c))
 169 #define CONFIG_SYS_NOR_FTIM3    0x0
 170
 171 #define CONFIG_SYS_FLASH_QUIET_TEST
 172 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 173
 174 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177
 178 #define CONFIG_SYS_FLASH_EMPTY_INFO
 179 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 180
 181 #ifdef CONFIG_TARGET_T1024RDB
 182 /* CPLD on IFC */
 183 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 184 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 185 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 186 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 187                                                 | CSPR_PORT_SIZE_8 \
 188                                                 | CSPR_MSEL_GPCM \
 189                                                 | CSPR_V)
 190 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 191 #define CONFIG_SYS_CSOR2                0x0
 192
 193 /* CPLD Timing parameters for IFC CS2 */
 194 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 195                                                 FTIM0_GPCM_TEADC(0x0e) | \
 196                                                 FTIM0_GPCM_TEAHC(0x0e))
 197 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 198                                                 FTIM1_GPCM_TRAD(0x1f))
 199 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 200                                                 FTIM2_GPCM_TCH(0x8) | \
 201                                                 FTIM2_GPCM_TWP(0x1f))
 202 #define CONFIG_SYS_CS2_FTIM3            0x0
 203 #endif
 204
 205 /* NAND Flash on IFC */
 206 #define CONFIG_SYS_NAND_BASE            0xff800000
 207 #ifdef CONFIG_PHYS_64BIT
 208 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 209 #else
 210 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 211 #endif
 212 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 213 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 214                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 215                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 216                                 | CSPR_V)
 217 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 218
 219 #if defined(CONFIG_TARGET_T1024RDB)
 220 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 221                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 222                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 223                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 224                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 225                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 226                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 227 #elif defined(CONFIG_TARGET_T1023RDB)
 228 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 229                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 230                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 231                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 232                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 233                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 234                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 235 #endif
 236
 237 /* ONFI NAND Flash mode0 Timing Params */
 238 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 239                                         FTIM0_NAND_TWP(0x18)   | \
 240                                         FTIM0_NAND_TWCHT(0x07) | \
 241                                         FTIM0_NAND_TWH(0x0a))
 242 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 243                                         FTIM1_NAND_TWBE(0x39)  | \
 244                                         FTIM1_NAND_TRR(0x0e)   | \
 245                                         FTIM1_NAND_TRP(0x18))
 246 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 247                                         FTIM2_NAND_TREH(0x0a) | \
 248                                         FTIM2_NAND_TWHRE(0x1e))
 249 #define CONFIG_SYS_NAND_FTIM3           0x0
 250
 251 #define CONFIG_SYS_NAND_DDR_LAW         11
 252 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 253 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 254
 255 #if defined(CONFIG_MTD_RAW_NAND)
 256 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 257 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 258 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 259 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 260 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 261 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 262 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 263 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 264 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 265 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 266 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #else
 273 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 274 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 275 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 276 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 277 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 278 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 279 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 280 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 281 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 282 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 283 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 284 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 285 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 286 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 287 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 288 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 289 #endif
 290
 291 #if defined(CONFIG_RAMBOOT_PBL)
 292 #define CONFIG_SYS_RAMBOOT
 293 #endif
 294
 295 #define CONFIG_HWCONFIG
 296
 297 /* define to use L1 as initial stack */
 298 #define CONFIG_L1_INIT_RAM
 299 #define CONFIG_SYS_INIT_RAM_LOCK
 300 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 301 #ifdef CONFIG_PHYS_64BIT
 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 304 /* The assembler doesn't like typecast */
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 306         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 307           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 308 #else
 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 312 #endif
 313 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 314
 315 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 316
 317 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 318
 319 /* Serial Port */
 320 #define CONFIG_SYS_NS16550_SERIAL
 321 #define CONFIG_SYS_NS16550_REG_SIZE     1
 322 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 323
 324 #define CONFIG_SYS_BAUDRATE_TABLE       \
 325         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 326
 327 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 328 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 329 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 330 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 331
 332 /* I2C */
 333
 334 #define I2C_PCA6408_BUS_NUM             1
 335 #define I2C_PCA6408_ADDR                0x20
 336
 337 /* I2C bus multiplexer */
 338 #define I2C_MUX_CH_DEFAULT      0x8
 339
 340 /*
 341  * RTC configuration
 342  */
 343 #define RTC
 344 #define CONFIG_RTC_DS1337       1
 345 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 346
 347 /*
 348  * eSPI - Enhanced SPI
 349  */
 350
 351 /*
 352  * General PCIe
 353  * Memory space is mapped 1-1, but I/O space must start from 0.
 354  */
 355
 356 #ifdef CONFIG_PCI
 357 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 358 #ifdef CONFIG_PCIE1
 359 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 360 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 361 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 362 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 363 #endif
 364
 365 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 366 #ifdef CONFIG_PCIE2
 367 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 368 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 369 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 370 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 371 #endif
 372
 373 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 374 #ifdef CONFIG_PCIE3
 375 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 376 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 377 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 378 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 379 #endif
 380 #endif  /* CONFIG_PCI */
 381
 382 /*
 383  * USB
 384  */
 385
 386 /*
 387  * SDHC
 388  */
 389 #ifdef CONFIG_MMC
 390 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 391 #endif
 392
 393 /* Qman/Bman */
 394 #ifndef CONFIG_NOBQFMAN
 395 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 396 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 397 #ifdef CONFIG_PHYS_64BIT
 398 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 399 #else
 400 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 401 #endif
 402 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 403 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 404 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 405 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 406 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 407 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 408                                         CONFIG_SYS_BMAN_CENA_SIZE)
 409 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 410 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 411 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 412 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 413 #ifdef CONFIG_PHYS_64BIT
 414 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 415 #else
 416 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 417 #endif
 418 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 419 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 420 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 421 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 422 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 423 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 424                                         CONFIG_SYS_QMAN_CENA_SIZE)
 425 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 426 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 427
 428 #define CONFIG_SYS_DPAA_FMAN
 429
 430 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 431 #endif /* CONFIG_NOBQFMAN */
 432
 433 #ifdef CONFIG_SYS_DPAA_FMAN
 434 #if defined(CONFIG_TARGET_T1024RDB)
 435 #define RGMII_PHY1_ADDR         0x2
 436 #define RGMII_PHY2_ADDR         0x6
 437 #define SGMII_AQR_PHY_ADDR      0x2
 438 #define FM1_10GEC1_PHY_ADDR     0x1
 439 #elif defined(CONFIG_TARGET_T1023RDB)
 440 #define RGMII_PHY1_ADDR         0x1
 441 #define SGMII_RTK_PHY_ADDR      0x3
 442 #define SGMII_AQR_PHY_ADDR      0x2
 443 #endif
 444 #endif
 445
 446 /*
 447  * Dynamic MTD Partition support with mtdparts
 448  */
 449
 450 /*
 451  * Environment
 452  */
 453 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 454 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 455
 456 /*
 457  * Miscellaneous configurable options
 458  */
 459
 460 /*
 461  * For booting Linux, the board info and command line data
 462  * have to be in the first 64 MB of memory, since this is
 463  * the maximum mapped by the Linux kernel during initialization.
 464  */
 465 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 466 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 467
 468 /*
 469  * Environment Configuration
 470  */
 471 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 472 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 473 #define __USB_PHY_TYPE          utmi
 474
 475 #ifdef CONFIG_ARCH_T1024
 476 #define ARCH_EXTRA_ENV_SETTINGS \
 477         "bank_intlv=cs0_cs1\0"                  \
 478         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 479         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 480 #else
 481 #define ARCH_EXTRA_ENV_SETTINGS \
 482         "bank_intlv=null\0"                     \
 483         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 484         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 485 #endif
 486
 487 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 488         ARCH_EXTRA_ENV_SETTINGS                                 \
 489         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 490         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 491         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 492         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 493         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 494         "netdev=eth0\0"                                         \
 495         "tftpflash=tftpboot $loadaddr $uboot && "               \
 496         "protect off $ubootaddr +$filesize && "                 \
 497         "erase $ubootaddr +$filesize && "                       \
 498         "cp.b $loadaddr $ubootaddr $filesize && "               \
 499         "protect on $ubootaddr +$filesize && "                  \
 500         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 501         "consoledev=ttyS0\0"                                    \
 502         "ramdiskaddr=2000000\0"                                 \
 503         "fdtaddr=1e00000\0"                                     \
 504         "bdev=sda3\0"
 505
 506 #include <asm/fsl_secure_boot.h>
 507
 508 #endif  /* __T1024RDB_H */