include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17
  18 #define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #define RESET_VECTOR_OFFSET             0x27FFC
  22 #define BOOT_PAGE_OFFSET                0x27000
  23
  24 #ifdef CONFIG_MTD_RAW_NAND
  25 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  26 #define CFG_SYS_NAND_U_BOOT_DST 0x30000000
  27 #define CFG_SYS_NAND_U_BOOT_START       0x30000000
  28 #endif
  29
  30 #ifdef CONFIG_SPIFLASH
  31 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  32 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE   (768 << 10)
  33 #define CFG_SYS_SPI_FLASH_U_BOOT_DST            (0x30000000)
  34 #define CFG_SYS_SPI_FLASH_U_BOOT_START  (0x30000000)
  35 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS   (256 << 10)
  36 #endif
  37
  38 #ifdef CONFIG_SDCARD
  39 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  40 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  41 #define CFG_SYS_MMC_U_BOOT_DST  (0x30000000)
  42 #define CFG_SYS_MMC_U_BOOT_START        (0x30000000)
  43 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  44 #endif
  45
  46 #endif /* CONFIG_RAMBOOT_PBL */
  47
  48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  50 #endif
  51
  52 /*
  53  * for slave u-boot IMAGE instored in master memory space,
  54  * PHYS must be aligned based on the SIZE
  55  */
  56 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  57 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  58 #ifdef CONFIG_PHYS_64BIT
  59 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  60 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  61 #else
  62 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  63 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  64 #endif
  65 /*
  66  * for slave UCODE and ENV instored in master memory space,
  67  * PHYS must be aligned based on the SIZE
  68  */
  69 #ifdef CONFIG_PHYS_64BIT
  70 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  71 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS     0x3ffe00000ull
  72 #else
  73 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  74 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  75 #endif
  76 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE       0x40000 /* 256K */
  77 /* slave core release by master*/
  78 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET   0xe00e4
  79 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  80
  81 /* PCIe Boot - Slave */
  82 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  83 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  84 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  85                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  86 /* Set 1M boot space for PCIe boot */
  87 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  88 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS  \
  89                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  90 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  91 #endif
  92
  93 /*
  94  * These can be toggled for performance analysis, otherwise use default.
  95  */
  96 #define CFG_SYS_INIT_L2CSR0             L2CSR0_L2E
  97 #ifdef CONFIG_DDR_ECC
  98 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  99 #endif
 100
 101 /*
 102  *  Config the L3 Cache as L3 SRAM
 103  */
 104 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
 105 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 106
 107 #ifdef CONFIG_PHYS_64BIT
 108 #define CFG_SYS_DCSRBAR         0xf0000000
 109 #define CFG_SYS_DCSRBAR_PHYS            0xf00000000ull
 110 #endif
 111
 112 /*
 113  * DDR Setup
 114  */
 115 #define CONFIG_VERY_BIG_RAM
 116 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
 117 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
 118 #if defined(CONFIG_TARGET_T1024RDB)
 119 #define SPD_EEPROM_ADDRESS      0x51
 120 #define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
 121 #elif defined(CONFIG_TARGET_T1023RDB)
 122 #define CFG_SYS_SDRAM_SIZE   2048
 123 #endif
 124
 125 /*
 126  * IFC Definitions
 127  */
 128 #define CFG_SYS_FLASH_BASE      0xe8000000
 129 #ifdef CONFIG_PHYS_64BIT
 130 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
 131 #else
 132 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
 133 #endif
 134
 135 #define CFG_SYS_NOR0_CSPR_EXT   (0xf)
 136 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 137                                 CSPR_PORT_SIZE_16 | \
 138                                 CSPR_MSEL_NOR | \
 139                                 CSPR_V)
 140 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 141
 142 /* NOR Flash Timing Params */
 143 #if defined(CONFIG_TARGET_T1024RDB)
 144 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 145 #elif defined(CONFIG_TARGET_T1023RDB)
 146 #define CFG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 147                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 148 #endif
 149 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 150                                 FTIM0_NOR_TEADC(0x5) | \
 151                                 FTIM0_NOR_TEAHC(0x5))
 152 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 153                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 154                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 155 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 156                                 FTIM2_NOR_TCH(0x4) | \
 157                                 FTIM2_NOR_TWPH(0x0E) | \
 158                                 FTIM2_NOR_TWP(0x1c))
 159 #define CFG_SYS_NOR_FTIM3       0x0
 160
 161 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 162
 163 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 164
 165 #ifdef CONFIG_TARGET_T1024RDB
 166 /* CPLD on IFC */
 167 #define CFG_SYS_CPLD_BASE               0xffdf0000
 168 #define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 169 #define CFG_SYS_CSPR2_EXT               (0xf)
 170 #define CFG_SYS_CSPR2           (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
 171                                                 | CSPR_PORT_SIZE_8 \
 172                                                 | CSPR_MSEL_GPCM \
 173                                                 | CSPR_V)
 174 #define CFG_SYS_AMASK2          IFC_AMASK(64*1024)
 175 #define CFG_SYS_CSOR2           0x0
 176
 177 /* CPLD Timing parameters for IFC CS2 */
 178 #define CFG_SYS_CS2_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 179                                                 FTIM0_GPCM_TEADC(0x0e) | \
 180                                                 FTIM0_GPCM_TEAHC(0x0e))
 181 #define CFG_SYS_CS2_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 182                                                 FTIM1_GPCM_TRAD(0x1f))
 183 #define CFG_SYS_CS2_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 184                                                 FTIM2_GPCM_TCH(0x8) | \
 185                                                 FTIM2_GPCM_TWP(0x1f))
 186 #define CFG_SYS_CS2_FTIM3               0x0
 187 #endif
 188
 189 /* NAND Flash on IFC */
 190 #define CFG_SYS_NAND_BASE               0xff800000
 191 #ifdef CONFIG_PHYS_64BIT
 192 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 193 #else
 194 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 195 #endif
 196 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 197 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 198                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 199                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 200                                 | CSPR_V)
 201 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 202
 203 #if defined(CONFIG_TARGET_T1024RDB)
 204 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 205                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 206                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 207                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 208                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 209                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 210                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 211 #elif defined(CONFIG_TARGET_T1023RDB)
 212 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 213                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 214                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 215                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 216                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 217                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 218                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 219 #endif
 220
 221 /* ONFI NAND Flash mode0 Timing Params */
 222 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 223                                         FTIM0_NAND_TWP(0x18)   | \
 224                                         FTIM0_NAND_TWCHT(0x07) | \
 225                                         FTIM0_NAND_TWH(0x0a))
 226 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 227                                         FTIM1_NAND_TWBE(0x39)  | \
 228                                         FTIM1_NAND_TRR(0x0e)   | \
 229                                         FTIM1_NAND_TRP(0x18))
 230 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
 231                                         FTIM2_NAND_TREH(0x0a) | \
 232                                         FTIM2_NAND_TWHRE(0x1e))
 233 #define CFG_SYS_NAND_FTIM3              0x0
 234
 235 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 236
 237 #if defined(CONFIG_MTD_RAW_NAND)
 238 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 239 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 240 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 241 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 242 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 243 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 244 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 245 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 246 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 247 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 248 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 249 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 250 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 251 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 252 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 253 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 254 #else
 255 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 256 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 257 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 258 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 259 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 260 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 261 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 262 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 263 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 264 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 265 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 266 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 267 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 268 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 269 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 270 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 271 #endif
 272
 273 /* define to use L1 as initial stack */
 274 #define CONFIG_L1_INIT_RAM
 275 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000      /* Initial L1 address */
 276 #ifdef CONFIG_PHYS_64BIT
 277 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 278 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 279 /* The assembler doesn't like typecast */
 280 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 281         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 282           CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 283 #else
 284 #define CFG_SYS_INIT_RAM_ADDR_PHYS      0xfe03c000 /* Initial L1 address */
 285 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 286 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
 287 #endif
 288 #define CFG_SYS_INIT_RAM_SIZE           0x00004000
 289
 290 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 291
 292 /* Serial Port */
 293 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 294
 295 #define CFG_SYS_BAUDRATE_TABLE  \
 296         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 297
 298 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x11C500)
 299 #define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x11C600)
 300 #define CFG_SYS_NS16550_COM3    (CFG_SYS_CCSRBAR+0x11D500)
 301 #define CFG_SYS_NS16550_COM4    (CFG_SYS_CCSRBAR+0x11D600)
 302
 303 /* I2C */
 304
 305 #define I2C_PCA6408_BUS_NUM             1
 306 #define I2C_PCA6408_ADDR                0x20
 307
 308 /* I2C bus multiplexer */
 309 #define I2C_MUX_CH_DEFAULT      0x8
 310
 311 /*
 312  * RTC configuration
 313  */
 314 #define CFG_SYS_I2C_RTC_ADDR    0x68
 315
 316 /*
 317  * eSPI - Enhanced SPI
 318  */
 319
 320 /*
 321  * General PCIe
 322  * Memory space is mapped 1-1, but I/O space must start from 0.
 323  */
 324
 325 #ifdef CONFIG_PCI
 326 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 327 #ifdef CONFIG_PCIE1
 328 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 329 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 330 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 331 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 332 #endif
 333
 334 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 335 #ifdef CONFIG_PCIE2
 336 #define CFG_SYS_PCIE2_MEM_VIRT  0x90000000
 337 #define CFG_SYS_PCIE2_MEM_PHYS  0xc10000000ull
 338 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 339 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 340 #endif
 341
 342 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 343 #ifdef CONFIG_PCIE3
 344 #define CFG_SYS_PCIE3_MEM_VIRT  0xa0000000
 345 #define CFG_SYS_PCIE3_MEM_PHYS  0xc20000000ull
 346 #endif
 347 #endif  /* CONFIG_PCI */
 348
 349 /*
 350  * USB
 351  */
 352
 353 /*
 354  * SDHC
 355  */
 356 #ifdef CONFIG_MMC
 357 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 358 #endif
 359
 360 /* Qman/Bman */
 361 #ifndef CONFIG_NOBQFMAN
 362 #define CFG_SYS_BMAN_NUM_PORTALS        10
 363 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 364 #ifdef CONFIG_PHYS_64BIT
 365 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 366 #else
 367 #define CFG_SYS_BMAN_MEM_PHYS   CFG_SYS_BMAN_MEM_BASE
 368 #endif
 369 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 370 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 371 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 372 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 373 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 374 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 375                                         CFG_SYS_BMAN_CENA_SIZE)
 376 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 377 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 378 #define CFG_SYS_QMAN_NUM_PORTALS        10
 379 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 380 #ifdef CONFIG_PHYS_64BIT
 381 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 382 #else
 383 #define CFG_SYS_QMAN_MEM_PHYS   CFG_SYS_QMAN_MEM_BASE
 384 #endif
 385 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 386 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 387 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 388 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 389                                         CFG_SYS_QMAN_CENA_SIZE)
 390 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 391 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 392
 393 #endif /* CONFIG_NOBQFMAN */
 394
 395 #ifdef CONFIG_SYS_DPAA_FMAN
 396 #if defined(CONFIG_TARGET_T1024RDB)
 397 #define RGMII_PHY1_ADDR         0x2
 398 #define RGMII_PHY2_ADDR         0x6
 399 #define SGMII_AQR_PHY_ADDR      0x2
 400 #define FM1_10GEC1_PHY_ADDR     0x1
 401 #elif defined(CONFIG_TARGET_T1023RDB)
 402 #define RGMII_PHY1_ADDR         0x1
 403 #define SGMII_RTK_PHY_ADDR      0x3
 404 #define SGMII_AQR_PHY_ADDR      0x2
 405 #endif
 406 #endif
 407
 408 /*
 409  * Dynamic MTD Partition support with mtdparts
 410  */
 411
 412 /*
 413  * Miscellaneous configurable options
 414  */
 415
 416 /*
 417  * For booting Linux, the board info and command line data
 418  * have to be in the first 64 MB of memory, since this is
 419  * the maximum mapped by the Linux kernel during initialization.
 420  */
 421 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 422
 423 /*
 424  * Environment Configuration
 425  */
 426 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 427 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 428 #define __USB_PHY_TYPE          utmi
 429
 430 #ifdef CONFIG_ARCH_T1024
 431 #define ARCH_EXTRA_ENV_SETTINGS \
 432         "bank_intlv=cs0_cs1\0"                  \
 433         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 434         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 435 #else
 436 #define ARCH_EXTRA_ENV_SETTINGS \
 437         "bank_intlv=null\0"                     \
 438         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 439         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 440 #endif
 441
 442 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 443         ARCH_EXTRA_ENV_SETTINGS                                 \
 444         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 445         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 446         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 447         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 448         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 449         "netdev=eth0\0"                                         \
 450         "tftpflash=tftpboot $loadaddr $uboot && "               \
 451         "protect off $ubootaddr +$filesize && "                 \
 452         "erase $ubootaddr +$filesize && "                       \
 453         "cp.b $loadaddr $ubootaddr $filesize && "               \
 454         "protect on $ubootaddr +$filesize && "                  \
 455         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 456         "consoledev=ttyS0\0"                                    \
 457         "ramdiskaddr=2000000\0"                                 \
 458         "fdtaddr=1e00000\0"                                     \
 459         "bdev=sda3\0"
 460
 461 #include <asm/fsl_secure_boot.h>
 462
 463 #endif  /* __T1024RDB_H */