include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 #ifdef CONFIG_RAMBOOT_PBL
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26
  27 #ifdef CONFIG_MTD_RAW_NAND
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  30 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  31 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  32 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  33 #endif
  34 #endif
  35
  36 #ifdef CONFIG_SPIFLASH
  37 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  42 #ifndef CONFIG_SPL_BUILD
  43 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  44 #endif
  45 #endif
  46
  47 #ifdef CONFIG_SDCARD
  48 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  49 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  50 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  51 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  52 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  53 #ifndef CONFIG_SPL_BUILD
  54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  55 #endif
  56 #endif
  57
  58 #endif /* CONFIG_RAMBOOT_PBL */
  59
  60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  61 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  62 #endif
  63
  64 /* PCIe Boot - Master */
  65 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  66 /*
  67  * for slave u-boot IMAGE instored in master memory space,
  68  * PHYS must be aligned based on the SIZE
  69  */
  70 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  71 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  72 #ifdef CONFIG_PHYS_64BIT
  73 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  74 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  75 #else
  76 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  77 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  78 #endif
  79 /*
  80  * for slave UCODE and ENV instored in master memory space,
  81  * PHYS must be aligned based on the SIZE
  82  */
  83 #ifdef CONFIG_PHYS_64BIT
  84 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  85 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  86 #else
  87 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  88 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  89 #endif
  90 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
  91 /* slave core release by master*/
  92 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
  93 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
  94
  95 /* PCIe Boot - Slave */
  96 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  97 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  98 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  99                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 100 /* Set 1M boot space for PCIe boot */
 101 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 102 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 103                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 104 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 105 #endif
 106
 107 /*
 108  * These can be toggled for performance analysis, otherwise use default.
 109  */
 110 #define CONFIG_SYS_CACHE_STASHING
 111 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 112 #ifdef CONFIG_DDR_ECC
 113 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 114 #endif
 115
 116 /*
 117  *  Config the L3 Cache as L3 SRAM
 118  */
 119 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 120 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 121 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 122
 123 #ifdef CONFIG_PHYS_64BIT
 124 #define CONFIG_SYS_DCSRBAR              0xf0000000
 125 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 126 #endif
 127
 128 /* EEPROM */
 129 #define CONFIG_SYS_I2C_EEPROM_NXID
 130 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 131
 132 /*
 133  * DDR Setup
 134  */
 135 #define CONFIG_VERY_BIG_RAM
 136 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 137 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 138 #if defined(CONFIG_TARGET_T1024RDB)
 139 #define CONFIG_SYS_SPD_BUS_NUM  0
 140 #define SPD_EEPROM_ADDRESS      0x51
 141 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 142 #elif defined(CONFIG_TARGET_T1023RDB)
 143 #define CONFIG_SYS_DDR_RAW_TIMING
 144 #define CONFIG_SYS_SDRAM_SIZE   2048
 145 #endif
 146
 147 /*
 148  * IFC Definitions
 149  */
 150 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 151 #ifdef CONFIG_PHYS_64BIT
 152 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 153 #else
 154 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 155 #endif
 156
 157 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 158 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 159                                 CSPR_PORT_SIZE_16 | \
 160                                 CSPR_MSEL_NOR | \
 161                                 CSPR_V)
 162 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 163
 164 /* NOR Flash Timing Params */
 165 #if defined(CONFIG_TARGET_T1024RDB)
 166 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 167 #elif defined(CONFIG_TARGET_T1023RDB)
 168 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 169                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 170 #endif
 171 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 172                                 FTIM0_NOR_TEADC(0x5) | \
 173                                 FTIM0_NOR_TEAHC(0x5))
 174 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 175                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 176                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 177 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 178                                 FTIM2_NOR_TCH(0x4) | \
 179                                 FTIM2_NOR_TWPH(0x0E) | \
 180                                 FTIM2_NOR_TWP(0x1c))
 181 #define CONFIG_SYS_NOR_FTIM3    0x0
 182
 183 #define CONFIG_SYS_FLASH_QUIET_TEST
 184 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 185
 186 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 187 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 188 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 189
 190 #define CONFIG_SYS_FLASH_EMPTY_INFO
 191 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 192
 193 #ifdef CONFIG_TARGET_T1024RDB
 194 /* CPLD on IFC */
 195 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 196 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 197 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 198 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 199                                                 | CSPR_PORT_SIZE_8 \
 200                                                 | CSPR_MSEL_GPCM \
 201                                                 | CSPR_V)
 202 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 203 #define CONFIG_SYS_CSOR2                0x0
 204
 205 /* CPLD Timing parameters for IFC CS2 */
 206 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 207                                                 FTIM0_GPCM_TEADC(0x0e) | \
 208                                                 FTIM0_GPCM_TEAHC(0x0e))
 209 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 210                                                 FTIM1_GPCM_TRAD(0x1f))
 211 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 212                                                 FTIM2_GPCM_TCH(0x8) | \
 213                                                 FTIM2_GPCM_TWP(0x1f))
 214 #define CONFIG_SYS_CS2_FTIM3            0x0
 215 #endif
 216
 217 /* NAND Flash on IFC */
 218 #define CONFIG_SYS_NAND_BASE            0xff800000
 219 #ifdef CONFIG_PHYS_64BIT
 220 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 221 #else
 222 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 223 #endif
 224 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 225 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 226                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 227                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 228                                 | CSPR_V)
 229 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 230
 231 #if defined(CONFIG_TARGET_T1024RDB)
 232 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 233                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 234                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 235                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 236                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 237                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 238                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 239 #elif defined(CONFIG_TARGET_T1023RDB)
 240 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 241                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 242                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 243                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 244                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 245                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 246                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 247 #endif
 248
 249 /* ONFI NAND Flash mode0 Timing Params */
 250 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 251                                         FTIM0_NAND_TWP(0x18)   | \
 252                                         FTIM0_NAND_TWCHT(0x07) | \
 253                                         FTIM0_NAND_TWH(0x0a))
 254 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 255                                         FTIM1_NAND_TWBE(0x39)  | \
 256                                         FTIM1_NAND_TRR(0x0e)   | \
 257                                         FTIM1_NAND_TRP(0x18))
 258 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 259                                         FTIM2_NAND_TREH(0x0a) | \
 260                                         FTIM2_NAND_TWHRE(0x1e))
 261 #define CONFIG_SYS_NAND_FTIM3           0x0
 262
 263 #define CONFIG_SYS_NAND_DDR_LAW         11
 264 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 265 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 266
 267 #if defined(CONFIG_MTD_RAW_NAND)
 268 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 269 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 270 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 271 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 272 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 273 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 274 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 275 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 276 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 277 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 278 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 279 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 280 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 281 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 282 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 283 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 284 #else
 285 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 286 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 287 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 288 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 289 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 290 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 291 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 292 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 293 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 294 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 295 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 296 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 297 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 298 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 299 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 300 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 301 #endif
 302
 303 #if defined(CONFIG_RAMBOOT_PBL)
 304 #define CONFIG_SYS_RAMBOOT
 305 #endif
 306
 307 #define CONFIG_HWCONFIG
 308
 309 /* define to use L1 as initial stack */
 310 #define CONFIG_L1_INIT_RAM
 311 #define CONFIG_SYS_INIT_RAM_LOCK
 312 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 316 /* The assembler doesn't like typecast */
 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 318         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 319           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 320 #else
 321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 324 #endif
 325 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 326
 327 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 328
 329 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 330
 331 /* Serial Port */
 332 #define CONFIG_SYS_NS16550_SERIAL
 333 #define CONFIG_SYS_NS16550_REG_SIZE     1
 334 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 335
 336 #define CONFIG_SYS_BAUDRATE_TABLE       \
 337         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 338
 339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 341 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 342 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 343
 344 /* I2C */
 345
 346 #define I2C_PCA6408_BUS_NUM             1
 347 #define I2C_PCA6408_ADDR                0x20
 348
 349 /* I2C bus multiplexer */
 350 #define I2C_MUX_CH_DEFAULT      0x8
 351
 352 /*
 353  * RTC configuration
 354  */
 355 #define RTC
 356 #define CONFIG_RTC_DS1337       1
 357 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 358
 359 /*
 360  * eSPI - Enhanced SPI
 361  */
 362
 363 /*
 364  * General PCIe
 365  * Memory space is mapped 1-1, but I/O space must start from 0.
 366  */
 367 #define CONFIG_PCIE1            /* PCIE controller 1 */
 368 #define CONFIG_PCIE2            /* PCIE controller 2 */
 369 #define CONFIG_PCIE3            /* PCIE controller 3 */
 370
 371 #ifdef CONFIG_PCI
 372 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 373 #ifdef CONFIG_PCIE1
 374 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 375 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 376 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 377 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 378 #endif
 379
 380 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 381 #ifdef CONFIG_PCIE2
 382 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 383 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 384 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 385 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 386 #endif
 387
 388 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 389 #ifdef CONFIG_PCIE3
 390 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 391 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 392 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 393 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 394 #endif
 395
 396 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 397 #endif  /* CONFIG_PCI */
 398
 399 /*
 400  * USB
 401  */
 402 #define CONFIG_HAS_FSL_DR_USB
 403
 404 #ifdef CONFIG_HAS_FSL_DR_USB
 405 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 406 #endif
 407
 408 /*
 409  * SDHC
 410  */
 411 #ifdef CONFIG_MMC
 412 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 413 #endif
 414
 415 /* Qman/Bman */
 416 #ifndef CONFIG_NOBQFMAN
 417 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 418 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 419 #ifdef CONFIG_PHYS_64BIT
 420 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 421 #else
 422 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 423 #endif
 424 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 425 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 426 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 427 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 428 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 429 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 430                                         CONFIG_SYS_BMAN_CENA_SIZE)
 431 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 432 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 433 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 434 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 435 #ifdef CONFIG_PHYS_64BIT
 436 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 437 #else
 438 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 439 #endif
 440 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 441 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 442 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 443 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 444 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 445 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 446                                         CONFIG_SYS_QMAN_CENA_SIZE)
 447 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 448 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 449
 450 #define CONFIG_SYS_DPAA_FMAN
 451
 452 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 453 #endif /* CONFIG_NOBQFMAN */
 454
 455 #ifdef CONFIG_SYS_DPAA_FMAN
 456 #if defined(CONFIG_TARGET_T1024RDB)
 457 #define RGMII_PHY1_ADDR         0x2
 458 #define RGMII_PHY2_ADDR         0x6
 459 #define SGMII_AQR_PHY_ADDR      0x2
 460 #define FM1_10GEC1_PHY_ADDR     0x1
 461 #elif defined(CONFIG_TARGET_T1023RDB)
 462 #define RGMII_PHY1_ADDR         0x1
 463 #define SGMII_RTK_PHY_ADDR      0x3
 464 #define SGMII_AQR_PHY_ADDR      0x2
 465 #endif
 466 #endif
 467
 468 /*
 469  * Dynamic MTD Partition support with mtdparts
 470  */
 471
 472 /*
 473  * Environment
 474  */
 475 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 476 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 477
 478 /*
 479  * Miscellaneous configurable options
 480  */
 481
 482 /*
 483  * For booting Linux, the board info and command line data
 484  * have to be in the first 64 MB of memory, since this is
 485  * the maximum mapped by the Linux kernel during initialization.
 486  */
 487 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 488 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 489
 490 /*
 491  * Environment Configuration
 492  */
 493 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 494 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 495 #define __USB_PHY_TYPE          utmi
 496
 497 #ifdef CONFIG_ARCH_T1024
 498 #define ARCH_EXTRA_ENV_SETTINGS \
 499         "bank_intlv=cs0_cs1\0"                  \
 500         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 501         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 502 #else
 503 #define ARCH_EXTRA_ENV_SETTINGS \
 504         "bank_intlv=null\0"                     \
 505         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 506         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 507 #endif
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 510         ARCH_EXTRA_ENV_SETTINGS                                 \
 511         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 512         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 513         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 514         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 515         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 516         "netdev=eth0\0"                                         \
 517         "tftpflash=tftpboot $loadaddr $uboot && "               \
 518         "protect off $ubootaddr +$filesize && "                 \
 519         "erase $ubootaddr +$filesize && "                       \
 520         "cp.b $loadaddr $ubootaddr $filesize && "               \
 521         "protect on $ubootaddr +$filesize && "                  \
 522         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 523         "consoledev=ttyS0\0"                                    \
 524         "ramdiskaddr=2000000\0"                                 \
 525         "fdtaddr=1e00000\0"                                     \
 526         "bdev=sda3\0"
 527
 528 #include <asm/fsl_secure_boot.h>
 529
 530 #endif  /* __T1024RDB_H */