include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 RDB board configuration file
   8  */
   9
  10 #ifndef __T1024RDB_H
  11 #define __T1024RDB_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 /* support deep sleep */
  28 #ifdef CONFIG_ARCH_T1024
  29 #define CONFIG_DEEP_SLEEP
  30 #endif
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_SKIP_RELOCATE
  41 #define CONFIG_SPL_COMMON_INIT_DDR
  42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 #endif
  44
  45 #ifdef CONFIG_MTD_RAW_NAND
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  50 #if defined(CONFIG_TARGET_T1024RDB)
  51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  52 #elif defined(CONFIG_TARGET_T1023RDB)
  53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  54 #endif
  55 #endif
  56
  57 #ifdef CONFIG_SPIFLASH
  58 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66 #endif
  67 #if defined(CONFIG_TARGET_T1024RDB)
  68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  69 #elif defined(CONFIG_TARGET_T1023RDB)
  70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  71 #endif
  72 #endif
  73
  74 #ifdef CONFIG_SDCARD
  75 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  76 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  77 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  78 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  79 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  80 #ifndef CONFIG_SPL_BUILD
  81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  82 #endif
  83 #if defined(CONFIG_TARGET_T1024RDB)
  84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  85 #elif defined(CONFIG_TARGET_T1023RDB)
  86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  87 #endif
  88 #endif
  89
  90 #endif /* CONFIG_RAMBOOT_PBL */
  91
  92 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  93 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  94 #endif
  95
  96 /* PCIe Boot - Master */
  97 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  98 /*
  99  * for slave u-boot IMAGE instored in master memory space,
 100  * PHYS must be aligned based on the SIZE
 101  */
 102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 104 #ifdef CONFIG_PHYS_64BIT
 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 107 #else
 108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 110 #endif
 111 /*
 112  * for slave UCODE and ENV instored in master memory space,
 113  * PHYS must be aligned based on the SIZE
 114  */
 115 #ifdef CONFIG_PHYS_64BIT
 116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 118 #else
 119 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 121 #endif
 122 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 123 /* slave core release by master*/
 124 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 125 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 126
 127 /* PCIe Boot - Slave */
 128 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 131                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 132 /* Set 1M boot space for PCIe boot */
 133 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 135                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 136 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 137 #endif
 138
 139 #if defined(CONFIG_SPIFLASH)
 140 #elif defined(CONFIG_SDCARD)
 141 #define CONFIG_SYS_MMC_ENV_DEV          0
 142 #endif
 143
 144 #ifndef __ASSEMBLY__
 145 unsigned long get_board_sys_clk(void);
 146 unsigned long get_board_ddr_clk(void);
 147 #endif
 148
 149 #define CONFIG_SYS_CLK_FREQ     100000000
 150 #define CONFIG_DDR_CLK_FREQ     100000000
 151
 152 /*
 153  * These can be toggled for performance analysis, otherwise use default.
 154  */
 155 #define CONFIG_SYS_CACHE_STASHING
 156 #define CONFIG_BACKSIDE_L2_CACHE
 157 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 158 #define CONFIG_BTB                      /* toggle branch predition */
 159 #define CONFIG_DDR_ECC
 160 #ifdef CONFIG_DDR_ECC
 161 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 162 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 163 #endif
 164
 165 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 166 #define CONFIG_SYS_MEMTEST_END          0x00400000
 167
 168 /*
 169  *  Config the L3 Cache as L3 SRAM
 170  */
 171 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 172 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 173 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 174 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 175 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 176 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 177 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 178
 179 #ifdef CONFIG_PHYS_64BIT
 180 #define CONFIG_SYS_DCSRBAR              0xf0000000
 181 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 182 #endif
 183
 184 /* EEPROM */
 185 #define CONFIG_ID_EEPROM
 186 #define CONFIG_SYS_I2C_EEPROM_NXID
 187 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 188 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 192
 193 /*
 194  * DDR Setup
 195  */
 196 #define CONFIG_VERY_BIG_RAM
 197 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 198 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 199 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 200 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 201 #if defined(CONFIG_TARGET_T1024RDB)
 202 #define CONFIG_DDR_SPD
 203 #define CONFIG_SYS_SPD_BUS_NUM  0
 204 #define SPD_EEPROM_ADDRESS      0x51
 205 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 206 #elif defined(CONFIG_TARGET_T1023RDB)
 207 #define CONFIG_SYS_DDR_RAW_TIMING
 208 #define CONFIG_SYS_SDRAM_SIZE   2048
 209 #endif
 210
 211 /*
 212  * IFC Definitions
 213  */
 214 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 215 #ifdef CONFIG_PHYS_64BIT
 216 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 217 #else
 218 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 219 #endif
 220
 221 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 222 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 223                                 CSPR_PORT_SIZE_16 | \
 224                                 CSPR_MSEL_NOR | \
 225                                 CSPR_V)
 226 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 227
 228 /* NOR Flash Timing Params */
 229 #if defined(CONFIG_TARGET_T1024RDB)
 230 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 231 #elif defined(CONFIG_TARGET_T1023RDB)
 232 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 233                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 234 #endif
 235 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 236                                 FTIM0_NOR_TEADC(0x5) | \
 237                                 FTIM0_NOR_TEAHC(0x5))
 238 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 239                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 240                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 241 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 242                                 FTIM2_NOR_TCH(0x4) | \
 243                                 FTIM2_NOR_TWPH(0x0E) | \
 244                                 FTIM2_NOR_TWP(0x1c))
 245 #define CONFIG_SYS_NOR_FTIM3    0x0
 246
 247 #define CONFIG_SYS_FLASH_QUIET_TEST
 248 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 249
 250 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 251 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 252 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 253 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 254
 255 #define CONFIG_SYS_FLASH_EMPTY_INFO
 256 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 257
 258 #ifdef CONFIG_TARGET_T1024RDB
 259 /* CPLD on IFC */
 260 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 261 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 262 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 263 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 264                                                 | CSPR_PORT_SIZE_8 \
 265                                                 | CSPR_MSEL_GPCM \
 266                                                 | CSPR_V)
 267 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 268 #define CONFIG_SYS_CSOR2                0x0
 269
 270 /* CPLD Timing parameters for IFC CS2 */
 271 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 272                                                 FTIM0_GPCM_TEADC(0x0e) | \
 273                                                 FTIM0_GPCM_TEAHC(0x0e))
 274 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 275                                                 FTIM1_GPCM_TRAD(0x1f))
 276 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 277                                                 FTIM2_GPCM_TCH(0x8) | \
 278                                                 FTIM2_GPCM_TWP(0x1f))
 279 #define CONFIG_SYS_CS2_FTIM3            0x0
 280 #endif
 281
 282 /* NAND Flash on IFC */
 283 #define CONFIG_NAND_FSL_IFC
 284 #define CONFIG_SYS_NAND_BASE            0xff800000
 285 #ifdef CONFIG_PHYS_64BIT
 286 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 287 #else
 288 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 289 #endif
 290 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 291 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 292                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 293                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 294                                 | CSPR_V)
 295 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 296
 297 #if defined(CONFIG_TARGET_T1024RDB)
 298 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 299                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 300                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 301                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 302                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 303                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 304                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 305 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 306 #elif defined(CONFIG_TARGET_T1023RDB)
 307 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 308                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 309                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 310                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 311                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 312                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 313                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 314 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 315 #endif
 316
 317 #define CONFIG_SYS_NAND_ONFI_DETECTION
 318 /* ONFI NAND Flash mode0 Timing Params */
 319 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 320                                         FTIM0_NAND_TWP(0x18)   | \
 321                                         FTIM0_NAND_TWCHT(0x07) | \
 322                                         FTIM0_NAND_TWH(0x0a))
 323 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 324                                         FTIM1_NAND_TWBE(0x39)  | \
 325                                         FTIM1_NAND_TRR(0x0e)   | \
 326                                         FTIM1_NAND_TRP(0x18))
 327 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 328                                         FTIM2_NAND_TREH(0x0a) | \
 329                                         FTIM2_NAND_TWHRE(0x1e))
 330 #define CONFIG_SYS_NAND_FTIM3           0x0
 331
 332 #define CONFIG_SYS_NAND_DDR_LAW         11
 333 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 334 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 335
 336 #if defined(CONFIG_MTD_RAW_NAND)
 337 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 338 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 339 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 340 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 341 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 342 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 343 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 344 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 345 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 346 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 347 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 348 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 349 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 350 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 351 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 352 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 353 #else
 354 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 355 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 356 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 357 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 358 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 359 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 360 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 361 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 362 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 363 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 364 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 365 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 366 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 367 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 368 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 369 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 370 #endif
 371
 372 #ifdef CONFIG_SPL_BUILD
 373 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 374 #else
 375 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 376 #endif
 377
 378 #if defined(CONFIG_RAMBOOT_PBL)
 379 #define CONFIG_SYS_RAMBOOT
 380 #endif
 381
 382 #define CONFIG_HWCONFIG
 383
 384 /* define to use L1 as initial stack */
 385 #define CONFIG_L1_INIT_RAM
 386 #define CONFIG_SYS_INIT_RAM_LOCK
 387 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 388 #ifdef CONFIG_PHYS_64BIT
 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 391 /* The assembler doesn't like typecast */
 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 393         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 394           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 395 #else
 396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 399 #endif
 400 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 401
 402 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 403                                         GENERATED_GBL_DATA_SIZE)
 404 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 405
 406 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 407 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 408
 409 /* Serial Port */
 410 #define CONFIG_SYS_NS16550_SERIAL
 411 #define CONFIG_SYS_NS16550_REG_SIZE     1
 412 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 413
 414 #define CONFIG_SYS_BAUDRATE_TABLE       \
 415         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 416
 417 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 418 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 419 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 420 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 421
 422 /* Video */
 423 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 424 #ifdef CONFIG_FSL_DIU_FB
 425 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 426 #define CONFIG_VIDEO_LOGO
 427 #define CONFIG_VIDEO_BMP_LOGO
 428 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 429 /*
 430  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 431  * disable empty flash sector detection, which is I/O-intensive.
 432  */
 433 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 434 #endif
 435
 436 /* I2C */
 437 #define CONFIG_SYS_I2C
 438 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 439 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 440 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 441 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 442 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 443 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 444 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 445
 446 #define I2C_PCA6408_BUS_NUM             1
 447 #define I2C_PCA6408_ADDR                0x20
 448
 449 /* I2C bus multiplexer */
 450 #define I2C_MUX_CH_DEFAULT      0x8
 451
 452 /*
 453  * RTC configuration
 454  */
 455 #define RTC
 456 #define CONFIG_RTC_DS1337       1
 457 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 458
 459 /*
 460  * eSPI - Enhanced SPI
 461  */
 462
 463 /*
 464  * General PCIe
 465  * Memory space is mapped 1-1, but I/O space must start from 0.
 466  */
 467 #define CONFIG_PCIE1            /* PCIE controller 1 */
 468 #define CONFIG_PCIE2            /* PCIE controller 2 */
 469 #define CONFIG_PCIE3            /* PCIE controller 3 */
 470 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 471
 472 #ifdef CONFIG_PCI
 473 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 474 #ifdef CONFIG_PCIE1
 475 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 476 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 477 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 478 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 479 #endif
 480
 481 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 482 #ifdef CONFIG_PCIE2
 483 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 484 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 485 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 486 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 487 #endif
 488
 489 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 490 #ifdef CONFIG_PCIE3
 491 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 492 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 493 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 494 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 495 #endif
 496
 497 #if !defined(CONFIG_DM_PCI)
 498 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 499 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 500 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 501 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 502 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 503 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 504 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 505 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 506 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 507 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 508 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 509 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 510 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 511 #define CONFIG_PCI_INDIRECT_BRIDGE
 512 #endif
 513
 514 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 515 #endif  /* CONFIG_PCI */
 516
 517 /*
 518  * USB
 519  */
 520 #define CONFIG_HAS_FSL_DR_USB
 521
 522 #ifdef CONFIG_HAS_FSL_DR_USB
 523 #define CONFIG_USB_EHCI_FSL
 524 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 525 #endif
 526
 527 /*
 528  * SDHC
 529  */
 530 #ifdef CONFIG_MMC
 531 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 532 #endif
 533
 534 /* Qman/Bman */
 535 #ifndef CONFIG_NOBQFMAN
 536 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 537 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 538 #ifdef CONFIG_PHYS_64BIT
 539 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 540 #else
 541 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 542 #endif
 543 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 544 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 545 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 546 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 547 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 548 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 549                                         CONFIG_SYS_BMAN_CENA_SIZE)
 550 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 551 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 552 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 553 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 554 #ifdef CONFIG_PHYS_64BIT
 555 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 556 #else
 557 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 558 #endif
 559 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 560 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 561 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 562 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 563 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 564 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 565                                         CONFIG_SYS_QMAN_CENA_SIZE)
 566 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 567 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 568
 569 #define CONFIG_SYS_DPAA_FMAN
 570
 571 /* Default address of microcode for the Linux FMan driver */
 572 #if defined(CONFIG_SPIFLASH)
 573 /*
 574  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 575  * env, so we got 0x110000.
 576  */
 577 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 578 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 579 #elif defined(CONFIG_SDCARD)
 580 /*
 581  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 582  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 583  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 584  */
 585 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 586 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 587 #elif defined(CONFIG_MTD_RAW_NAND)
 588 #if defined(CONFIG_TARGET_T1024RDB)
 589 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 590 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 591 #elif defined(CONFIG_TARGET_T1023RDB)
 592 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 593 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 594 #endif
 595 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 596 /*
 597  * Slave has no ucode locally, it can fetch this from remote. When implementing
 598  * in two corenet boards, slave's ucode could be stored in master's memory
 599  * space, the address can be mapped from slave TLB->slave LAW->
 600  * slave SRIO or PCIE outbound window->master inbound window->
 601  * master LAW->the ucode address in master's memory space.
 602  */
 603 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 604 #else
 605 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 606 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 607 #endif
 608 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 609 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 610 #endif /* CONFIG_NOBQFMAN */
 611
 612 #ifdef CONFIG_SYS_DPAA_FMAN
 613 #define CONFIG_PHY_REALTEK
 614 #if defined(CONFIG_TARGET_T1024RDB)
 615 #define RGMII_PHY1_ADDR         0x2
 616 #define RGMII_PHY2_ADDR         0x6
 617 #define SGMII_AQR_PHY_ADDR      0x2
 618 #define FM1_10GEC1_PHY_ADDR     0x1
 619 #elif defined(CONFIG_TARGET_T1023RDB)
 620 #define RGMII_PHY1_ADDR         0x1
 621 #define SGMII_RTK_PHY_ADDR      0x3
 622 #define SGMII_AQR_PHY_ADDR      0x2
 623 #endif
 624 #endif
 625
 626 #ifdef CONFIG_FMAN_ENET
 627 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 628 #endif
 629
 630 /*
 631  * Dynamic MTD Partition support with mtdparts
 632  */
 633
 634 /*
 635  * Environment
 636  */
 637 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 638 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 639
 640 /*
 641  * Miscellaneous configurable options
 642  */
 643 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 644
 645 /*
 646  * For booting Linux, the board info and command line data
 647  * have to be in the first 64 MB of memory, since this is
 648  * the maximum mapped by the Linux kernel during initialization.
 649  */
 650 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 651 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 652
 653 #ifdef CONFIG_CMD_KGDB
 654 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 655 #endif
 656
 657 /*
 658  * Environment Configuration
 659  */
 660 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 661 #define CONFIG_BOOTFILE         "uImage"
 662 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 663 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 664 #define __USB_PHY_TYPE          utmi
 665
 666 #ifdef CONFIG_ARCH_T1024
 667 #define CONFIG_BOARDNAME t1024rdb
 668 #define BANK_INTLV cs0_cs1
 669 #else
 670 #define CONFIG_BOARDNAME t1023rdb
 671 #define BANK_INTLV  null
 672 #endif
 673
 674 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 675         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 676         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 677         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 678         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 679         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 680         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 681         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 682         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 683         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 684         "netdev=eth0\0"                                         \
 685         "tftpflash=tftpboot $loadaddr $uboot && "               \
 686         "protect off $ubootaddr +$filesize && "                 \
 687         "erase $ubootaddr +$filesize && "                       \
 688         "cp.b $loadaddr $ubootaddr $filesize && "               \
 689         "protect on $ubootaddr +$filesize && "                  \
 690         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 691         "consoledev=ttyS0\0"                                    \
 692         "ramdiskaddr=2000000\0"                                 \
 693         "fdtaddr=1e00000\0"                                     \
 694         "bdev=sda3\0"
 695
 696 #define CONFIG_LINUX                                    \
 697         "setenv bootargs root=/dev/ram rw "             \
 698         "console=$consoledev,$baudrate $othbootargs;"   \
 699         "setenv ramdiskaddr 0x02000000;"                \
 700         "setenv fdtaddr 0x00c00000;"                    \
 701         "setenv loadaddr 0x1000000;"                    \
 702         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 703
 704 #define CONFIG_NFSBOOTCOMMAND                   \
 705         "setenv bootargs root=/dev/nfs rw "     \
 706         "nfsroot=$serverip:$rootpath "          \
 707         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 708         "console=$consoledev,$baudrate $othbootargs;"   \
 709         "tftp $loadaddr $bootfile;"             \
 710         "tftp $fdtaddr $fdtfile;"               \
 711         "bootm $loadaddr - $fdtaddr"
 712
 713 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 714
 715 #include <asm/fsl_secure_boot.h>
 716
 717 #endif  /* __T1024RDB_H */