1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 * T1024/T1023 RDB board configuration file
13 /* High Level Configuration Options */
14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
15 #define CONFIG_ENABLE_36BIT_PHYS
17 #ifdef CONFIG_PHYS_64BIT
18 #define CONFIG_ADDR_MAP 1
19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
25 #define CONFIG_ENV_OVERWRITE
27 /* support deep sleep */
28 #ifdef CONFIG_ARCH_T1024
29 #define CONFIG_DEEP_SLEEP
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
40 #ifdef CONFIG_SPL_BUILD
41 #define CONFIG_SPL_SKIP_RELOCATE
42 #define CONFIG_SPL_COMMON_INIT_DDR
43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
52 #if defined(CONFIG_TARGET_T1024RDB)
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
54 #elif defined(CONFIG_TARGET_T1023RDB)
55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
57 #define CONFIG_SPL_NAND_BOOT
60 #ifdef CONFIG_SPIFLASH
61 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
62 #define CONFIG_SPL_SPI_FLASH_MINIMAL
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68 #ifndef CONFIG_SPL_BUILD
69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
71 #if defined(CONFIG_TARGET_T1024RDB)
72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
73 #elif defined(CONFIG_TARGET_T1023RDB)
74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
76 #define CONFIG_SPL_SPI_BOOT
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
81 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
84 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
86 #ifndef CONFIG_SPL_BUILD
87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
89 #if defined(CONFIG_TARGET_T1024RDB)
90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
91 #elif defined(CONFIG_TARGET_T1023RDB)
92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
94 #define CONFIG_SPL_MMC_BOOT
97 #endif /* CONFIG_RAMBOOT_PBL */
99 #ifndef CONFIG_RESET_VECTOR_ADDRESS
100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
103 #ifdef CONFIG_MTD_NOR_FLASH
104 #define CONFIG_FLASH_CFI_DRIVER
105 #define CONFIG_SYS_FLASH_CFI
106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
109 /* PCIe Boot - Master */
110 #define CONFIG_SRIO_PCIE_BOOT_MASTER
112 * for slave u-boot IMAGE instored in master memory space,
113 * PHYS must be aligned based on the SIZE
115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
117 #ifdef CONFIG_PHYS_64BIT
118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
125 * for slave UCODE and ENV instored in master memory space,
126 * PHYS must be aligned based on the SIZE
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
136 /* slave core release by master*/
137 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
138 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
140 /* PCIe Boot - Slave */
141 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
142 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
143 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
144 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
145 /* Set 1M boot space for PCIe boot */
146 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
147 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
148 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
149 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
152 #if defined(CONFIG_SPIFLASH)
153 #define CONFIG_SYS_EXTRA_ENV_RELOC
154 #define CONFIG_ENV_SPI_BUS 0
155 #define CONFIG_ENV_SPI_CS 0
156 #define CONFIG_ENV_SPI_MAX_HZ 10000000
157 #define CONFIG_ENV_SPI_MODE 0
158 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
159 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
160 #if defined(CONFIG_TARGET_T1024RDB)
161 #define CONFIG_ENV_SECT_SIZE 0x10000
162 #elif defined(CONFIG_TARGET_T1023RDB)
163 #define CONFIG_ENV_SECT_SIZE 0x40000
165 #elif defined(CONFIG_SDCARD)
166 #define CONFIG_SYS_EXTRA_ENV_RELOC
167 #define CONFIG_SYS_MMC_ENV_DEV 0
168 #define CONFIG_ENV_SIZE 0x2000
169 #define CONFIG_ENV_OFFSET (512 * 0x800)
170 #elif defined(CONFIG_NAND)
171 #define CONFIG_SYS_EXTRA_ENV_RELOC
172 #define CONFIG_ENV_SIZE 0x2000
173 #if defined(CONFIG_TARGET_T1024RDB)
174 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
175 #elif defined(CONFIG_TARGET_T1023RDB)
176 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
178 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
179 #define CONFIG_ENV_ADDR 0xffe20000
180 #define CONFIG_ENV_SIZE 0x2000
181 #elif defined(CONFIG_ENV_IS_NOWHERE)
182 #define CONFIG_ENV_SIZE 0x2000
184 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
185 #define CONFIG_ENV_SIZE 0x2000
186 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
190 unsigned long get_board_sys_clk(void);
191 unsigned long get_board_ddr_clk(void);
194 #define CONFIG_SYS_CLK_FREQ 100000000
195 #define CONFIG_DDR_CLK_FREQ 100000000
198 * These can be toggled for performance analysis, otherwise use default.
200 #define CONFIG_SYS_CACHE_STASHING
201 #define CONFIG_BACKSIDE_L2_CACHE
202 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
203 #define CONFIG_BTB /* toggle branch predition */
204 #define CONFIG_DDR_ECC
205 #ifdef CONFIG_DDR_ECC
206 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
207 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
210 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
211 #define CONFIG_SYS_MEMTEST_END 0x00400000
214 * Config the L3 Cache as L3 SRAM
216 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
217 #define CONFIG_SYS_L3_SIZE (256 << 10)
218 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
219 #ifdef CONFIG_RAMBOOT_PBL
220 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
222 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
223 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
224 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
226 #ifdef CONFIG_PHYS_64BIT
227 #define CONFIG_SYS_DCSRBAR 0xf0000000
228 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
232 #define CONFIG_ID_EEPROM
233 #define CONFIG_SYS_I2C_EEPROM_NXID
234 #define CONFIG_SYS_EEPROM_BUS_NUM 0
235 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
236 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
243 #define CONFIG_VERY_BIG_RAM
244 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
245 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
246 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
247 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
248 #define CONFIG_FSL_DDR_INTERACTIVE
249 #if defined(CONFIG_TARGET_T1024RDB)
250 #define CONFIG_DDR_SPD
251 #define CONFIG_SYS_SPD_BUS_NUM 0
252 #define SPD_EEPROM_ADDRESS 0x51
253 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
254 #elif defined(CONFIG_TARGET_T1023RDB)
255 #define CONFIG_SYS_DDR_RAW_TIMING
256 #define CONFIG_SYS_SDRAM_SIZE 2048
262 #define CONFIG_SYS_FLASH_BASE 0xe8000000
263 #ifdef CONFIG_PHYS_64BIT
264 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
266 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
269 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
270 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
271 CSPR_PORT_SIZE_16 | \
274 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
276 /* NOR Flash Timing Params */
277 #if defined(CONFIG_TARGET_T1024RDB)
278 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
279 #elif defined(CONFIG_TARGET_T1023RDB)
280 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
281 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
283 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
284 FTIM0_NOR_TEADC(0x5) | \
285 FTIM0_NOR_TEAHC(0x5))
286 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
287 FTIM1_NOR_TRAD_NOR(0x1A) |\
288 FTIM1_NOR_TSEQRAD_NOR(0x13))
289 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
290 FTIM2_NOR_TCH(0x4) | \
291 FTIM2_NOR_TWPH(0x0E) | \
293 #define CONFIG_SYS_NOR_FTIM3 0x0
295 #define CONFIG_SYS_FLASH_QUIET_TEST
296 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
298 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
299 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
300 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
301 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
303 #define CONFIG_SYS_FLASH_EMPTY_INFO
304 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
306 #ifdef CONFIG_TARGET_T1024RDB
308 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
309 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
310 #define CONFIG_SYS_CSPR2_EXT (0xf)
311 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
315 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
316 #define CONFIG_SYS_CSOR2 0x0
318 /* CPLD Timing parameters for IFC CS2 */
319 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
320 FTIM0_GPCM_TEADC(0x0e) | \
321 FTIM0_GPCM_TEAHC(0x0e))
322 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
323 FTIM1_GPCM_TRAD(0x1f))
324 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
325 FTIM2_GPCM_TCH(0x8) | \
326 FTIM2_GPCM_TWP(0x1f))
327 #define CONFIG_SYS_CS2_FTIM3 0x0
330 /* NAND Flash on IFC */
331 #define CONFIG_NAND_FSL_IFC
332 #define CONFIG_SYS_NAND_BASE 0xff800000
333 #ifdef CONFIG_PHYS_64BIT
334 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
336 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
338 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
339 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
340 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
341 | CSPR_MSEL_NAND /* MSEL = NAND */ \
343 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
345 #if defined(CONFIG_TARGET_T1024RDB)
346 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
347 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
348 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
349 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
350 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
351 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
352 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
353 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
354 #elif defined(CONFIG_TARGET_T1023RDB)
355 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
356 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
357 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
358 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
359 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
360 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
361 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
362 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
365 #define CONFIG_SYS_NAND_ONFI_DETECTION
366 /* ONFI NAND Flash mode0 Timing Params */
367 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
368 FTIM0_NAND_TWP(0x18) | \
369 FTIM0_NAND_TWCHT(0x07) | \
370 FTIM0_NAND_TWH(0x0a))
371 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
372 FTIM1_NAND_TWBE(0x39) | \
373 FTIM1_NAND_TRR(0x0e) | \
374 FTIM1_NAND_TRP(0x18))
375 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
376 FTIM2_NAND_TREH(0x0a) | \
377 FTIM2_NAND_TWHRE(0x1e))
378 #define CONFIG_SYS_NAND_FTIM3 0x0
380 #define CONFIG_SYS_NAND_DDR_LAW 11
381 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
382 #define CONFIG_SYS_MAX_NAND_DEVICE 1
384 #if defined(CONFIG_NAND)
385 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
386 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
387 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
388 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
389 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
390 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
391 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
392 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
393 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
394 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
395 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
396 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
397 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
398 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
399 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
400 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
402 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
403 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
404 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
405 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
406 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
407 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
408 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
409 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
410 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
411 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
412 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
413 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
414 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
415 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
416 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
417 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
420 #ifdef CONFIG_SPL_BUILD
421 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
426 #if defined(CONFIG_RAMBOOT_PBL)
427 #define CONFIG_SYS_RAMBOOT
430 #define CONFIG_MISC_INIT_R
432 #define CONFIG_HWCONFIG
434 /* define to use L1 as initial stack */
435 #define CONFIG_L1_INIT_RAM
436 #define CONFIG_SYS_INIT_RAM_LOCK
437 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
441 /* The assembler doesn't like typecast */
442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
443 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
444 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
450 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
452 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
453 GENERATED_GBL_DATA_SIZE)
454 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
456 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
457 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
460 #define CONFIG_SYS_NS16550_SERIAL
461 #define CONFIG_SYS_NS16550_REG_SIZE 1
462 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
464 #define CONFIG_SYS_BAUDRATE_TABLE \
465 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
467 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
468 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
469 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
470 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
473 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
474 #ifdef CONFIG_FSL_DIU_FB
475 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
476 #define CONFIG_VIDEO_LOGO
477 #define CONFIG_VIDEO_BMP_LOGO
478 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
480 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
481 * disable empty flash sector detection, which is I/O-intensive.
483 #undef CONFIG_SYS_FLASH_EMPTY_INFO
487 #define CONFIG_SYS_I2C
488 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
489 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
490 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
491 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
492 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
493 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
494 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
496 #define I2C_PCA6408_BUS_NUM 1
497 #define I2C_PCA6408_ADDR 0x20
499 /* I2C bus multiplexer */
500 #define I2C_MUX_CH_DEFAULT 0x8
506 #define CONFIG_RTC_DS1337 1
507 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
510 * eSPI - Enhanced SPI
512 #define CONFIG_SPI_FLASH_BAR
513 #define CONFIG_SF_DEFAULT_SPEED 10000000
514 #define CONFIG_SF_DEFAULT_MODE 0
518 * Memory space is mapped 1-1, but I/O space must start from 0.
520 #define CONFIG_PCIE1 /* PCIE controller 1 */
521 #define CONFIG_PCIE2 /* PCIE controller 2 */
522 #define CONFIG_PCIE3 /* PCIE controller 3 */
523 #ifdef CONFIG_ARCH_T1040
524 #define CONFIG_PCIE4 /* PCIE controller 4 */
526 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
527 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
528 #define CONFIG_PCI_INDIRECT_BRIDGE
531 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
533 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
534 #ifdef CONFIG_PHYS_64BIT
535 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
536 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
538 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
539 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
541 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
542 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
543 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
544 #ifdef CONFIG_PHYS_64BIT
545 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
547 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
549 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
552 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
554 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
555 #ifdef CONFIG_PHYS_64BIT
556 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
557 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
559 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
560 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
562 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
563 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
564 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
565 #ifdef CONFIG_PHYS_64BIT
566 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
568 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
570 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
573 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
575 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
576 #ifdef CONFIG_PHYS_64BIT
577 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
578 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
580 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
581 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
583 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
584 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
585 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
586 #ifdef CONFIG_PHYS_64BIT
587 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
589 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
591 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
594 /* controller 4, Base address 203000, to be removed */
596 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
597 #ifdef CONFIG_PHYS_64BIT
598 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
599 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
601 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
602 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
604 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
605 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
606 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
607 #ifdef CONFIG_PHYS_64BIT
608 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
610 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
612 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
615 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
616 #endif /* CONFIG_PCI */
621 #define CONFIG_HAS_FSL_DR_USB
623 #ifdef CONFIG_HAS_FSL_DR_USB
624 #define CONFIG_USB_EHCI_FSL
625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
632 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
636 #ifndef CONFIG_NOBQFMAN
637 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
638 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
639 #ifdef CONFIG_PHYS_64BIT
640 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
642 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
644 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
645 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
646 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
647 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
648 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
649 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
650 CONFIG_SYS_BMAN_CENA_SIZE)
651 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
652 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
653 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
654 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
655 #ifdef CONFIG_PHYS_64BIT
656 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
658 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
660 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
661 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
662 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
663 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
664 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
665 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
666 CONFIG_SYS_QMAN_CENA_SIZE)
667 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
668 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
670 #define CONFIG_SYS_DPAA_FMAN
672 #ifdef CONFIG_TARGET_T1024RDB
676 /* Default address of microcode for the Linux FMan driver */
677 #if defined(CONFIG_SPIFLASH)
679 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
680 * env, so we got 0x110000.
682 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
683 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
684 #define CONFIG_SYS_QE_FW_ADDR 0x130000
685 #elif defined(CONFIG_SDCARD)
687 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
688 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
689 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
691 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
692 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
693 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
694 #elif defined(CONFIG_NAND)
695 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
696 #if defined(CONFIG_TARGET_T1024RDB)
697 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
698 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
699 #elif defined(CONFIG_TARGET_T1023RDB)
700 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
701 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
703 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
705 * Slave has no ucode locally, it can fetch this from remote. When implementing
706 * in two corenet boards, slave's ucode could be stored in master's memory
707 * space, the address can be mapped from slave TLB->slave LAW->
708 * slave SRIO or PCIE outbound window->master inbound window->
709 * master LAW->the ucode address in master's memory space.
711 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
712 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
714 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
715 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
716 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
718 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
719 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
720 #endif /* CONFIG_NOBQFMAN */
722 #ifdef CONFIG_SYS_DPAA_FMAN
723 #define CONFIG_FMAN_ENET
724 #define CONFIG_PHYLIB_10G
725 #define CONFIG_PHY_REALTEK
726 #define CONFIG_PHY_AQUANTIA
727 #if defined(CONFIG_TARGET_T1024RDB)
728 #define RGMII_PHY1_ADDR 0x2
729 #define RGMII_PHY2_ADDR 0x6
730 #define SGMII_AQR_PHY_ADDR 0x2
731 #define FM1_10GEC1_PHY_ADDR 0x1
732 #elif defined(CONFIG_TARGET_T1023RDB)
733 #define RGMII_PHY1_ADDR 0x1
734 #define SGMII_RTK_PHY_ADDR 0x3
735 #define SGMII_AQR_PHY_ADDR 0x2
739 #ifdef CONFIG_FMAN_ENET
740 #define CONFIG_MII /* MII PHY management */
741 #define CONFIG_ETHPRIME "FM1@DTSEC4"
745 * Dynamic MTD Partition support with mtdparts
747 #ifdef CONFIG_MTD_NOR_FLASH
748 #define CONFIG_FLASH_CFI_MTD
754 #define CONFIG_LOADS_ECHO /* echo on for serial download */
755 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
758 * Miscellaneous configurable options
760 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
763 * For booting Linux, the board info and command line data
764 * have to be in the first 64 MB of memory, since this is
765 * the maximum mapped by the Linux kernel during initialization.
767 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
768 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
770 #ifdef CONFIG_CMD_KGDB
771 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
775 * Environment Configuration
777 #define CONFIG_ROOTPATH "/opt/nfsroot"
778 #define CONFIG_BOOTFILE "uImage"
779 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
780 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
781 #define __USB_PHY_TYPE utmi
783 #ifdef CONFIG_ARCH_T1024
784 #define CONFIG_BOARDNAME t1024rdb
785 #define BANK_INTLV cs0_cs1
787 #define CONFIG_BOARDNAME t1023rdb
788 #define BANK_INTLV null
791 #define CONFIG_EXTRA_ENV_SETTINGS \
792 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
793 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
794 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
795 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
796 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
797 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
798 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
799 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
800 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
802 "tftpflash=tftpboot $loadaddr $uboot && " \
803 "protect off $ubootaddr +$filesize && " \
804 "erase $ubootaddr +$filesize && " \
805 "cp.b $loadaddr $ubootaddr $filesize && " \
806 "protect on $ubootaddr +$filesize && " \
807 "cmp.b $loadaddr $ubootaddr $filesize\0" \
808 "consoledev=ttyS0\0" \
809 "ramdiskaddr=2000000\0" \
810 "fdtaddr=1e00000\0" \
813 #define CONFIG_LINUX \
814 "setenv bootargs root=/dev/ram rw " \
815 "console=$consoledev,$baudrate $othbootargs;" \
816 "setenv ramdiskaddr 0x02000000;" \
817 "setenv fdtaddr 0x00c00000;" \
818 "setenv loadaddr 0x1000000;" \
819 "bootm $loadaddr $ramdiskaddr $fdtaddr"
821 #define CONFIG_NFSBOOTCOMMAND \
822 "setenv bootargs root=/dev/nfs rw " \
823 "nfsroot=$serverip:$rootpath " \
824 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
825 "console=$consoledev,$baudrate $othbootargs;" \
826 "tftp $loadaddr $bootfile;" \
827 "tftp $fdtaddr $fdtfile;" \
828 "bootm $loadaddr - $fdtaddr"
830 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
832 #include <asm/fsl_secure_boot.h>
834 #endif /* __T1024RDB_H */