include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 /* support deep sleep */
  24 #ifdef CONFIG_ARCH_T1024
  25 #define CONFIG_DEEP_SLEEP
  26 #endif
  27
  28 #ifdef CONFIG_RAMBOOT_PBL
  29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  30 #define CONFIG_SPL_FLUSH_IMAGE
  31 #define CONFIG_SPL_PAD_TO               0x40000
  32 #define CONFIG_SPL_MAX_SIZE             0x28000
  33 #define RESET_VECTOR_OFFSET             0x27FFC
  34 #define BOOT_PAGE_OFFSET                0x27000
  35 #ifdef CONFIG_SPL_BUILD
  36 #define CONFIG_SPL_SKIP_RELOCATE
  37 #define CONFIG_SPL_COMMON_INIT_DDR
  38 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  39 #endif
  40
  41 #ifdef CONFIG_MTD_RAW_NAND
  42 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  43 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  44 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  45 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  46 #if defined(CONFIG_TARGET_T1024RDB)
  47 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  48 #elif defined(CONFIG_TARGET_T1023RDB)
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  50 #endif
  51 #endif
  52
  53 #ifdef CONFIG_SPIFLASH
  54 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  55 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  60 #ifndef CONFIG_SPL_BUILD
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #endif
  63 #if defined(CONFIG_TARGET_T1024RDB)
  64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  65 #elif defined(CONFIG_TARGET_T1023RDB)
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  67 #endif
  68 #endif
  69
  70 #ifdef CONFIG_SDCARD
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  72 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  73 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  74 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  75 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #if defined(CONFIG_TARGET_T1024RDB)
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  81 #elif defined(CONFIG_TARGET_T1023RDB)
  82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  83 #endif
  84 #endif
  85
  86 #endif /* CONFIG_RAMBOOT_PBL */
  87
  88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  89 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  90 #endif
  91
  92 /* PCIe Boot - Master */
  93 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  94 /*
  95  * for slave u-boot IMAGE instored in master memory space,
  96  * PHYS must be aligned based on the SIZE
  97  */
  98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  99 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 103 #else
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 106 #endif
 107 /*
 108  * for slave UCODE and ENV instored in master memory space,
 109  * PHYS must be aligned based on the SIZE
 110  */
 111 #ifdef CONFIG_PHYS_64BIT
 112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 113 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 114 #else
 115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 117 #endif
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 119 /* slave core release by master*/
 120 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 121 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 122
 123 /* PCIe Boot - Slave */
 124 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 126 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 127                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 128 /* Set 1M boot space for PCIe boot */
 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 131                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 132 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 133 #endif
 134
 135 #ifndef __ASSEMBLY__
 136 unsigned long get_board_sys_clk(void);
 137 unsigned long get_board_ddr_clk(void);
 138 #endif
 139
 140 #define CONFIG_SYS_CLK_FREQ     100000000
 141 #define CONFIG_DDR_CLK_FREQ     100000000
 142
 143 /*
 144  * These can be toggled for performance analysis, otherwise use default.
 145  */
 146 #define CONFIG_SYS_CACHE_STASHING
 147 #define CONFIG_BACKSIDE_L2_CACHE
 148 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 149 #define CONFIG_BTB                      /* toggle branch predition */
 150 #define CONFIG_DDR_ECC
 151 #ifdef CONFIG_DDR_ECC
 152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 153 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 154 #endif
 155
 156 /*
 157  *  Config the L3 Cache as L3 SRAM
 158  */
 159 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 160 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 161 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 162 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 163 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 164 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 165 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 166
 167 #ifdef CONFIG_PHYS_64BIT
 168 #define CONFIG_SYS_DCSRBAR              0xf0000000
 169 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 170 #endif
 171
 172 /* EEPROM */
 173 #define CONFIG_ID_EEPROM
 174 #define CONFIG_SYS_I2C_EEPROM_NXID
 175 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 176 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 177 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 179 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 180
 181 /*
 182  * DDR Setup
 183  */
 184 #define CONFIG_VERY_BIG_RAM
 185 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 186 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 187 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 188 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 189 #if defined(CONFIG_TARGET_T1024RDB)
 190 #define CONFIG_DDR_SPD
 191 #define CONFIG_SYS_SPD_BUS_NUM  0
 192 #define SPD_EEPROM_ADDRESS      0x51
 193 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 194 #elif defined(CONFIG_TARGET_T1023RDB)
 195 #define CONFIG_SYS_DDR_RAW_TIMING
 196 #define CONFIG_SYS_SDRAM_SIZE   2048
 197 #endif
 198
 199 /*
 200  * IFC Definitions
 201  */
 202 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 203 #ifdef CONFIG_PHYS_64BIT
 204 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 205 #else
 206 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 207 #endif
 208
 209 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 210 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 211                                 CSPR_PORT_SIZE_16 | \
 212                                 CSPR_MSEL_NOR | \
 213                                 CSPR_V)
 214 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 215
 216 /* NOR Flash Timing Params */
 217 #if defined(CONFIG_TARGET_T1024RDB)
 218 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 219 #elif defined(CONFIG_TARGET_T1023RDB)
 220 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 221                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 222 #endif
 223 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 224                                 FTIM0_NOR_TEADC(0x5) | \
 225                                 FTIM0_NOR_TEAHC(0x5))
 226 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 227                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 228                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 229 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 230                                 FTIM2_NOR_TCH(0x4) | \
 231                                 FTIM2_NOR_TWPH(0x0E) | \
 232                                 FTIM2_NOR_TWP(0x1c))
 233 #define CONFIG_SYS_NOR_FTIM3    0x0
 234
 235 #define CONFIG_SYS_FLASH_QUIET_TEST
 236 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 237
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 239 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 240 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 241 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 242
 243 #define CONFIG_SYS_FLASH_EMPTY_INFO
 244 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 245
 246 #ifdef CONFIG_TARGET_T1024RDB
 247 /* CPLD on IFC */
 248 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 249 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 250 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 251 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 252                                                 | CSPR_PORT_SIZE_8 \
 253                                                 | CSPR_MSEL_GPCM \
 254                                                 | CSPR_V)
 255 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 256 #define CONFIG_SYS_CSOR2                0x0
 257
 258 /* CPLD Timing parameters for IFC CS2 */
 259 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 260                                                 FTIM0_GPCM_TEADC(0x0e) | \
 261                                                 FTIM0_GPCM_TEAHC(0x0e))
 262 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 263                                                 FTIM1_GPCM_TRAD(0x1f))
 264 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 265                                                 FTIM2_GPCM_TCH(0x8) | \
 266                                                 FTIM2_GPCM_TWP(0x1f))
 267 #define CONFIG_SYS_CS2_FTIM3            0x0
 268 #endif
 269
 270 /* NAND Flash on IFC */
 271 #define CONFIG_NAND_FSL_IFC
 272 #define CONFIG_SYS_NAND_BASE            0xff800000
 273 #ifdef CONFIG_PHYS_64BIT
 274 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 275 #else
 276 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 277 #endif
 278 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 279 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 280                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 281                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 282                                 | CSPR_V)
 283 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 284
 285 #if defined(CONFIG_TARGET_T1024RDB)
 286 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 287                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 288                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 289                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 290                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 291                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 292                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 293 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 294 #elif defined(CONFIG_TARGET_T1023RDB)
 295 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 296                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 297                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 298                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 299                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 300                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 301                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 302 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 303 #endif
 304
 305 #define CONFIG_SYS_NAND_ONFI_DETECTION
 306 /* ONFI NAND Flash mode0 Timing Params */
 307 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 308                                         FTIM0_NAND_TWP(0x18)   | \
 309                                         FTIM0_NAND_TWCHT(0x07) | \
 310                                         FTIM0_NAND_TWH(0x0a))
 311 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 312                                         FTIM1_NAND_TWBE(0x39)  | \
 313                                         FTIM1_NAND_TRR(0x0e)   | \
 314                                         FTIM1_NAND_TRP(0x18))
 315 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 316                                         FTIM2_NAND_TREH(0x0a) | \
 317                                         FTIM2_NAND_TWHRE(0x1e))
 318 #define CONFIG_SYS_NAND_FTIM3           0x0
 319
 320 #define CONFIG_SYS_NAND_DDR_LAW         11
 321 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 322 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 323
 324 #if defined(CONFIG_MTD_RAW_NAND)
 325 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 326 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 327 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 328 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 329 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 330 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 331 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 332 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 333 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 334 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 335 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 336 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 337 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 338 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 339 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 340 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 341 #else
 342 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 343 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 344 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 345 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 346 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 347 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 348 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 349 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 350 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 351 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 352 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 353 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 354 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 355 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 356 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 357 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 358 #endif
 359
 360 #ifdef CONFIG_SPL_BUILD
 361 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 362 #else
 363 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 364 #endif
 365
 366 #if defined(CONFIG_RAMBOOT_PBL)
 367 #define CONFIG_SYS_RAMBOOT
 368 #endif
 369
 370 #define CONFIG_HWCONFIG
 371
 372 /* define to use L1 as initial stack */
 373 #define CONFIG_L1_INIT_RAM
 374 #define CONFIG_SYS_INIT_RAM_LOCK
 375 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 376 #ifdef CONFIG_PHYS_64BIT
 377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 379 /* The assembler doesn't like typecast */
 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 381         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 382           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 383 #else
 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 387 #endif
 388 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 389
 390 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 391                                         GENERATED_GBL_DATA_SIZE)
 392 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 393
 394 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 395 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 396
 397 /* Serial Port */
 398 #define CONFIG_SYS_NS16550_SERIAL
 399 #define CONFIG_SYS_NS16550_REG_SIZE     1
 400 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 401
 402 #define CONFIG_SYS_BAUDRATE_TABLE       \
 403         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 404
 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 409
 410 /* Video */
 411 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 412 #ifdef CONFIG_FSL_DIU_FB
 413 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 414 #define CONFIG_VIDEO_LOGO
 415 #define CONFIG_VIDEO_BMP_LOGO
 416 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 417 /*
 418  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 419  * disable empty flash sector detection, which is I/O-intensive.
 420  */
 421 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 422 #endif
 423
 424 /* I2C */
 425 #ifndef CONFIG_DM_I2C
 426 #define CONFIG_SYS_I2C
 427 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 428 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 429 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 430 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 431 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 432 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 433 #else
 434 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 435 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 436 #endif
 437
 438 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 439 #define I2C_PCA6408_BUS_NUM             1
 440 #define I2C_PCA6408_ADDR                0x20
 441
 442 /* I2C bus multiplexer */
 443 #define I2C_MUX_CH_DEFAULT      0x8
 444
 445 /*
 446  * RTC configuration
 447  */
 448 #define RTC
 449 #define CONFIG_RTC_DS1337       1
 450 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 451
 452 /*
 453  * eSPI - Enhanced SPI
 454  */
 455
 456 /*
 457  * General PCIe
 458  * Memory space is mapped 1-1, but I/O space must start from 0.
 459  */
 460 #define CONFIG_PCIE1            /* PCIE controller 1 */
 461 #define CONFIG_PCIE2            /* PCIE controller 2 */
 462 #define CONFIG_PCIE3            /* PCIE controller 3 */
 463 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 464
 465 #ifdef CONFIG_PCI
 466 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 467 #ifdef CONFIG_PCIE1
 468 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 469 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 470 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 471 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 472 #endif
 473
 474 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 475 #ifdef CONFIG_PCIE2
 476 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 477 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 478 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 479 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 480 #endif
 481
 482 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 483 #ifdef CONFIG_PCIE3
 484 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 485 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 486 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 487 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 488 #endif
 489
 490 #if !defined(CONFIG_DM_PCI)
 491 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 492 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 493 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 494 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 495 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 496 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 497 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 498 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 499 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 500 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 501 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 502 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 503 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 504 #define CONFIG_PCI_INDIRECT_BRIDGE
 505 #endif
 506
 507 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 508 #endif  /* CONFIG_PCI */
 509
 510 /*
 511  * USB
 512  */
 513 #define CONFIG_HAS_FSL_DR_USB
 514
 515 #ifdef CONFIG_HAS_FSL_DR_USB
 516 #define CONFIG_USB_EHCI_FSL
 517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 518 #endif
 519
 520 /*
 521  * SDHC
 522  */
 523 #ifdef CONFIG_MMC
 524 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 525 #endif
 526
 527 /* Qman/Bman */
 528 #ifndef CONFIG_NOBQFMAN
 529 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 530 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 533 #else
 534 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 535 #endif
 536 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 537 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 538 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 539 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 540 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 541 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 542                                         CONFIG_SYS_BMAN_CENA_SIZE)
 543 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 544 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 545 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 546 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 547 #ifdef CONFIG_PHYS_64BIT
 548 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 549 #else
 550 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 551 #endif
 552 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 553 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 554 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 555 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 556 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 557 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 558                                         CONFIG_SYS_QMAN_CENA_SIZE)
 559 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 560 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 561
 562 #define CONFIG_SYS_DPAA_FMAN
 563
 564 /* Default address of microcode for the Linux FMan driver */
 565 #if defined(CONFIG_SPIFLASH)
 566 /*
 567  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 568  * env, so we got 0x110000.
 569  */
 570 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 571 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 572 #elif defined(CONFIG_SDCARD)
 573 /*
 574  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 575  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 576  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 577  */
 578 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 579 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 580 #elif defined(CONFIG_MTD_RAW_NAND)
 581 #if defined(CONFIG_TARGET_T1024RDB)
 582 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 583 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 584 #elif defined(CONFIG_TARGET_T1023RDB)
 585 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 586 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 587 #endif
 588 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 589 /*
 590  * Slave has no ucode locally, it can fetch this from remote. When implementing
 591  * in two corenet boards, slave's ucode could be stored in master's memory
 592  * space, the address can be mapped from slave TLB->slave LAW->
 593  * slave SRIO or PCIE outbound window->master inbound window->
 594  * master LAW->the ucode address in master's memory space.
 595  */
 596 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 597 #else
 598 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 599 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 600 #endif
 601 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 602 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 603 #endif /* CONFIG_NOBQFMAN */
 604
 605 #ifdef CONFIG_SYS_DPAA_FMAN
 606 #if defined(CONFIG_TARGET_T1024RDB)
 607 #define RGMII_PHY1_ADDR         0x2
 608 #define RGMII_PHY2_ADDR         0x6
 609 #define SGMII_AQR_PHY_ADDR      0x2
 610 #define FM1_10GEC1_PHY_ADDR     0x1
 611 #elif defined(CONFIG_TARGET_T1023RDB)
 612 #define RGMII_PHY1_ADDR         0x1
 613 #define SGMII_RTK_PHY_ADDR      0x3
 614 #define SGMII_AQR_PHY_ADDR      0x2
 615 #endif
 616 #endif
 617
 618 #ifdef CONFIG_FMAN_ENET
 619 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 620 #endif
 621
 622 /*
 623  * Dynamic MTD Partition support with mtdparts
 624  */
 625
 626 /*
 627  * Environment
 628  */
 629 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 630 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 631
 632 /*
 633  * Miscellaneous configurable options
 634  */
 635 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 636
 637 /*
 638  * For booting Linux, the board info and command line data
 639  * have to be in the first 64 MB of memory, since this is
 640  * the maximum mapped by the Linux kernel during initialization.
 641  */
 642 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 643 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 644
 645 #ifdef CONFIG_CMD_KGDB
 646 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 647 #endif
 648
 649 /*
 650  * Environment Configuration
 651  */
 652 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 653 #define CONFIG_BOOTFILE         "uImage"
 654 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 655 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 656 #define __USB_PHY_TYPE          utmi
 657
 658 #ifdef CONFIG_ARCH_T1024
 659 #define CONFIG_BOARDNAME t1024rdb
 660 #define BANK_INTLV cs0_cs1
 661 #else
 662 #define CONFIG_BOARDNAME t1023rdb
 663 #define BANK_INTLV  null
 664 #endif
 665
 666 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 667         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 668         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 669         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 670         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 671         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 672         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 673         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 674         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 675         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 676         "netdev=eth0\0"                                         \
 677         "tftpflash=tftpboot $loadaddr $uboot && "               \
 678         "protect off $ubootaddr +$filesize && "                 \
 679         "erase $ubootaddr +$filesize && "                       \
 680         "cp.b $loadaddr $ubootaddr $filesize && "               \
 681         "protect on $ubootaddr +$filesize && "                  \
 682         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 683         "consoledev=ttyS0\0"                                    \
 684         "ramdiskaddr=2000000\0"                                 \
 685         "fdtaddr=1e00000\0"                                     \
 686         "bdev=sda3\0"
 687
 688 #define CONFIG_LINUX                                    \
 689         "setenv bootargs root=/dev/ram rw "             \
 690         "console=$consoledev,$baudrate $othbootargs;"   \
 691         "setenv ramdiskaddr 0x02000000;"                \
 692         "setenv fdtaddr 0x00c00000;"                    \
 693         "setenv loadaddr 0x1000000;"                    \
 694         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 695
 696 #define CONFIG_NFSBOOTCOMMAND                   \
 697         "setenv bootargs root=/dev/nfs rw "     \
 698         "nfsroot=$serverip:$rootpath "          \
 699         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 700         "console=$consoledev,$baudrate $othbootargs;"   \
 701         "tftp $loadaddr $bootfile;"             \
 702         "tftp $fdtaddr $fdtfile;"               \
 703         "bootm $loadaddr - $fdtaddr"
 704
 705 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 706
 707 #include <asm/fsl_secure_boot.h>
 708
 709 #endif  /* __T1024RDB_H */