Merge branch 'master' of git://git.denx.de/u-boot-spi
[platform/kernel/u-boot.git] / include / configs / T102xQDS.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T1024/T1023 QDS board configuration file
9  */
10
11 #ifndef __T1024QDS_H
12 #define __T1024QDS_H
13
14 /* High Level Configuration Options */
15 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_BOOKE
17 #define CONFIG_E500                     /* BOOKE e500 family */
18 #define CONFIG_E500MC                   /* BOOKE e500mc family */
19 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
20 #define CONFIG_MP                       /* support multiple processors */
21 #define CONFIG_PHYS_64BIT
22 #define CONFIG_ENABLE_36BIT_PHYS
23
24 #ifdef CONFIG_PHYS_64BIT
25 #define CONFIG_ADDR_MAP         1
26 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
27 #endif
28
29 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
30 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
31 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
32
33 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
34 #define CONFIG_ENV_OVERWRITE
35
36 #define CONFIG_DEEP_SLEEP
37 #if defined(CONFIG_DEEP_SLEEP)
38 #define CONFIG_SILENT_CONSOLE
39 #define CONFIG_BOARD_EARLY_INIT_F
40 #endif
41
42 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
43
44 #ifdef CONFIG_RAMBOOT_PBL
45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
46 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
48 #define CONFIG_SPL_ENV_SUPPORT
49 #define CONFIG_SPL_SERIAL_SUPPORT
50 #define CONFIG_SPL_FLUSH_IMAGE
51 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
52 #define CONFIG_SPL_LIBGENERIC_SUPPORT
53 #define CONFIG_SPL_LIBCOMMON_SUPPORT
54 #define CONFIG_SPL_I2C_SUPPORT
55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
56 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
57 #define CONFIG_SYS_TEXT_BASE            0x00201000
58 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
59 #define CONFIG_SPL_PAD_TO               0x40000
60 #define CONFIG_SPL_MAX_SIZE             0x28000
61 #define RESET_VECTOR_OFFSET             0x27FFC
62 #define BOOT_PAGE_OFFSET                0x27000
63 #ifdef CONFIG_SPL_BUILD
64 #define CONFIG_SPL_SKIP_RELOCATE
65 #define CONFIG_SPL_COMMON_INIT_DDR
66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
67 #define CONFIG_SYS_NO_FLASH
68 #endif
69
70 #ifdef CONFIG_NAND
71 #define CONFIG_SPL_NAND_SUPPORT
72 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
73 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
74 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
75 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
76 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
77 #define CONFIG_SPL_NAND_BOOT
78 #endif
79
80 #ifdef CONFIG_SPIFLASH
81 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
82 #define CONFIG_SPL_SPI_SUPPORT
83 #define CONFIG_SPL_SPI_FLASH_SUPPORT
84 #define CONFIG_SPL_SPI_FLASH_MINIMAL
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
89 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90 #ifndef CONFIG_SPL_BUILD
91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
92 #endif
93 #define CONFIG_SPL_SPI_BOOT
94 #endif
95
96 #ifdef CONFIG_SDCARD
97 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
98 #define CONFIG_SPL_MMC_SUPPORT
99 #define CONFIG_SPL_MMC_MINIMAL
100 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
101 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
102 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
103 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
104 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
105 #ifndef CONFIG_SPL_BUILD
106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
107 #endif
108 #define CONFIG_SPL_MMC_BOOT
109 #endif
110
111 #endif /* CONFIG_RAMBOOT_PBL */
112
113 #ifndef CONFIG_SYS_TEXT_BASE
114 #define CONFIG_SYS_TEXT_BASE    0xeff40000
115 #endif
116
117 #ifndef CONFIG_RESET_VECTOR_ADDRESS
118 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
119 #endif
120
121 #ifndef CONFIG_SYS_NO_FLASH
122 #define CONFIG_FLASH_CFI_DRIVER
123 #define CONFIG_SYS_FLASH_CFI
124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
125 #endif
126
127 /* PCIe Boot - Master */
128 #define CONFIG_SRIO_PCIE_BOOT_MASTER
129 /*
130  * for slave u-boot IMAGE instored in master memory space,
131  * PHYS must be aligned based on the SIZE
132  */
133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
135 #ifdef CONFIG_PHYS_64BIT
136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
138 #else
139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
141 #endif
142 /*
143  * for slave UCODE and ENV instored in master memory space,
144  * PHYS must be aligned based on the SIZE
145  */
146 #ifdef CONFIG_PHYS_64BIT
147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
149 #else
150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
152 #endif
153 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
154 /* slave core release by master*/
155 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
156 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
157
158 /* PCIe Boot - Slave */
159 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
160 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
161 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
162                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
163 /* Set 1M boot space for PCIe boot */
164 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
165 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
166                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
167 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
168 #define CONFIG_SYS_NO_FLASH
169 #endif
170
171 #if defined(CONFIG_SPIFLASH)
172 #define CONFIG_SYS_EXTRA_ENV_RELOC
173 #define CONFIG_ENV_IS_IN_SPI_FLASH
174 #define CONFIG_ENV_SPI_BUS              0
175 #define CONFIG_ENV_SPI_CS               0
176 #define CONFIG_ENV_SPI_MAX_HZ           10000000
177 #define CONFIG_ENV_SPI_MODE             0
178 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
179 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
180 #define CONFIG_ENV_SECT_SIZE            0x10000
181 #elif defined(CONFIG_SDCARD)
182 #define CONFIG_SYS_EXTRA_ENV_RELOC
183 #define CONFIG_ENV_IS_IN_MMC
184 #define CONFIG_SYS_MMC_ENV_DEV          0
185 #define CONFIG_ENV_SIZE                 0x2000
186 #define CONFIG_ENV_OFFSET               (512 * 0x800)
187 #elif defined(CONFIG_NAND)
188 #define CONFIG_SYS_EXTRA_ENV_RELOC
189 #define CONFIG_ENV_IS_IN_NAND
190 #define CONFIG_ENV_SIZE                 0x2000
191 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
192 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
193 #define CONFIG_ENV_IS_IN_REMOTE
194 #define CONFIG_ENV_ADDR         0xffe20000
195 #define CONFIG_ENV_SIZE         0x2000
196 #elif defined(CONFIG_ENV_IS_NOWHERE)
197 #define CONFIG_ENV_SIZE         0x2000
198 #else
199 #define CONFIG_ENV_IS_IN_FLASH
200 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
201 #define CONFIG_ENV_SIZE         0x2000
202 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
203 #endif
204
205
206 #ifndef __ASSEMBLY__
207 unsigned long get_board_sys_clk(void);
208 unsigned long get_board_ddr_clk(void);
209 #endif
210
211 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
212 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
213
214 /*
215  * These can be toggled for performance analysis, otherwise use default.
216  */
217 #define CONFIG_SYS_CACHE_STASHING
218 #define CONFIG_BACKSIDE_L2_CACHE
219 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
220 #define CONFIG_BTB                      /* toggle branch predition */
221 #define CONFIG_DDR_ECC
222 #ifdef CONFIG_DDR_ECC
223 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
224 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
225 #endif
226
227 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
228 #define CONFIG_SYS_MEMTEST_END          0x00400000
229 #define CONFIG_SYS_ALT_MEMTEST
230 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
231
232 /*
233  *  Config the L3 Cache as L3 SRAM
234  */
235 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
236 #define CONFIG_SYS_L3_SIZE              (256 << 10)
237 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
238 #ifdef CONFIG_RAMBOOT_PBL
239 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
240 #endif
241 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
242 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
243 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
244 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
245
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_DCSRBAR              0xf0000000
248 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
249 #endif
250
251 /* EEPROM */
252 #define CONFIG_ID_EEPROM
253 #define CONFIG_SYS_I2C_EEPROM_NXID
254 #define CONFIG_SYS_EEPROM_BUS_NUM       0
255 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
259
260 /*
261  * DDR Setup
262  */
263 #define CONFIG_VERY_BIG_RAM
264 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
265 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
266 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
267 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
268 #define CONFIG_DDR_SPD
269 #ifndef CONFIG_SYS_FSL_DDR4
270 #define CONFIG_SYS_FSL_DDR3
271 #endif
272
273 #define CONFIG_SYS_SPD_BUS_NUM  0
274 #define SPD_EEPROM_ADDRESS      0x51
275
276 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
277
278 /*
279  * IFC Definitions
280  */
281 #define CONFIG_SYS_FLASH_BASE   0xe0000000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
284 #else
285 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
286 #endif
287
288 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
289 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
290                                 + 0x8000000) | \
291                                 CSPR_PORT_SIZE_16 | \
292                                 CSPR_MSEL_NOR | \
293                                 CSPR_V)
294 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
295 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
296                                 CSPR_PORT_SIZE_16 | \
297                                 CSPR_MSEL_NOR | \
298                                 CSPR_V)
299 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
300 /* NOR Flash Timing Params */
301 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
302 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
303                                 FTIM0_NOR_TEADC(0x5) | \
304                                 FTIM0_NOR_TEAHC(0x5))
305 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
306                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
307                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
308 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
309                                 FTIM2_NOR_TCH(0x4) | \
310                                 FTIM2_NOR_TWPH(0x0E) | \
311                                 FTIM2_NOR_TWP(0x1c))
312 #define CONFIG_SYS_NOR_FTIM3    0x0
313
314 #define CONFIG_SYS_FLASH_QUIET_TEST
315 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
316
317 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
318 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
319 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
320 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
321
322 #define CONFIG_SYS_FLASH_EMPTY_INFO
323 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
324                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
325 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
326 #define QIXIS_BASE              0xffdf0000
327 #ifdef CONFIG_PHYS_64BIT
328 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
329 #else
330 #define QIXIS_BASE_PHYS         QIXIS_BASE
331 #endif
332 #define QIXIS_LBMAP_SWITCH              0x06
333 #define QIXIS_LBMAP_MASK                0x0f
334 #define QIXIS_LBMAP_SHIFT               0
335 #define QIXIS_LBMAP_DFLTBANK            0x00
336 #define QIXIS_LBMAP_ALTBANK             0x04
337 #define QIXIS_RST_CTL_RESET             0x31
338 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
339 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
340 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
341 #define QIXIS_RST_FORCE_MEM             0x01
342
343 #define CONFIG_SYS_CSPR3_EXT    (0xf)
344 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
345                                 | CSPR_PORT_SIZE_8 \
346                                 | CSPR_MSEL_GPCM \
347                                 | CSPR_V)
348 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
349 #define CONFIG_SYS_CSOR3        0x0
350 /* QIXIS Timing parameters for IFC CS3 */
351 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
352                                         FTIM0_GPCM_TEADC(0x0e) | \
353                                         FTIM0_GPCM_TEAHC(0x0e))
354 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
355                                         FTIM1_GPCM_TRAD(0x3f))
356 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
357                                         FTIM2_GPCM_TCH(0x8) | \
358                                         FTIM2_GPCM_TWP(0x1f))
359 #define CONFIG_SYS_CS3_FTIM3            0x0
360
361 #define CONFIG_NAND_FSL_IFC
362 #define CONFIG_SYS_NAND_BASE            0xff800000
363 #ifdef CONFIG_PHYS_64BIT
364 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
365 #else
366 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
367 #endif
368 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
369 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
370                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
371                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
372                                 | CSPR_V)
373 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
374
375 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
376                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
377                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
378                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
379                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
380                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
381                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
382
383 #define CONFIG_SYS_NAND_ONFI_DETECTION
384
385 /* ONFI NAND Flash mode0 Timing Params */
386 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
387                                         FTIM0_NAND_TWP(0x18)   | \
388                                         FTIM0_NAND_TWCHT(0x07) | \
389                                         FTIM0_NAND_TWH(0x0a))
390 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
391                                         FTIM1_NAND_TWBE(0x39)  | \
392                                         FTIM1_NAND_TRR(0x0e)   | \
393                                         FTIM1_NAND_TRP(0x18))
394 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
395                                         FTIM2_NAND_TREH(0x0a) | \
396                                         FTIM2_NAND_TWHRE(0x1e))
397 #define CONFIG_SYS_NAND_FTIM3           0x0
398
399 #define CONFIG_SYS_NAND_DDR_LAW         11
400 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
401 #define CONFIG_SYS_MAX_NAND_DEVICE      1
402 #define CONFIG_CMD_NAND
403
404 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
405
406 #if defined(CONFIG_NAND)
407 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
408 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
409 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
410 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
411 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
412 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
413 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
414 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
415 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
416 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
417 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
418 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
419 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
420 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
421 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
422 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
423 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
424 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
425 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
426 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
427 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
428 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
429 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
430 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
431 #else
432 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
433 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
434 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
435 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
436 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
437 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
438 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
439 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
440 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
441 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
442 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
443 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
444 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
445 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
446 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
447 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
448 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
449 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
450 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
451 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
452 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
453 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
454 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
455 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
456 #endif
457
458 #ifdef CONFIG_SPL_BUILD
459 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
460 #else
461 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
462 #endif
463
464 #if defined(CONFIG_RAMBOOT_PBL)
465 #define CONFIG_SYS_RAMBOOT
466 #endif
467
468 #define CONFIG_BOARD_EARLY_INIT_R
469 #define CONFIG_MISC_INIT_R
470
471 #define CONFIG_HWCONFIG
472
473 /* define to use L1 as initial stack */
474 #define CONFIG_L1_INIT_RAM
475 #define CONFIG_SYS_INIT_RAM_LOCK
476 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
477 #ifdef CONFIG_PHYS_64BIT
478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
480 /* The assembler doesn't like typecast */
481 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
482         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
483           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
484 #else
485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
488 #endif
489 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
490
491 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
492                                         GENERATED_GBL_DATA_SIZE)
493 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
494
495 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
496 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
497
498 /* Serial Port */
499 #define CONFIG_CONS_INDEX       1
500 #define CONFIG_SYS_NS16550_SERIAL
501 #define CONFIG_SYS_NS16550_REG_SIZE     1
502 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
503
504 #define CONFIG_SYS_BAUDRATE_TABLE       \
505         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
506
507 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
508 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
509 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
510 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
511 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
512
513 /* Use the HUSH parser */
514 #define CONFIG_SYS_HUSH_PARSER
515 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
516
517 /* Video */
518 #ifdef CONFIG_PPC_T1024         /* no DIU on T1023 */
519 #define CONFIG_FSL_DIU_FB
520 #ifdef CONFIG_FSL_DIU_FB
521 #define CONFIG_FSL_DIU_CH7301
522 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
523 #define CONFIG_VIDEO
524 #define CONFIG_CMD_BMP
525 #define CONFIG_CFB_CONSOLE
526 #define CONFIG_VIDEO_SW_CURSOR
527 #define CONFIG_VGA_AS_SINGLE_DEVICE
528 #define CONFIG_VIDEO_LOGO
529 #define CONFIG_VIDEO_BMP_LOGO
530 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
531 /*
532  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
533  * disable empty flash sector detection, which is I/O-intensive.
534  */
535 #undef CONFIG_SYS_FLASH_EMPTY_INFO
536 #endif
537 #endif
538
539 /* I2C */
540 #define CONFIG_SYS_I2C
541 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
542 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
543 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
544 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
545 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
546 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
547 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
548
549 #define I2C_MUX_PCA_ADDR                0x77
550 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
551 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
552 #define I2C_RETIMER_ADDR                0x18
553
554 /* I2C bus multiplexer */
555 #define I2C_MUX_CH_DEFAULT      0x8
556 #define I2C_MUX_CH_DIU          0xC
557 #define I2C_MUX_CH5             0xD
558 #define I2C_MUX_CH7             0xF
559
560 /* LDI/DVI Encoder for display */
561 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
562 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
563
564 /*
565  * RTC configuration
566  */
567 #define RTC
568 #define CONFIG_RTC_DS3231       1
569 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
570
571 /*
572  * eSPI - Enhanced SPI
573  */
574 #ifndef CONFIG_SPL_BUILD
575 #endif
576 #define CONFIG_CMD_SF
577 #define CONFIG_SPI_FLASH_BAR
578 #define CONFIG_SF_DEFAULT_SPEED  10000000
579 #define CONFIG_SF_DEFAULT_MODE    0
580
581 /*
582  * General PCIe
583  * Memory space is mapped 1-1, but I/O space must start from 0.
584  */
585 #define CONFIG_PCI              /* Enable PCI/PCIE */
586 #define CONFIG_PCIE1            /* PCIE controler 1 */
587 #define CONFIG_PCIE2            /* PCIE controler 2 */
588 #define CONFIG_PCIE3            /* PCIE controler 3 */
589 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
590 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
591 #define CONFIG_PCI_INDIRECT_BRIDGE
592
593 #ifdef CONFIG_PCI
594 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
595 #ifdef CONFIG_PCIE1
596 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
597 #ifdef CONFIG_PHYS_64BIT
598 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
599 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
600 #else
601 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
602 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
603 #endif
604 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
605 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
606 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
607 #ifdef CONFIG_PHYS_64BIT
608 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
609 #else
610 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
611 #endif
612 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
613 #endif
614
615 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
616 #ifdef CONFIG_PCIE2
617 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
618 #ifdef CONFIG_PHYS_64BIT
619 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
620 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
621 #else
622 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
623 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
624 #endif
625 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
626 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
627 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
628 #ifdef CONFIG_PHYS_64BIT
629 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
630 #else
631 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
632 #endif
633 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
634 #endif
635
636 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
637 #ifdef CONFIG_PCIE3
638 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
639 #ifdef CONFIG_PHYS_64BIT
640 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
641 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
642 #else
643 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
644 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
645 #endif
646 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
647 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
648 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
649 #ifdef CONFIG_PHYS_64BIT
650 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
651 #else
652 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
653 #endif
654 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
655 #endif
656
657 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
658 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
659 #define CONFIG_DOS_PARTITION
660 #endif  /* CONFIG_PCI */
661
662 /*
663  *SATA
664  */
665 #define CONFIG_FSL_SATA_V2
666 #ifdef CONFIG_FSL_SATA_V2
667 #define CONFIG_LIBATA
668 #define CONFIG_FSL_SATA
669 #define CONFIG_SYS_SATA_MAX_DEVICE      1
670 #define CONFIG_SATA1
671 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
672 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
673 #define CONFIG_LBA48
674 #define CONFIG_CMD_SATA
675 #define CONFIG_DOS_PARTITION
676 #define CONFIG_CMD_EXT2
677 #endif
678
679 /*
680  * USB
681  */
682 #define CONFIG_HAS_FSL_DR_USB
683
684 #ifdef CONFIG_HAS_FSL_DR_USB
685 #define CONFIG_USB_EHCI
686 #define CONFIG_CMD_USB
687 #define CONFIG_USB_STORAGE
688 #define CONFIG_USB_EHCI_FSL
689 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
690 #define CONFIG_CMD_EXT2
691 #endif
692
693 /*
694  * SDHC
695  */
696 #define CONFIG_MMC
697 #ifdef CONFIG_MMC
698 #define CONFIG_FSL_ESDHC
699 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
700 #define CONFIG_CMD_MMC
701 #define CONFIG_GENERIC_MMC
702 #define CONFIG_CMD_EXT2
703 #define CONFIG_CMD_FAT
704 #define CONFIG_DOS_PARTITION
705 #endif
706
707 /* Qman/Bman */
708 #ifndef CONFIG_NOBQFMAN
709 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
710 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
711 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
712 #ifdef CONFIG_PHYS_64BIT
713 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
714 #else
715 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
716 #endif
717 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
718 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
719 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
720 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
721 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
722 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
723                                         CONFIG_SYS_BMAN_CENA_SIZE)
724 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
725 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
726 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
727 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
728 #ifdef CONFIG_PHYS_64BIT
729 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
730 #else
731 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
732 #endif
733 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
734 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
735 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
736 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
737 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
738 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
739                                         CONFIG_SYS_QMAN_CENA_SIZE)
740 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
741 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
742
743 #define CONFIG_SYS_DPAA_FMAN
744
745 #define CONFIG_QE
746 #define CONFIG_U_QE
747 /* Default address of microcode for the Linux FMan driver */
748 #if defined(CONFIG_SPIFLASH)
749 /*
750  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
751  * env, so we got 0x110000.
752  */
753 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
754 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
755 #define CONFIG_SYS_QE_FW_ADDR   0x130000
756 #elif defined(CONFIG_SDCARD)
757 /*
758  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
759  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
760  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
761  */
762 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
763 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
764 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
765 #elif defined(CONFIG_NAND)
766 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
767 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
768 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
769 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
770 /*
771  * Slave has no ucode locally, it can fetch this from remote. When implementing
772  * in two corenet boards, slave's ucode could be stored in master's memory
773  * space, the address can be mapped from slave TLB->slave LAW->
774  * slave SRIO or PCIE outbound window->master inbound window->
775  * master LAW->the ucode address in master's memory space.
776  */
777 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
778 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
779 #else
780 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
781 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
782 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
783 #endif
784 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
785 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
786 #endif /* CONFIG_NOBQFMAN */
787
788 #ifdef CONFIG_SYS_DPAA_FMAN
789 #define CONFIG_FMAN_ENET
790 #define CONFIG_PHYLIB_10G
791 #define CONFIG_PHY_VITESSE
792 #define CONFIG_PHY_REALTEK
793 #define CONFIG_PHY_TERANETICS
794 #define RGMII_PHY1_ADDR         0x1
795 #define RGMII_PHY2_ADDR         0x2
796 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
797 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
798 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
799 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
800 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
801 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
802 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
803 #endif
804
805 #ifdef CONFIG_FMAN_ENET
806 #define CONFIG_MII              /* MII PHY management */
807 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
808 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
809 #endif
810
811 /*
812  * Dynamic MTD Partition support with mtdparts
813  */
814 #ifndef CONFIG_SYS_NO_FLASH
815 #define CONFIG_MTD_DEVICE
816 #define CONFIG_MTD_PARTITIONS
817 #define CONFIG_CMD_MTDPARTS
818 #define CONFIG_FLASH_CFI_MTD
819 #define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
820                           "spi0=spife110000.0"
821 #define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
822                           "128k(dtb),96m(fs),-(user);"\
823                           "fff800000.flash:2m(uboot),9m(kernel),"\
824                           "128k(dtb),96m(fs),-(user);spife110000.0:" \
825                           "2m(uboot),9m(kernel),128k(dtb),-(user)"
826 #endif
827
828 /*
829  * Environment
830  */
831 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
832 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
833
834 /*
835  * Command line configuration.
836  */
837 #define CONFIG_CMD_DATE
838 #define CONFIG_CMD_DHCP
839 #define CONFIG_CMD_EEPROM
840 #define CONFIG_CMD_ERRATA
841 #define CONFIG_CMD_GREPENV
842 #define CONFIG_CMD_IRQ
843 #define CONFIG_CMD_I2C
844 #define CONFIG_CMD_MII
845 #define CONFIG_CMD_PING
846 #define CONFIG_CMD_REGINFO
847
848 #ifdef CONFIG_PCI
849 #define CONFIG_CMD_PCI
850 #endif
851
852 /*
853  * Miscellaneous configurable options
854  */
855 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
856 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
857 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
858 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
859 #ifdef CONFIG_CMD_KGDB
860 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
861 #else
862 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
863 #endif
864 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
865 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
866 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
867
868 /*
869  * For booting Linux, the board info and command line data
870  * have to be in the first 64 MB of memory, since this is
871  * the maximum mapped by the Linux kernel during initialization.
872  */
873 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
874 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
875
876 #ifdef CONFIG_CMD_KGDB
877 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
878 #endif
879
880 /*
881  * Environment Configuration
882  */
883 #define CONFIG_ROOTPATH         "/opt/nfsroot"
884 #define CONFIG_BOOTFILE         "uImage"
885 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
886 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
887 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
888 #define CONFIG_BAUDRATE         115200
889 #define __USB_PHY_TYPE          utmi
890
891
892 #define CONFIG_EXTRA_ENV_SETTINGS                               \
893         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
894         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
895         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
896         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
897         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
898         "netdev=eth0\0"                                         \
899         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
900         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
901         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
902         "tftpflash=tftpboot $loadaddr $uboot && "               \
903         "protect off $ubootaddr +$filesize && "                 \
904         "erase $ubootaddr +$filesize && "                       \
905         "cp.b $loadaddr $ubootaddr $filesize && "               \
906         "protect on $ubootaddr +$filesize && "                  \
907         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
908         "consoledev=ttyS0\0"                                    \
909         "ramdiskaddr=2000000\0"                                 \
910         "fdtaddr=d00000\0"                                      \
911         "bdev=sda3\0"
912
913 #define CONFIG_LINUX                                    \
914         "setenv bootargs root=/dev/ram rw "             \
915         "console=$consoledev,$baudrate $othbootargs;"   \
916         "setenv ramdiskaddr 0x02000000;"                \
917         "setenv fdtaddr 0x00c00000;"                    \
918         "setenv loadaddr 0x1000000;"                    \
919         "bootm $loadaddr $ramdiskaddr $fdtaddr"
920
921 #define CONFIG_NFSBOOTCOMMAND                   \
922         "setenv bootargs root=/dev/nfs rw "     \
923         "nfsroot=$serverip:$rootpath "          \
924         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
925         "console=$consoledev,$baudrate $othbootargs;"   \
926         "tftp $loadaddr $bootfile;"             \
927         "tftp $fdtaddr $fdtfile;"               \
928         "bootm $loadaddr - $fdtaddr"
929
930 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
931
932 /* Hash command with SHA acceleration supported in hardware */
933 #ifdef CONFIG_FSL_CAAM
934 #define CONFIG_CMD_HASH
935 #define CONFIG_SHA_HW_ACCEL
936 #endif
937
938 #include <asm/fsl_secure_boot.h>
939
940 #endif  /* __T1024QDS_H */