include/configs/T102xQDS.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_DISPLAY_BOARDINFO
  16 #define CONFIG_BOOKE
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  19 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  20 #define CONFIG_MP                       /* support multiple processors */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #ifdef CONFIG_PHYS_64BIT
  24 #define CONFIG_ADDR_MAP         1
  25 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  26 #endif
  27
  28 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  30 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  31
  32 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  33 #define CONFIG_ENV_OVERWRITE
  34
  35 #define CONFIG_DEEP_SLEEP
  36 #if defined(CONFIG_DEEP_SLEEP)
  37 #define CONFIG_SILENT_CONSOLE
  38 #define CONFIG_BOARD_EARLY_INIT_F
  39 #endif
  40
  41 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  42
  43 #ifdef CONFIG_RAMBOOT_PBL
  44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
  46 #define CONFIG_SPL_FLUSH_IMAGE
  47 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  48 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  49 #define CONFIG_SYS_TEXT_BASE            0x00201000
  50 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  51 #define CONFIG_SPL_PAD_TO               0x40000
  52 #define CONFIG_SPL_MAX_SIZE             0x28000
  53 #define RESET_VECTOR_OFFSET             0x27FFC
  54 #define BOOT_PAGE_OFFSET                0x27000
  55 #ifdef CONFIG_SPL_BUILD
  56 #define CONFIG_SPL_SKIP_RELOCATE
  57 #define CONFIG_SPL_COMMON_INIT_DDR
  58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  59 #define CONFIG_SYS_NO_FLASH
  60 #endif
  61
  62 #ifdef CONFIG_NAND
  63 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  64 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  65 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  66 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  67 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  68 #define CONFIG_SPL_NAND_BOOT
  69 #endif
  70
  71 #ifdef CONFIG_SPIFLASH
  72 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  73 #define CONFIG_SPL_SPI_SUPPORT
  74 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  75 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  80 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #define CONFIG_SPL_SPI_BOOT
  85 #endif
  86
  87 #ifdef CONFIG_SDCARD
  88 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  89 #define CONFIG_SPL_MMC_MINIMAL
  90 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  91 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  92 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  93 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  94 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  95 #ifndef CONFIG_SPL_BUILD
  96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  97 #endif
  98 #define CONFIG_SPL_MMC_BOOT
  99 #endif
 100
 101 #endif /* CONFIG_RAMBOOT_PBL */
 102
 103 #ifndef CONFIG_SYS_TEXT_BASE
 104 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 105 #endif
 106
 107 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 108 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 109 #endif
 110
 111 #ifndef CONFIG_SYS_NO_FLASH
 112 #define CONFIG_FLASH_CFI_DRIVER
 113 #define CONFIG_SYS_FLASH_CFI
 114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 115 #endif
 116
 117 /* PCIe Boot - Master */
 118 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 119 /*
 120  * for slave u-boot IMAGE instored in master memory space,
 121  * PHYS must be aligned based on the SIZE
 122  */
 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 125 #ifdef CONFIG_PHYS_64BIT
 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 128 #else
 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 131 #endif
 132 /*
 133  * for slave UCODE and ENV instored in master memory space,
 134  * PHYS must be aligned based on the SIZE
 135  */
 136 #ifdef CONFIG_PHYS_64BIT
 137 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 139 #else
 140 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 142 #endif
 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 144 /* slave core release by master*/
 145 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 146 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 147
 148 /* PCIe Boot - Slave */
 149 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 152                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 153 /* Set 1M boot space for PCIe boot */
 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 156                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 157 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 158 #define CONFIG_SYS_NO_FLASH
 159 #endif
 160
 161 #if defined(CONFIG_SPIFLASH)
 162 #define CONFIG_SYS_EXTRA_ENV_RELOC
 163 #define CONFIG_ENV_IS_IN_SPI_FLASH
 164 #define CONFIG_ENV_SPI_BUS              0
 165 #define CONFIG_ENV_SPI_CS               0
 166 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 167 #define CONFIG_ENV_SPI_MODE             0
 168 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 169 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 170 #define CONFIG_ENV_SECT_SIZE            0x10000
 171 #elif defined(CONFIG_SDCARD)
 172 #define CONFIG_SYS_EXTRA_ENV_RELOC
 173 #define CONFIG_ENV_IS_IN_MMC
 174 #define CONFIG_SYS_MMC_ENV_DEV          0
 175 #define CONFIG_ENV_SIZE                 0x2000
 176 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 177 #elif defined(CONFIG_NAND)
 178 #define CONFIG_SYS_EXTRA_ENV_RELOC
 179 #define CONFIG_ENV_IS_IN_NAND
 180 #define CONFIG_ENV_SIZE                 0x2000
 181 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 182 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 183 #define CONFIG_ENV_IS_IN_REMOTE
 184 #define CONFIG_ENV_ADDR         0xffe20000
 185 #define CONFIG_ENV_SIZE         0x2000
 186 #elif defined(CONFIG_ENV_IS_NOWHERE)
 187 #define CONFIG_ENV_SIZE         0x2000
 188 #else
 189 #define CONFIG_ENV_IS_IN_FLASH
 190 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 191 #define CONFIG_ENV_SIZE         0x2000
 192 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 193 #endif
 194
 195 #ifndef __ASSEMBLY__
 196 unsigned long get_board_sys_clk(void);
 197 unsigned long get_board_ddr_clk(void);
 198 #endif
 199
 200 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 201 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 202
 203 /*
 204  * These can be toggled for performance analysis, otherwise use default.
 205  */
 206 #define CONFIG_SYS_CACHE_STASHING
 207 #define CONFIG_BACKSIDE_L2_CACHE
 208 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 209 #define CONFIG_BTB                      /* toggle branch predition */
 210 #define CONFIG_DDR_ECC
 211 #ifdef CONFIG_DDR_ECC
 212 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 213 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 214 #endif
 215
 216 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 217 #define CONFIG_SYS_MEMTEST_END          0x00400000
 218 #define CONFIG_SYS_ALT_MEMTEST
 219 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 220
 221 /*
 222  *  Config the L3 Cache as L3 SRAM
 223  */
 224 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 225 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 226 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 227 #ifdef CONFIG_RAMBOOT_PBL
 228 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 229 #endif
 230 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 231 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 232 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 233 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 234
 235 #ifdef CONFIG_PHYS_64BIT
 236 #define CONFIG_SYS_DCSRBAR              0xf0000000
 237 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 238 #endif
 239
 240 /* EEPROM */
 241 #define CONFIG_ID_EEPROM
 242 #define CONFIG_SYS_I2C_EEPROM_NXID
 243 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 244 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 248
 249 /*
 250  * DDR Setup
 251  */
 252 #define CONFIG_VERY_BIG_RAM
 253 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 254 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 255 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 256 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 257 #define CONFIG_DDR_SPD
 258 #ifndef CONFIG_SYS_FSL_DDR4
 259 #define CONFIG_SYS_FSL_DDR3
 260 #endif
 261
 262 #define CONFIG_SYS_SPD_BUS_NUM  0
 263 #define SPD_EEPROM_ADDRESS      0x51
 264
 265 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 266
 267 /*
 268  * IFC Definitions
 269  */
 270 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 271 #ifdef CONFIG_PHYS_64BIT
 272 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 273 #else
 274 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 275 #endif
 276
 277 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 278 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 279                                 + 0x8000000) | \
 280                                 CSPR_PORT_SIZE_16 | \
 281                                 CSPR_MSEL_NOR | \
 282                                 CSPR_V)
 283 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 284 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 285                                 CSPR_PORT_SIZE_16 | \
 286                                 CSPR_MSEL_NOR | \
 287                                 CSPR_V)
 288 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 289 /* NOR Flash Timing Params */
 290 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 291 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 292                                 FTIM0_NOR_TEADC(0x5) | \
 293                                 FTIM0_NOR_TEAHC(0x5))
 294 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 295                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 296                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 297 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 298                                 FTIM2_NOR_TCH(0x4) | \
 299                                 FTIM2_NOR_TWPH(0x0E) | \
 300                                 FTIM2_NOR_TWP(0x1c))
 301 #define CONFIG_SYS_NOR_FTIM3    0x0
 302
 303 #define CONFIG_SYS_FLASH_QUIET_TEST
 304 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 305
 306 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 307 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 308 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 309 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 310
 311 #define CONFIG_SYS_FLASH_EMPTY_INFO
 312 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 313                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 314 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 315 #define QIXIS_BASE              0xffdf0000
 316 #ifdef CONFIG_PHYS_64BIT
 317 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 318 #else
 319 #define QIXIS_BASE_PHYS         QIXIS_BASE
 320 #endif
 321 #define QIXIS_LBMAP_SWITCH              0x06
 322 #define QIXIS_LBMAP_MASK                0x0f
 323 #define QIXIS_LBMAP_SHIFT               0
 324 #define QIXIS_LBMAP_DFLTBANK            0x00
 325 #define QIXIS_LBMAP_ALTBANK             0x04
 326 #define QIXIS_RST_CTL_RESET             0x31
 327 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 328 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 329 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 330 #define QIXIS_RST_FORCE_MEM             0x01
 331
 332 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 333 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 334                                 | CSPR_PORT_SIZE_8 \
 335                                 | CSPR_MSEL_GPCM \
 336                                 | CSPR_V)
 337 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 338 #define CONFIG_SYS_CSOR3        0x0
 339 /* QIXIS Timing parameters for IFC CS3 */
 340 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 341                                         FTIM0_GPCM_TEADC(0x0e) | \
 342                                         FTIM0_GPCM_TEAHC(0x0e))
 343 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 344                                         FTIM1_GPCM_TRAD(0x3f))
 345 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 346                                         FTIM2_GPCM_TCH(0x8) | \
 347                                         FTIM2_GPCM_TWP(0x1f))
 348 #define CONFIG_SYS_CS3_FTIM3            0x0
 349
 350 #define CONFIG_NAND_FSL_IFC
 351 #define CONFIG_SYS_NAND_BASE            0xff800000
 352 #ifdef CONFIG_PHYS_64BIT
 353 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 354 #else
 355 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 356 #endif
 357 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 358 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 359                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 360                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 361                                 | CSPR_V)
 362 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 363
 364 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 365                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 366                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 367                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 368                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 369                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 370                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 371
 372 #define CONFIG_SYS_NAND_ONFI_DETECTION
 373
 374 /* ONFI NAND Flash mode0 Timing Params */
 375 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 376                                         FTIM0_NAND_TWP(0x18)   | \
 377                                         FTIM0_NAND_TWCHT(0x07) | \
 378                                         FTIM0_NAND_TWH(0x0a))
 379 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 380                                         FTIM1_NAND_TWBE(0x39)  | \
 381                                         FTIM1_NAND_TRR(0x0e)   | \
 382                                         FTIM1_NAND_TRP(0x18))
 383 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 384                                         FTIM2_NAND_TREH(0x0a) | \
 385                                         FTIM2_NAND_TWHRE(0x1e))
 386 #define CONFIG_SYS_NAND_FTIM3           0x0
 387
 388 #define CONFIG_SYS_NAND_DDR_LAW         11
 389 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 390 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 391 #define CONFIG_CMD_NAND
 392
 393 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 394
 395 #if defined(CONFIG_NAND)
 396 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 397 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 398 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 399 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 400 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 401 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 402 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 403 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 404 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 405 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 406 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 407 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 408 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 409 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 410 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 411 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 412 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 413 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 414 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 415 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 416 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 417 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 418 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 419 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 420 #else
 421 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 422 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 423 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 424 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 425 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 426 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 427 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 428 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 429 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 430 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 431 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 432 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 433 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 434 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 435 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 436 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 437 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 438 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 439 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 440 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 441 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 442 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 443 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 444 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 445 #endif
 446
 447 #ifdef CONFIG_SPL_BUILD
 448 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 449 #else
 450 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 451 #endif
 452
 453 #if defined(CONFIG_RAMBOOT_PBL)
 454 #define CONFIG_SYS_RAMBOOT
 455 #endif
 456
 457 #define CONFIG_BOARD_EARLY_INIT_R
 458 #define CONFIG_MISC_INIT_R
 459
 460 #define CONFIG_HWCONFIG
 461
 462 /* define to use L1 as initial stack */
 463 #define CONFIG_L1_INIT_RAM
 464 #define CONFIG_SYS_INIT_RAM_LOCK
 465 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 466 #ifdef CONFIG_PHYS_64BIT
 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 469 /* The assembler doesn't like typecast */
 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 471         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 472           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 473 #else
 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 477 #endif
 478 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 479
 480 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 481                                         GENERATED_GBL_DATA_SIZE)
 482 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 483
 484 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 485 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 486
 487 /* Serial Port */
 488 #define CONFIG_CONS_INDEX       1
 489 #define CONFIG_SYS_NS16550_SERIAL
 490 #define CONFIG_SYS_NS16550_REG_SIZE     1
 491 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 492
 493 #define CONFIG_SYS_BAUDRATE_TABLE       \
 494         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 495
 496 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 497 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 498 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 499 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 500 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 501
 502 /* Video */
 503 #ifdef CONFIG_PPC_T1024         /* no DIU on T1023 */
 504 #define CONFIG_FSL_DIU_FB
 505 #ifdef CONFIG_FSL_DIU_FB
 506 #define CONFIG_FSL_DIU_CH7301
 507 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 508 #define CONFIG_VIDEO
 509 #define CONFIG_CMD_BMP
 510 #define CONFIG_CFB_CONSOLE
 511 #define CONFIG_VIDEO_SW_CURSOR
 512 #define CONFIG_VGA_AS_SINGLE_DEVICE
 513 #define CONFIG_VIDEO_LOGO
 514 #define CONFIG_VIDEO_BMP_LOGO
 515 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 516 /*
 517  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 518  * disable empty flash sector detection, which is I/O-intensive.
 519  */
 520 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 521 #endif
 522 #endif
 523
 524 /* I2C */
 525 #define CONFIG_SYS_I2C
 526 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 527 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 528 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 529 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 530 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 531 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 532 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 533
 534 #define I2C_MUX_PCA_ADDR                0x77
 535 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 536 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 537 #define I2C_RETIMER_ADDR                0x18
 538
 539 /* I2C bus multiplexer */
 540 #define I2C_MUX_CH_DEFAULT      0x8
 541 #define I2C_MUX_CH_DIU          0xC
 542 #define I2C_MUX_CH5             0xD
 543 #define I2C_MUX_CH7             0xF
 544
 545 /* LDI/DVI Encoder for display */
 546 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 547 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 548
 549 /*
 550  * RTC configuration
 551  */
 552 #define RTC
 553 #define CONFIG_RTC_DS3231       1
 554 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 555
 556 /*
 557  * eSPI - Enhanced SPI
 558  */
 559 #ifndef CONFIG_SPL_BUILD
 560 #endif
 561 #define CONFIG_SPI_FLASH_BAR
 562 #define CONFIG_SF_DEFAULT_SPEED  10000000
 563 #define CONFIG_SF_DEFAULT_MODE    0
 564
 565 /*
 566  * General PCIe
 567  * Memory space is mapped 1-1, but I/O space must start from 0.
 568  */
 569 #define CONFIG_PCI              /* Enable PCI/PCIE */
 570 #define CONFIG_PCIE1            /* PCIE controller 1 */
 571 #define CONFIG_PCIE2            /* PCIE controller 2 */
 572 #define CONFIG_PCIE3            /* PCIE controller 3 */
 573 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 574 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 575 #define CONFIG_PCI_INDIRECT_BRIDGE
 576
 577 #ifdef CONFIG_PCI
 578 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 579 #ifdef CONFIG_PCIE1
 580 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 581 #ifdef CONFIG_PHYS_64BIT
 582 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 583 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 584 #else
 585 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 586 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 587 #endif
 588 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 589 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 590 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 591 #ifdef CONFIG_PHYS_64BIT
 592 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 593 #else
 594 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 595 #endif
 596 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 597 #endif
 598
 599 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 600 #ifdef CONFIG_PCIE2
 601 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 602 #ifdef CONFIG_PHYS_64BIT
 603 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 604 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 605 #else
 606 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 607 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 608 #endif
 609 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 610 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 611 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 612 #ifdef CONFIG_PHYS_64BIT
 613 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 614 #else
 615 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 616 #endif
 617 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 618 #endif
 619
 620 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 621 #ifdef CONFIG_PCIE3
 622 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 623 #ifdef CONFIG_PHYS_64BIT
 624 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 625 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 626 #else
 627 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 628 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 629 #endif
 630 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 631 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 632 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 633 #ifdef CONFIG_PHYS_64BIT
 634 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 635 #else
 636 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 637 #endif
 638 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 639 #endif
 640
 641 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 642 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 643 #define CONFIG_DOS_PARTITION
 644 #endif  /* CONFIG_PCI */
 645
 646 /*
 647  *SATA
 648  */
 649 #define CONFIG_FSL_SATA_V2
 650 #ifdef CONFIG_FSL_SATA_V2
 651 #define CONFIG_LIBATA
 652 #define CONFIG_FSL_SATA
 653 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 654 #define CONFIG_SATA1
 655 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 656 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 657 #define CONFIG_LBA48
 658 #define CONFIG_CMD_SATA
 659 #define CONFIG_DOS_PARTITION
 660 #endif
 661
 662 /*
 663  * USB
 664  */
 665 #define CONFIG_HAS_FSL_DR_USB
 666
 667 #ifdef CONFIG_HAS_FSL_DR_USB
 668 #define CONFIG_USB_EHCI
 669 #define CONFIG_USB_EHCI_FSL
 670 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 671 #endif
 672
 673 /*
 674  * SDHC
 675  */
 676 #define CONFIG_MMC
 677 #ifdef CONFIG_MMC
 678 #define CONFIG_FSL_ESDHC
 679 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 680 #define CONFIG_GENERIC_MMC
 681 #define CONFIG_DOS_PARTITION
 682 #endif
 683
 684 /* Qman/Bman */
 685 #ifndef CONFIG_NOBQFMAN
 686 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 687 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 688 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 689 #ifdef CONFIG_PHYS_64BIT
 690 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 691 #else
 692 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 693 #endif
 694 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 695 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 696 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 697 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 698 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 699 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 700                                         CONFIG_SYS_BMAN_CENA_SIZE)
 701 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 702 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 703 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 704 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 705 #ifdef CONFIG_PHYS_64BIT
 706 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 707 #else
 708 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 709 #endif
 710 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 711 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 712 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 713 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 714 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 715 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 716                                         CONFIG_SYS_QMAN_CENA_SIZE)
 717 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 718 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 719
 720 #define CONFIG_SYS_DPAA_FMAN
 721
 722 #define CONFIG_QE
 723 #define CONFIG_U_QE
 724 /* Default address of microcode for the Linux FMan driver */
 725 #if defined(CONFIG_SPIFLASH)
 726 /*
 727  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 728  * env, so we got 0x110000.
 729  */
 730 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 731 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 732 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 733 #elif defined(CONFIG_SDCARD)
 734 /*
 735  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 736  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 737  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 738  */
 739 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 740 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 741 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 742 #elif defined(CONFIG_NAND)
 743 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 744 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 745 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 746 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 747 /*
 748  * Slave has no ucode locally, it can fetch this from remote. When implementing
 749  * in two corenet boards, slave's ucode could be stored in master's memory
 750  * space, the address can be mapped from slave TLB->slave LAW->
 751  * slave SRIO or PCIE outbound window->master inbound window->
 752  * master LAW->the ucode address in master's memory space.
 753  */
 754 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 755 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 756 #else
 757 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 758 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 759 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 760 #endif
 761 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 762 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 763 #endif /* CONFIG_NOBQFMAN */
 764
 765 #ifdef CONFIG_SYS_DPAA_FMAN
 766 #define CONFIG_FMAN_ENET
 767 #define CONFIG_PHYLIB_10G
 768 #define CONFIG_PHY_VITESSE
 769 #define CONFIG_PHY_REALTEK
 770 #define CONFIG_PHY_TERANETICS
 771 #define RGMII_PHY1_ADDR         0x1
 772 #define RGMII_PHY2_ADDR         0x2
 773 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 774 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 775 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 776 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 777 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 778 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 779 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 780 #endif
 781
 782 #ifdef CONFIG_FMAN_ENET
 783 #define CONFIG_MII              /* MII PHY management */
 784 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 785 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 786 #endif
 787
 788 /*
 789  * Dynamic MTD Partition support with mtdparts
 790  */
 791 #ifndef CONFIG_SYS_NO_FLASH
 792 #define CONFIG_MTD_DEVICE
 793 #define CONFIG_MTD_PARTITIONS
 794 #define CONFIG_CMD_MTDPARTS
 795 #define CONFIG_FLASH_CFI_MTD
 796 #define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
 797                           "spi0=spife110000.0"
 798 #define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 799                           "128k(dtb),96m(fs),-(user);"\
 800                           "fff800000.flash:2m(uboot),9m(kernel),"\
 801                           "128k(dtb),96m(fs),-(user);spife110000.0:" \
 802                           "2m(uboot),9m(kernel),128k(dtb),-(user)"
 803 #endif
 804
 805 /*
 806  * Environment
 807  */
 808 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 809 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 810
 811 /*
 812  * Command line configuration.
 813  */
 814 #define CONFIG_CMD_DATE
 815 #define CONFIG_CMD_EEPROM
 816 #define CONFIG_CMD_ERRATA
 817 #define CONFIG_CMD_IRQ
 818 #define CONFIG_CMD_REGINFO
 819
 820 #ifdef CONFIG_PCI
 821 #define CONFIG_CMD_PCI
 822 #endif
 823
 824 /*
 825  * Miscellaneous configurable options
 826  */
 827 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 828 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 829 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 830 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 831 #ifdef CONFIG_CMD_KGDB
 832 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 833 #else
 834 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 835 #endif
 836 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 837 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 838 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 839
 840 /*
 841  * For booting Linux, the board info and command line data
 842  * have to be in the first 64 MB of memory, since this is
 843  * the maximum mapped by the Linux kernel during initialization.
 844  */
 845 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 846 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 847
 848 #ifdef CONFIG_CMD_KGDB
 849 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 850 #endif
 851
 852 /*
 853  * Environment Configuration
 854  */
 855 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 856 #define CONFIG_BOOTFILE         "uImage"
 857 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 858 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 859 #define CONFIG_BAUDRATE         115200
 860 #define __USB_PHY_TYPE          utmi
 861
 862 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 863         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 864         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 865         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 866         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 867         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 868         "netdev=eth0\0"                                         \
 869         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 870         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 871         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 872         "tftpflash=tftpboot $loadaddr $uboot && "               \
 873         "protect off $ubootaddr +$filesize && "                 \
 874         "erase $ubootaddr +$filesize && "                       \
 875         "cp.b $loadaddr $ubootaddr $filesize && "               \
 876         "protect on $ubootaddr +$filesize && "                  \
 877         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 878         "consoledev=ttyS0\0"                                    \
 879         "ramdiskaddr=2000000\0"                                 \
 880         "fdtaddr=d00000\0"                                      \
 881         "bdev=sda3\0"
 882
 883 #define CONFIG_LINUX                                    \
 884         "setenv bootargs root=/dev/ram rw "             \
 885         "console=$consoledev,$baudrate $othbootargs;"   \
 886         "setenv ramdiskaddr 0x02000000;"                \
 887         "setenv fdtaddr 0x00c00000;"                    \
 888         "setenv loadaddr 0x1000000;"                    \
 889         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 890
 891 #define CONFIG_NFSBOOTCOMMAND                   \
 892         "setenv bootargs root=/dev/nfs rw "     \
 893         "nfsroot=$serverip:$rootpath "          \
 894         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 895         "console=$consoledev,$baudrate $othbootargs;"   \
 896         "tftp $loadaddr $bootfile;"             \
 897         "tftp $fdtaddr $fdtfile;"               \
 898         "bootm $loadaddr - $fdtaddr"
 899
 900 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 901
 902 /* Hash command with SHA acceleration supported in hardware */
 903 #ifdef CONFIG_FSL_CAAM
 904 #define CONFIG_CMD_HASH
 905 #define CONFIG_SHA_HW_ACCEL
 906 #endif
 907
 908 #include <asm/fsl_secure_boot.h>
 909
 910 #endif  /* __T1024QDS_H */