include/configs/T102xQDS.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_DISPLAY_BOARDINFO
  16 #define CONFIG_BOOKE
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  19 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  20 #define CONFIG_MP                       /* support multiple processors */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #ifdef CONFIG_PHYS_64BIT
  24 #define CONFIG_ADDR_MAP         1
  25 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  26 #endif
  27
  28 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  30 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  31
  32 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  33 #define CONFIG_ENV_OVERWRITE
  34
  35 #define CONFIG_DEEP_SLEEP
  36 #if defined(CONFIG_DEEP_SLEEP)
  37 #define CONFIG_SILENT_CONSOLE
  38 #define CONFIG_BOARD_EARLY_INIT_F
  39 #endif
  40
  41 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  42
  43 #ifdef CONFIG_RAMBOOT_PBL
  44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
  46 #define CONFIG_SPL_SERIAL_SUPPORT
  47 #define CONFIG_SPL_FLUSH_IMAGE
  48 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  49 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  50 #define CONFIG_SYS_TEXT_BASE            0x00201000
  51 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  52 #define CONFIG_SPL_PAD_TO               0x40000
  53 #define CONFIG_SPL_MAX_SIZE             0x28000
  54 #define RESET_VECTOR_OFFSET             0x27FFC
  55 #define BOOT_PAGE_OFFSET                0x27000
  56 #ifdef CONFIG_SPL_BUILD
  57 #define CONFIG_SPL_SKIP_RELOCATE
  58 #define CONFIG_SPL_COMMON_INIT_DDR
  59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  60 #define CONFIG_SYS_NO_FLASH
  61 #endif
  62
  63 #ifdef CONFIG_NAND
  64 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  65 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  66 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  67 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  68 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  69 #define CONFIG_SPL_NAND_BOOT
  70 #endif
  71
  72 #ifdef CONFIG_SPIFLASH
  73 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  74 #define CONFIG_SPL_SPI_SUPPORT
  75 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  76 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  81 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  82 #ifndef CONFIG_SPL_BUILD
  83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  84 #endif
  85 #define CONFIG_SPL_SPI_BOOT
  86 #endif
  87
  88 #ifdef CONFIG_SDCARD
  89 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  90 #define CONFIG_SPL_MMC_MINIMAL
  91 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  92 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  93 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  94 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  95 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  96 #ifndef CONFIG_SPL_BUILD
  97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  98 #endif
  99 #define CONFIG_SPL_MMC_BOOT
 100 #endif
 101
 102 #endif /* CONFIG_RAMBOOT_PBL */
 103
 104 #ifndef CONFIG_SYS_TEXT_BASE
 105 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 106 #endif
 107
 108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 109 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 110 #endif
 111
 112 #ifndef CONFIG_SYS_NO_FLASH
 113 #define CONFIG_FLASH_CFI_DRIVER
 114 #define CONFIG_SYS_FLASH_CFI
 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 116 #endif
 117
 118 /* PCIe Boot - Master */
 119 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 120 /*
 121  * for slave u-boot IMAGE instored in master memory space,
 122  * PHYS must be aligned based on the SIZE
 123  */
 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 129 #else
 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 132 #endif
 133 /*
 134  * for slave UCODE and ENV instored in master memory space,
 135  * PHYS must be aligned based on the SIZE
 136  */
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 140 #else
 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 143 #endif
 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 145 /* slave core release by master*/
 146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 148
 149 /* PCIe Boot - Slave */
 150 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 153                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 154 /* Set 1M boot space for PCIe boot */
 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 157                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 159 #define CONFIG_SYS_NO_FLASH
 160 #endif
 161
 162 #if defined(CONFIG_SPIFLASH)
 163 #define CONFIG_SYS_EXTRA_ENV_RELOC
 164 #define CONFIG_ENV_IS_IN_SPI_FLASH
 165 #define CONFIG_ENV_SPI_BUS              0
 166 #define CONFIG_ENV_SPI_CS               0
 167 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 168 #define CONFIG_ENV_SPI_MODE             0
 169 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 170 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 171 #define CONFIG_ENV_SECT_SIZE            0x10000
 172 #elif defined(CONFIG_SDCARD)
 173 #define CONFIG_SYS_EXTRA_ENV_RELOC
 174 #define CONFIG_ENV_IS_IN_MMC
 175 #define CONFIG_SYS_MMC_ENV_DEV          0
 176 #define CONFIG_ENV_SIZE                 0x2000
 177 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 178 #elif defined(CONFIG_NAND)
 179 #define CONFIG_SYS_EXTRA_ENV_RELOC
 180 #define CONFIG_ENV_IS_IN_NAND
 181 #define CONFIG_ENV_SIZE                 0x2000
 182 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 183 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 184 #define CONFIG_ENV_IS_IN_REMOTE
 185 #define CONFIG_ENV_ADDR         0xffe20000
 186 #define CONFIG_ENV_SIZE         0x2000
 187 #elif defined(CONFIG_ENV_IS_NOWHERE)
 188 #define CONFIG_ENV_SIZE         0x2000
 189 #else
 190 #define CONFIG_ENV_IS_IN_FLASH
 191 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 192 #define CONFIG_ENV_SIZE         0x2000
 193 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 194 #endif
 195
 196 #ifndef __ASSEMBLY__
 197 unsigned long get_board_sys_clk(void);
 198 unsigned long get_board_ddr_clk(void);
 199 #endif
 200
 201 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 202 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 203
 204 /*
 205  * These can be toggled for performance analysis, otherwise use default.
 206  */
 207 #define CONFIG_SYS_CACHE_STASHING
 208 #define CONFIG_BACKSIDE_L2_CACHE
 209 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 210 #define CONFIG_BTB                      /* toggle branch predition */
 211 #define CONFIG_DDR_ECC
 212 #ifdef CONFIG_DDR_ECC
 213 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 214 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 215 #endif
 216
 217 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 218 #define CONFIG_SYS_MEMTEST_END          0x00400000
 219 #define CONFIG_SYS_ALT_MEMTEST
 220 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 221
 222 /*
 223  *  Config the L3 Cache as L3 SRAM
 224  */
 225 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 226 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 227 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 228 #ifdef CONFIG_RAMBOOT_PBL
 229 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 230 #endif
 231 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 232 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 233 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 234 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 235
 236 #ifdef CONFIG_PHYS_64BIT
 237 #define CONFIG_SYS_DCSRBAR              0xf0000000
 238 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 239 #endif
 240
 241 /* EEPROM */
 242 #define CONFIG_ID_EEPROM
 243 #define CONFIG_SYS_I2C_EEPROM_NXID
 244 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 245 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 246 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 249
 250 /*
 251  * DDR Setup
 252  */
 253 #define CONFIG_VERY_BIG_RAM
 254 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 255 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 256 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 257 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 258 #define CONFIG_DDR_SPD
 259 #ifndef CONFIG_SYS_FSL_DDR4
 260 #define CONFIG_SYS_FSL_DDR3
 261 #endif
 262
 263 #define CONFIG_SYS_SPD_BUS_NUM  0
 264 #define SPD_EEPROM_ADDRESS      0x51
 265
 266 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 267
 268 /*
 269  * IFC Definitions
 270  */
 271 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 272 #ifdef CONFIG_PHYS_64BIT
 273 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 274 #else
 275 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 276 #endif
 277
 278 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 279 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 280                                 + 0x8000000) | \
 281                                 CSPR_PORT_SIZE_16 | \
 282                                 CSPR_MSEL_NOR | \
 283                                 CSPR_V)
 284 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 285 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 286                                 CSPR_PORT_SIZE_16 | \
 287                                 CSPR_MSEL_NOR | \
 288                                 CSPR_V)
 289 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 290 /* NOR Flash Timing Params */
 291 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 292 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 293                                 FTIM0_NOR_TEADC(0x5) | \
 294                                 FTIM0_NOR_TEAHC(0x5))
 295 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 296                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 297                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 298 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 299                                 FTIM2_NOR_TCH(0x4) | \
 300                                 FTIM2_NOR_TWPH(0x0E) | \
 301                                 FTIM2_NOR_TWP(0x1c))
 302 #define CONFIG_SYS_NOR_FTIM3    0x0
 303
 304 #define CONFIG_SYS_FLASH_QUIET_TEST
 305 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 306
 307 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 308 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 309 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 310 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 311
 312 #define CONFIG_SYS_FLASH_EMPTY_INFO
 313 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 314                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 315 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 316 #define QIXIS_BASE              0xffdf0000
 317 #ifdef CONFIG_PHYS_64BIT
 318 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 319 #else
 320 #define QIXIS_BASE_PHYS         QIXIS_BASE
 321 #endif
 322 #define QIXIS_LBMAP_SWITCH              0x06
 323 #define QIXIS_LBMAP_MASK                0x0f
 324 #define QIXIS_LBMAP_SHIFT               0
 325 #define QIXIS_LBMAP_DFLTBANK            0x00
 326 #define QIXIS_LBMAP_ALTBANK             0x04
 327 #define QIXIS_RST_CTL_RESET             0x31
 328 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 329 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 330 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 331 #define QIXIS_RST_FORCE_MEM             0x01
 332
 333 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 334 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 335                                 | CSPR_PORT_SIZE_8 \
 336                                 | CSPR_MSEL_GPCM \
 337                                 | CSPR_V)
 338 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 339 #define CONFIG_SYS_CSOR3        0x0
 340 /* QIXIS Timing parameters for IFC CS3 */
 341 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 342                                         FTIM0_GPCM_TEADC(0x0e) | \
 343                                         FTIM0_GPCM_TEAHC(0x0e))
 344 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 345                                         FTIM1_GPCM_TRAD(0x3f))
 346 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 347                                         FTIM2_GPCM_TCH(0x8) | \
 348                                         FTIM2_GPCM_TWP(0x1f))
 349 #define CONFIG_SYS_CS3_FTIM3            0x0
 350
 351 #define CONFIG_NAND_FSL_IFC
 352 #define CONFIG_SYS_NAND_BASE            0xff800000
 353 #ifdef CONFIG_PHYS_64BIT
 354 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 355 #else
 356 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 357 #endif
 358 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 359 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 360                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 361                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 362                                 | CSPR_V)
 363 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 364
 365 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 366                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 367                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 368                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 369                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 370                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 371                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 372
 373 #define CONFIG_SYS_NAND_ONFI_DETECTION
 374
 375 /* ONFI NAND Flash mode0 Timing Params */
 376 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 377                                         FTIM0_NAND_TWP(0x18)   | \
 378                                         FTIM0_NAND_TWCHT(0x07) | \
 379                                         FTIM0_NAND_TWH(0x0a))
 380 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 381                                         FTIM1_NAND_TWBE(0x39)  | \
 382                                         FTIM1_NAND_TRR(0x0e)   | \
 383                                         FTIM1_NAND_TRP(0x18))
 384 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 385                                         FTIM2_NAND_TREH(0x0a) | \
 386                                         FTIM2_NAND_TWHRE(0x1e))
 387 #define CONFIG_SYS_NAND_FTIM3           0x0
 388
 389 #define CONFIG_SYS_NAND_DDR_LAW         11
 390 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 391 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 392 #define CONFIG_CMD_NAND
 393
 394 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 395
 396 #if defined(CONFIG_NAND)
 397 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 398 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 399 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 400 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 401 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 402 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 403 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 404 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 405 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 406 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 407 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 408 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 409 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 410 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 411 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 412 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 413 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 414 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 415 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 416 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 417 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 418 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 419 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 420 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 421 #else
 422 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 423 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 424 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 425 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 426 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 427 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 428 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 429 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 430 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 431 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 432 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 433 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 434 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 435 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 436 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 437 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 438 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 439 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 440 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 441 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 442 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 443 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 444 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 445 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 446 #endif
 447
 448 #ifdef CONFIG_SPL_BUILD
 449 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 450 #else
 451 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 452 #endif
 453
 454 #if defined(CONFIG_RAMBOOT_PBL)
 455 #define CONFIG_SYS_RAMBOOT
 456 #endif
 457
 458 #define CONFIG_BOARD_EARLY_INIT_R
 459 #define CONFIG_MISC_INIT_R
 460
 461 #define CONFIG_HWCONFIG
 462
 463 /* define to use L1 as initial stack */
 464 #define CONFIG_L1_INIT_RAM
 465 #define CONFIG_SYS_INIT_RAM_LOCK
 466 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 467 #ifdef CONFIG_PHYS_64BIT
 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 470 /* The assembler doesn't like typecast */
 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 472         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 473           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 474 #else
 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 478 #endif
 479 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 480
 481 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 482                                         GENERATED_GBL_DATA_SIZE)
 483 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 484
 485 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 486 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 487
 488 /* Serial Port */
 489 #define CONFIG_CONS_INDEX       1
 490 #define CONFIG_SYS_NS16550_SERIAL
 491 #define CONFIG_SYS_NS16550_REG_SIZE     1
 492 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 493
 494 #define CONFIG_SYS_BAUDRATE_TABLE       \
 495         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 496
 497 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 498 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 499 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 500 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 501 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 502
 503 /* Video */
 504 #ifdef CONFIG_PPC_T1024         /* no DIU on T1023 */
 505 #define CONFIG_FSL_DIU_FB
 506 #ifdef CONFIG_FSL_DIU_FB
 507 #define CONFIG_FSL_DIU_CH7301
 508 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 509 #define CONFIG_VIDEO
 510 #define CONFIG_CMD_BMP
 511 #define CONFIG_CFB_CONSOLE
 512 #define CONFIG_VIDEO_SW_CURSOR
 513 #define CONFIG_VGA_AS_SINGLE_DEVICE
 514 #define CONFIG_VIDEO_LOGO
 515 #define CONFIG_VIDEO_BMP_LOGO
 516 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 517 /*
 518  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 519  * disable empty flash sector detection, which is I/O-intensive.
 520  */
 521 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 522 #endif
 523 #endif
 524
 525 /* I2C */
 526 #define CONFIG_SYS_I2C
 527 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 528 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 529 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 530 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 531 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 532 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 533 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 534
 535 #define I2C_MUX_PCA_ADDR                0x77
 536 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 537 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 538 #define I2C_RETIMER_ADDR                0x18
 539
 540 /* I2C bus multiplexer */
 541 #define I2C_MUX_CH_DEFAULT      0x8
 542 #define I2C_MUX_CH_DIU          0xC
 543 #define I2C_MUX_CH5             0xD
 544 #define I2C_MUX_CH7             0xF
 545
 546 /* LDI/DVI Encoder for display */
 547 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 548 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 549
 550 /*
 551  * RTC configuration
 552  */
 553 #define RTC
 554 #define CONFIG_RTC_DS3231       1
 555 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 556
 557 /*
 558  * eSPI - Enhanced SPI
 559  */
 560 #ifndef CONFIG_SPL_BUILD
 561 #endif
 562 #define CONFIG_SPI_FLASH_BAR
 563 #define CONFIG_SF_DEFAULT_SPEED  10000000
 564 #define CONFIG_SF_DEFAULT_MODE    0
 565
 566 /*
 567  * General PCIe
 568  * Memory space is mapped 1-1, but I/O space must start from 0.
 569  */
 570 #define CONFIG_PCI              /* Enable PCI/PCIE */
 571 #define CONFIG_PCIE1            /* PCIE controller 1 */
 572 #define CONFIG_PCIE2            /* PCIE controller 2 */
 573 #define CONFIG_PCIE3            /* PCIE controller 3 */
 574 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 575 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 576 #define CONFIG_PCI_INDIRECT_BRIDGE
 577
 578 #ifdef CONFIG_PCI
 579 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 580 #ifdef CONFIG_PCIE1
 581 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 582 #ifdef CONFIG_PHYS_64BIT
 583 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 584 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 585 #else
 586 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 587 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 588 #endif
 589 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 590 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 591 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 592 #ifdef CONFIG_PHYS_64BIT
 593 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 594 #else
 595 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 596 #endif
 597 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 598 #endif
 599
 600 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 601 #ifdef CONFIG_PCIE2
 602 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 603 #ifdef CONFIG_PHYS_64BIT
 604 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 605 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 606 #else
 607 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 608 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 609 #endif
 610 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 611 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 612 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 613 #ifdef CONFIG_PHYS_64BIT
 614 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 615 #else
 616 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 617 #endif
 618 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 619 #endif
 620
 621 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 622 #ifdef CONFIG_PCIE3
 623 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 624 #ifdef CONFIG_PHYS_64BIT
 625 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 626 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 627 #else
 628 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 629 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 630 #endif
 631 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 632 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 633 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 634 #ifdef CONFIG_PHYS_64BIT
 635 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 636 #else
 637 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 638 #endif
 639 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 640 #endif
 641
 642 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 643 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 644 #define CONFIG_DOS_PARTITION
 645 #endif  /* CONFIG_PCI */
 646
 647 /*
 648  *SATA
 649  */
 650 #define CONFIG_FSL_SATA_V2
 651 #ifdef CONFIG_FSL_SATA_V2
 652 #define CONFIG_LIBATA
 653 #define CONFIG_FSL_SATA
 654 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 655 #define CONFIG_SATA1
 656 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 657 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 658 #define CONFIG_LBA48
 659 #define CONFIG_CMD_SATA
 660 #define CONFIG_DOS_PARTITION
 661 #endif
 662
 663 /*
 664  * USB
 665  */
 666 #define CONFIG_HAS_FSL_DR_USB
 667
 668 #ifdef CONFIG_HAS_FSL_DR_USB
 669 #define CONFIG_USB_EHCI
 670 #define CONFIG_USB_EHCI_FSL
 671 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 672 #endif
 673
 674 /*
 675  * SDHC
 676  */
 677 #define CONFIG_MMC
 678 #ifdef CONFIG_MMC
 679 #define CONFIG_FSL_ESDHC
 680 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 681 #define CONFIG_GENERIC_MMC
 682 #define CONFIG_DOS_PARTITION
 683 #endif
 684
 685 /* Qman/Bman */
 686 #ifndef CONFIG_NOBQFMAN
 687 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 688 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 689 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 690 #ifdef CONFIG_PHYS_64BIT
 691 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 692 #else
 693 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 694 #endif
 695 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 696 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 697 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 698 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 699 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 700 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 701                                         CONFIG_SYS_BMAN_CENA_SIZE)
 702 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 703 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 704 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 705 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 706 #ifdef CONFIG_PHYS_64BIT
 707 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 708 #else
 709 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 710 #endif
 711 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 712 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 713 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 714 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 715 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 716 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 717                                         CONFIG_SYS_QMAN_CENA_SIZE)
 718 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 719 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 720
 721 #define CONFIG_SYS_DPAA_FMAN
 722
 723 #define CONFIG_QE
 724 #define CONFIG_U_QE
 725 /* Default address of microcode for the Linux FMan driver */
 726 #if defined(CONFIG_SPIFLASH)
 727 /*
 728  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 729  * env, so we got 0x110000.
 730  */
 731 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 732 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 733 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 734 #elif defined(CONFIG_SDCARD)
 735 /*
 736  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 737  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 738  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 739  */
 740 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 741 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 742 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 743 #elif defined(CONFIG_NAND)
 744 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 745 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 746 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 747 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 748 /*
 749  * Slave has no ucode locally, it can fetch this from remote. When implementing
 750  * in two corenet boards, slave's ucode could be stored in master's memory
 751  * space, the address can be mapped from slave TLB->slave LAW->
 752  * slave SRIO or PCIE outbound window->master inbound window->
 753  * master LAW->the ucode address in master's memory space.
 754  */
 755 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 756 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 757 #else
 758 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 759 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 760 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 761 #endif
 762 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 763 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 764 #endif /* CONFIG_NOBQFMAN */
 765
 766 #ifdef CONFIG_SYS_DPAA_FMAN
 767 #define CONFIG_FMAN_ENET
 768 #define CONFIG_PHYLIB_10G
 769 #define CONFIG_PHY_VITESSE
 770 #define CONFIG_PHY_REALTEK
 771 #define CONFIG_PHY_TERANETICS
 772 #define RGMII_PHY1_ADDR         0x1
 773 #define RGMII_PHY2_ADDR         0x2
 774 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 775 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 776 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 777 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 778 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 779 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 780 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 781 #endif
 782
 783 #ifdef CONFIG_FMAN_ENET
 784 #define CONFIG_MII              /* MII PHY management */
 785 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 786 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 787 #endif
 788
 789 /*
 790  * Dynamic MTD Partition support with mtdparts
 791  */
 792 #ifndef CONFIG_SYS_NO_FLASH
 793 #define CONFIG_MTD_DEVICE
 794 #define CONFIG_MTD_PARTITIONS
 795 #define CONFIG_CMD_MTDPARTS
 796 #define CONFIG_FLASH_CFI_MTD
 797 #define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
 798                           "spi0=spife110000.0"
 799 #define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 800                           "128k(dtb),96m(fs),-(user);"\
 801                           "fff800000.flash:2m(uboot),9m(kernel),"\
 802                           "128k(dtb),96m(fs),-(user);spife110000.0:" \
 803                           "2m(uboot),9m(kernel),128k(dtb),-(user)"
 804 #endif
 805
 806 /*
 807  * Environment
 808  */
 809 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 810 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 811
 812 /*
 813  * Command line configuration.
 814  */
 815 #define CONFIG_CMD_DATE
 816 #define CONFIG_CMD_EEPROM
 817 #define CONFIG_CMD_ERRATA
 818 #define CONFIG_CMD_IRQ
 819 #define CONFIG_CMD_REGINFO
 820
 821 #ifdef CONFIG_PCI
 822 #define CONFIG_CMD_PCI
 823 #endif
 824
 825 /*
 826  * Miscellaneous configurable options
 827  */
 828 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 829 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 830 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 831 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 832 #ifdef CONFIG_CMD_KGDB
 833 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 834 #else
 835 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 836 #endif
 837 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 838 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 839 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 840
 841 /*
 842  * For booting Linux, the board info and command line data
 843  * have to be in the first 64 MB of memory, since this is
 844  * the maximum mapped by the Linux kernel during initialization.
 845  */
 846 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 847 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 848
 849 #ifdef CONFIG_CMD_KGDB
 850 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 851 #endif
 852
 853 /*
 854  * Environment Configuration
 855  */
 856 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 857 #define CONFIG_BOOTFILE         "uImage"
 858 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 859 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 860 #define CONFIG_BAUDRATE         115200
 861 #define __USB_PHY_TYPE          utmi
 862
 863 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 864         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 865         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 866         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 867         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 868         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 869         "netdev=eth0\0"                                         \
 870         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 871         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 872         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 873         "tftpflash=tftpboot $loadaddr $uboot && "               \
 874         "protect off $ubootaddr +$filesize && "                 \
 875         "erase $ubootaddr +$filesize && "                       \
 876         "cp.b $loadaddr $ubootaddr $filesize && "               \
 877         "protect on $ubootaddr +$filesize && "                  \
 878         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 879         "consoledev=ttyS0\0"                                    \
 880         "ramdiskaddr=2000000\0"                                 \
 881         "fdtaddr=d00000\0"                                      \
 882         "bdev=sda3\0"
 883
 884 #define CONFIG_LINUX                                    \
 885         "setenv bootargs root=/dev/ram rw "             \
 886         "console=$consoledev,$baudrate $othbootargs;"   \
 887         "setenv ramdiskaddr 0x02000000;"                \
 888         "setenv fdtaddr 0x00c00000;"                    \
 889         "setenv loadaddr 0x1000000;"                    \
 890         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 891
 892 #define CONFIG_NFSBOOTCOMMAND                   \
 893         "setenv bootargs root=/dev/nfs rw "     \
 894         "nfsroot=$serverip:$rootpath "          \
 895         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 896         "console=$consoledev,$baudrate $othbootargs;"   \
 897         "tftp $loadaddr $bootfile;"             \
 898         "tftp $fdtaddr $fdtfile;"               \
 899         "bootm $loadaddr - $fdtaddr"
 900
 901 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 902
 903 /* Hash command with SHA acceleration supported in hardware */
 904 #ifdef CONFIG_FSL_CAAM
 905 #define CONFIG_CMD_HASH
 906 #define CONFIG_SHA_HW_ACCEL
 907 #endif
 908
 909 #include <asm/fsl_secure_boot.h>
 910
 911 #endif  /* __T1024QDS_H */