include/configs/T102xQDS.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  26 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  27
  28 #define CONFIG_ENV_OVERWRITE
  29
  30 #define CONFIG_DEEP_SLEEP
  31 #if defined(CONFIG_DEEP_SLEEP)
  32 #define CONFIG_BOARD_EARLY_INIT_F
  33 #endif
  34
  35 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  36
  37 #ifdef CONFIG_RAMBOOT_PBL
  38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  39 #define CONFIG_SPL_FLUSH_IMAGE
  40 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  41 #define CONFIG_SYS_TEXT_BASE            0x00201000
  42 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  43 #define CONFIG_SPL_PAD_TO               0x40000
  44 #define CONFIG_SPL_MAX_SIZE             0x28000
  45 #define RESET_VECTOR_OFFSET             0x27FFC
  46 #define BOOT_PAGE_OFFSET                0x27000
  47 #ifdef CONFIG_SPL_BUILD
  48 #define CONFIG_SPL_SKIP_RELOCATE
  49 #define CONFIG_SPL_COMMON_INIT_DDR
  50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  51 #define CONFIG_SYS_NO_FLASH
  52 #endif
  53
  54 #ifdef CONFIG_NAND
  55 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  56 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  57 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  58 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  59 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  61 #define CONFIG_SPL_NAND_BOOT
  62 #endif
  63
  64 #ifdef CONFIG_SPIFLASH
  65 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  71 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  72 #ifndef CONFIG_SPL_BUILD
  73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  74 #endif
  75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  76 #define CONFIG_SPL_SPI_BOOT
  77 #endif
  78
  79 #ifdef CONFIG_SDCARD
  80 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  81 #define CONFIG_SPL_MMC_MINIMAL
  82 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  83 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  84 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  85 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  86 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  87 #ifndef CONFIG_SPL_BUILD
  88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  89 #endif
  90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  91 #define CONFIG_SPL_MMC_BOOT
  92 #endif
  93
  94 #endif /* CONFIG_RAMBOOT_PBL */
  95
  96 #ifndef CONFIG_SYS_TEXT_BASE
  97 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  98 #endif
  99
 100 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 101 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 102 #endif
 103
 104 #ifndef CONFIG_SYS_NO_FLASH
 105 #define CONFIG_FLASH_CFI_DRIVER
 106 #define CONFIG_SYS_FLASH_CFI
 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 108 #endif
 109
 110 /* PCIe Boot - Master */
 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 112 /*
 113  * for slave u-boot IMAGE instored in master memory space,
 114  * PHYS must be aligned based on the SIZE
 115  */
 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 121 #else
 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 124 #endif
 125 /*
 126  * for slave UCODE and ENV instored in master memory space,
 127  * PHYS must be aligned based on the SIZE
 128  */
 129 #ifdef CONFIG_PHYS_64BIT
 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 132 #else
 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 135 #endif
 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 137 /* slave core release by master*/
 138 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 139 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 140
 141 /* PCIe Boot - Slave */
 142 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 145                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 146 /* Set 1M boot space for PCIe boot */
 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 149                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 151 #define CONFIG_SYS_NO_FLASH
 152 #endif
 153
 154 #if defined(CONFIG_SPIFLASH)
 155 #define CONFIG_SYS_EXTRA_ENV_RELOC
 156 #define CONFIG_ENV_IS_IN_SPI_FLASH
 157 #define CONFIG_ENV_SPI_BUS              0
 158 #define CONFIG_ENV_SPI_CS               0
 159 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 160 #define CONFIG_ENV_SPI_MODE             0
 161 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 162 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 163 #define CONFIG_ENV_SECT_SIZE            0x10000
 164 #elif defined(CONFIG_SDCARD)
 165 #define CONFIG_SYS_EXTRA_ENV_RELOC
 166 #define CONFIG_ENV_IS_IN_MMC
 167 #define CONFIG_SYS_MMC_ENV_DEV          0
 168 #define CONFIG_ENV_SIZE                 0x2000
 169 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 170 #elif defined(CONFIG_NAND)
 171 #define CONFIG_SYS_EXTRA_ENV_RELOC
 172 #define CONFIG_ENV_IS_IN_NAND
 173 #define CONFIG_ENV_SIZE                 0x2000
 174 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 175 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 176 #define CONFIG_ENV_IS_IN_REMOTE
 177 #define CONFIG_ENV_ADDR         0xffe20000
 178 #define CONFIG_ENV_SIZE         0x2000
 179 #elif defined(CONFIG_ENV_IS_NOWHERE)
 180 #define CONFIG_ENV_SIZE         0x2000
 181 #else
 182 #define CONFIG_ENV_IS_IN_FLASH
 183 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 184 #define CONFIG_ENV_SIZE         0x2000
 185 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 186 #endif
 187
 188 #ifndef __ASSEMBLY__
 189 unsigned long get_board_sys_clk(void);
 190 unsigned long get_board_ddr_clk(void);
 191 #endif
 192
 193 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 194 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 195
 196 /*
 197  * These can be toggled for performance analysis, otherwise use default.
 198  */
 199 #define CONFIG_SYS_CACHE_STASHING
 200 #define CONFIG_BACKSIDE_L2_CACHE
 201 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 202 #define CONFIG_BTB                      /* toggle branch predition */
 203 #define CONFIG_DDR_ECC
 204 #ifdef CONFIG_DDR_ECC
 205 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 206 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 207 #endif
 208
 209 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 210 #define CONFIG_SYS_MEMTEST_END          0x00400000
 211 #define CONFIG_SYS_ALT_MEMTEST
 212 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 213
 214 /*
 215  *  Config the L3 Cache as L3 SRAM
 216  */
 217 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 218 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 219 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 220 #ifdef CONFIG_RAMBOOT_PBL
 221 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 222 #endif
 223 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 224 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 225 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 226 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 227
 228 #ifdef CONFIG_PHYS_64BIT
 229 #define CONFIG_SYS_DCSRBAR              0xf0000000
 230 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 231 #endif
 232
 233 /* EEPROM */
 234 #define CONFIG_ID_EEPROM
 235 #define CONFIG_SYS_I2C_EEPROM_NXID
 236 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 237 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 241
 242 /*
 243  * DDR Setup
 244  */
 245 #define CONFIG_VERY_BIG_RAM
 246 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 247 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 248 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 249 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 250 #define CONFIG_DDR_SPD
 251
 252 #define CONFIG_SYS_SPD_BUS_NUM  0
 253 #define SPD_EEPROM_ADDRESS      0x51
 254
 255 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 256
 257 /*
 258  * IFC Definitions
 259  */
 260 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 261 #ifdef CONFIG_PHYS_64BIT
 262 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 263 #else
 264 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 265 #endif
 266
 267 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 268 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 269                                 + 0x8000000) | \
 270                                 CSPR_PORT_SIZE_16 | \
 271                                 CSPR_MSEL_NOR | \
 272                                 CSPR_V)
 273 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 274 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 275                                 CSPR_PORT_SIZE_16 | \
 276                                 CSPR_MSEL_NOR | \
 277                                 CSPR_V)
 278 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 279 /* NOR Flash Timing Params */
 280 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 281 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 282                                 FTIM0_NOR_TEADC(0x5) | \
 283                                 FTIM0_NOR_TEAHC(0x5))
 284 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 285                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 286                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 287 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 288                                 FTIM2_NOR_TCH(0x4) | \
 289                                 FTIM2_NOR_TWPH(0x0E) | \
 290                                 FTIM2_NOR_TWP(0x1c))
 291 #define CONFIG_SYS_NOR_FTIM3    0x0
 292
 293 #define CONFIG_SYS_FLASH_QUIET_TEST
 294 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 295
 296 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 297 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 298 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 299 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 300
 301 #define CONFIG_SYS_FLASH_EMPTY_INFO
 302 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 303                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 304 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 305 #define QIXIS_BASE              0xffdf0000
 306 #ifdef CONFIG_PHYS_64BIT
 307 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 308 #else
 309 #define QIXIS_BASE_PHYS         QIXIS_BASE
 310 #endif
 311 #define QIXIS_LBMAP_SWITCH              0x06
 312 #define QIXIS_LBMAP_MASK                0x0f
 313 #define QIXIS_LBMAP_SHIFT               0
 314 #define QIXIS_LBMAP_DFLTBANK            0x00
 315 #define QIXIS_LBMAP_ALTBANK             0x04
 316 #define QIXIS_RST_CTL_RESET             0x31
 317 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 318 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 319 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 320 #define QIXIS_RST_FORCE_MEM             0x01
 321
 322 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 323 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 324                                 | CSPR_PORT_SIZE_8 \
 325                                 | CSPR_MSEL_GPCM \
 326                                 | CSPR_V)
 327 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 328 #define CONFIG_SYS_CSOR3        0x0
 329 /* QIXIS Timing parameters for IFC CS3 */
 330 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 331                                         FTIM0_GPCM_TEADC(0x0e) | \
 332                                         FTIM0_GPCM_TEAHC(0x0e))
 333 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 334                                         FTIM1_GPCM_TRAD(0x3f))
 335 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 336                                         FTIM2_GPCM_TCH(0x8) | \
 337                                         FTIM2_GPCM_TWP(0x1f))
 338 #define CONFIG_SYS_CS3_FTIM3            0x0
 339
 340 #define CONFIG_NAND_FSL_IFC
 341 #define CONFIG_SYS_NAND_BASE            0xff800000
 342 #ifdef CONFIG_PHYS_64BIT
 343 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 344 #else
 345 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 346 #endif
 347 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 348 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 349                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 350                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 351                                 | CSPR_V)
 352 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 353
 354 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 355                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 356                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 357                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 358                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 359                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 360                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 361
 362 #define CONFIG_SYS_NAND_ONFI_DETECTION
 363
 364 /* ONFI NAND Flash mode0 Timing Params */
 365 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 366                                         FTIM0_NAND_TWP(0x18)   | \
 367                                         FTIM0_NAND_TWCHT(0x07) | \
 368                                         FTIM0_NAND_TWH(0x0a))
 369 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 370                                         FTIM1_NAND_TWBE(0x39)  | \
 371                                         FTIM1_NAND_TRR(0x0e)   | \
 372                                         FTIM1_NAND_TRP(0x18))
 373 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 374                                         FTIM2_NAND_TREH(0x0a) | \
 375                                         FTIM2_NAND_TWHRE(0x1e))
 376 #define CONFIG_SYS_NAND_FTIM3           0x0
 377
 378 #define CONFIG_SYS_NAND_DDR_LAW         11
 379 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 380 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 381 #define CONFIG_CMD_NAND
 382
 383 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 384
 385 #if defined(CONFIG_NAND)
 386 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 387 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 388 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 389 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 390 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 391 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 392 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 393 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 394 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 395 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 396 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 397 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 398 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 399 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 400 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 401 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 402 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 403 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 404 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 405 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 406 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 407 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 408 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 409 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 410 #else
 411 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 412 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 413 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 414 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 415 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 416 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 417 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 418 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 419 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 420 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 421 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 422 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 423 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 424 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 425 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 426 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 427 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 428 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 429 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 430 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 431 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 432 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 433 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 434 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 435 #endif
 436
 437 #ifdef CONFIG_SPL_BUILD
 438 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 439 #else
 440 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 441 #endif
 442
 443 #if defined(CONFIG_RAMBOOT_PBL)
 444 #define CONFIG_SYS_RAMBOOT
 445 #endif
 446
 447 #define CONFIG_BOARD_EARLY_INIT_R
 448 #define CONFIG_MISC_INIT_R
 449
 450 #define CONFIG_HWCONFIG
 451
 452 /* define to use L1 as initial stack */
 453 #define CONFIG_L1_INIT_RAM
 454 #define CONFIG_SYS_INIT_RAM_LOCK
 455 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 456 #ifdef CONFIG_PHYS_64BIT
 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 459 /* The assembler doesn't like typecast */
 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 461         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 462           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 463 #else
 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 467 #endif
 468 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 469
 470 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 471                                         GENERATED_GBL_DATA_SIZE)
 472 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 473
 474 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 475 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 476
 477 /* Serial Port */
 478 #define CONFIG_CONS_INDEX       1
 479 #define CONFIG_SYS_NS16550_SERIAL
 480 #define CONFIG_SYS_NS16550_REG_SIZE     1
 481 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 482
 483 #define CONFIG_SYS_BAUDRATE_TABLE       \
 484         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 485
 486 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 487 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 488 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 489 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 490
 491 /* Video */
 492 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 493 #define CONFIG_FSL_DIU_FB
 494 #ifdef CONFIG_FSL_DIU_FB
 495 #define CONFIG_FSL_DIU_CH7301
 496 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 497 #define CONFIG_CMD_BMP
 498 #define CONFIG_VIDEO_LOGO
 499 #define CONFIG_VIDEO_BMP_LOGO
 500 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 501 /*
 502  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 503  * disable empty flash sector detection, which is I/O-intensive.
 504  */
 505 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 506 #endif
 507 #endif
 508
 509 /* I2C */
 510 #define CONFIG_SYS_I2C
 511 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 512 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 513 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 514 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 515 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 516 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 517 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 518
 519 #define I2C_MUX_PCA_ADDR                0x77
 520 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 521 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 522 #define I2C_RETIMER_ADDR                0x18
 523
 524 /* I2C bus multiplexer */
 525 #define I2C_MUX_CH_DEFAULT      0x8
 526 #define I2C_MUX_CH_DIU          0xC
 527 #define I2C_MUX_CH5             0xD
 528 #define I2C_MUX_CH7             0xF
 529
 530 /* LDI/DVI Encoder for display */
 531 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 532 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 533
 534 /*
 535  * RTC configuration
 536  */
 537 #define RTC
 538 #define CONFIG_RTC_DS3231       1
 539 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 540
 541 /*
 542  * eSPI - Enhanced SPI
 543  */
 544 #ifndef CONFIG_SPL_BUILD
 545 #endif
 546 #define CONFIG_SPI_FLASH_BAR
 547 #define CONFIG_SF_DEFAULT_SPEED  10000000
 548 #define CONFIG_SF_DEFAULT_MODE    0
 549
 550 /*
 551  * General PCIe
 552  * Memory space is mapped 1-1, but I/O space must start from 0.
 553  */
 554 #define CONFIG_PCIE1            /* PCIE controller 1 */
 555 #define CONFIG_PCIE2            /* PCIE controller 2 */
 556 #define CONFIG_PCIE3            /* PCIE controller 3 */
 557 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 558 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 559 #define CONFIG_PCI_INDIRECT_BRIDGE
 560
 561 #ifdef CONFIG_PCI
 562 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 563 #ifdef CONFIG_PCIE1
 564 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 565 #ifdef CONFIG_PHYS_64BIT
 566 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 567 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 568 #else
 569 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 570 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 571 #endif
 572 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 573 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 574 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 575 #ifdef CONFIG_PHYS_64BIT
 576 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 577 #else
 578 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 579 #endif
 580 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 581 #endif
 582
 583 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 584 #ifdef CONFIG_PCIE2
 585 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 586 #ifdef CONFIG_PHYS_64BIT
 587 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 588 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 589 #else
 590 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 591 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 592 #endif
 593 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 594 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 595 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 596 #ifdef CONFIG_PHYS_64BIT
 597 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 598 #else
 599 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 600 #endif
 601 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 602 #endif
 603
 604 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 605 #ifdef CONFIG_PCIE3
 606 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 607 #ifdef CONFIG_PHYS_64BIT
 608 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 609 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 610 #else
 611 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 612 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 613 #endif
 614 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 615 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 616 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 617 #ifdef CONFIG_PHYS_64BIT
 618 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 619 #else
 620 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 621 #endif
 622 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 623 #endif
 624
 625 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 626 #define CONFIG_DOS_PARTITION
 627 #endif  /* CONFIG_PCI */
 628
 629 /*
 630  *SATA
 631  */
 632 #define CONFIG_FSL_SATA_V2
 633 #ifdef CONFIG_FSL_SATA_V2
 634 #define CONFIG_LIBATA
 635 #define CONFIG_FSL_SATA
 636 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 637 #define CONFIG_SATA1
 638 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 639 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 640 #define CONFIG_LBA48
 641 #define CONFIG_CMD_SATA
 642 #define CONFIG_DOS_PARTITION
 643 #endif
 644
 645 /*
 646  * USB
 647  */
 648 #define CONFIG_HAS_FSL_DR_USB
 649
 650 #ifdef CONFIG_HAS_FSL_DR_USB
 651 #define CONFIG_USB_EHCI
 652 #define CONFIG_USB_EHCI_FSL
 653 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 654 #endif
 655
 656 /*
 657  * SDHC
 658  */
 659 #ifdef CONFIG_MMC
 660 #define CONFIG_FSL_ESDHC
 661 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 662 #define CONFIG_GENERIC_MMC
 663 #define CONFIG_DOS_PARTITION
 664 #endif
 665
 666 /* Qman/Bman */
 667 #ifndef CONFIG_NOBQFMAN
 668 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 669 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 670 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 671 #ifdef CONFIG_PHYS_64BIT
 672 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 673 #else
 674 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 675 #endif
 676 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 677 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 678 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 679 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 680 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 681 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 682                                         CONFIG_SYS_BMAN_CENA_SIZE)
 683 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 684 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 685 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 686 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 687 #ifdef CONFIG_PHYS_64BIT
 688 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 689 #else
 690 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 691 #endif
 692 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 693 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 694 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 695 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 696 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 697 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 698                                         CONFIG_SYS_QMAN_CENA_SIZE)
 699 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 700 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 701
 702 #define CONFIG_SYS_DPAA_FMAN
 703
 704 #define CONFIG_QE
 705 #define CONFIG_U_QE
 706 /* Default address of microcode for the Linux FMan driver */
 707 #if defined(CONFIG_SPIFLASH)
 708 /*
 709  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 710  * env, so we got 0x110000.
 711  */
 712 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 713 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 714 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 715 #elif defined(CONFIG_SDCARD)
 716 /*
 717  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 718  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 719  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 720  */
 721 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 722 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 723 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 724 #elif defined(CONFIG_NAND)
 725 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 726 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 727 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 728 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 729 /*
 730  * Slave has no ucode locally, it can fetch this from remote. When implementing
 731  * in two corenet boards, slave's ucode could be stored in master's memory
 732  * space, the address can be mapped from slave TLB->slave LAW->
 733  * slave SRIO or PCIE outbound window->master inbound window->
 734  * master LAW->the ucode address in master's memory space.
 735  */
 736 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 737 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 738 #else
 739 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 740 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 741 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 742 #endif
 743 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 744 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 745 #endif /* CONFIG_NOBQFMAN */
 746
 747 #ifdef CONFIG_SYS_DPAA_FMAN
 748 #define CONFIG_FMAN_ENET
 749 #define CONFIG_PHYLIB_10G
 750 #define CONFIG_PHY_VITESSE
 751 #define CONFIG_PHY_REALTEK
 752 #define CONFIG_PHY_TERANETICS
 753 #define RGMII_PHY1_ADDR         0x1
 754 #define RGMII_PHY2_ADDR         0x2
 755 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 756 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 757 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 758 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 759 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 760 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 761 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 762 #endif
 763
 764 #ifdef CONFIG_FMAN_ENET
 765 #define CONFIG_MII              /* MII PHY management */
 766 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 767 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 768 #endif
 769
 770 /*
 771  * Dynamic MTD Partition support with mtdparts
 772  */
 773 #ifndef CONFIG_SYS_NO_FLASH
 774 #define CONFIG_MTD_DEVICE
 775 #define CONFIG_MTD_PARTITIONS
 776 #define CONFIG_CMD_MTDPARTS
 777 #define CONFIG_FLASH_CFI_MTD
 778 #define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
 779                           "spi0=spife110000.0"
 780 #define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 781                           "128k(dtb),96m(fs),-(user);"\
 782                           "fff800000.flash:2m(uboot),9m(kernel),"\
 783                           "128k(dtb),96m(fs),-(user);spife110000.0:" \
 784                           "2m(uboot),9m(kernel),128k(dtb),-(user)"
 785 #endif
 786
 787 /*
 788  * Environment
 789  */
 790 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 791 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 792
 793 /*
 794  * Command line configuration.
 795  */
 796 #define CONFIG_CMD_DATE
 797 #define CONFIG_CMD_EEPROM
 798 #define CONFIG_CMD_ERRATA
 799 #define CONFIG_CMD_IRQ
 800 #define CONFIG_CMD_REGINFO
 801
 802 #ifdef CONFIG_PCI
 803 #define CONFIG_CMD_PCI
 804 #endif
 805
 806 /*
 807  * Miscellaneous configurable options
 808  */
 809 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 810 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 811 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 812 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 813 #ifdef CONFIG_CMD_KGDB
 814 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 815 #else
 816 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 817 #endif
 818 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 819 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 820 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 821
 822 /*
 823  * For booting Linux, the board info and command line data
 824  * have to be in the first 64 MB of memory, since this is
 825  * the maximum mapped by the Linux kernel during initialization.
 826  */
 827 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 828 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 829
 830 #ifdef CONFIG_CMD_KGDB
 831 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 832 #endif
 833
 834 /*
 835  * Environment Configuration
 836  */
 837 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 838 #define CONFIG_BOOTFILE         "uImage"
 839 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 840 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 841 #define CONFIG_BAUDRATE         115200
 842 #define __USB_PHY_TYPE          utmi
 843
 844 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 845         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 846         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 847         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 848         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 849         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 850         "netdev=eth0\0"                                         \
 851         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 852         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 853         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 854         "tftpflash=tftpboot $loadaddr $uboot && "               \
 855         "protect off $ubootaddr +$filesize && "                 \
 856         "erase $ubootaddr +$filesize && "                       \
 857         "cp.b $loadaddr $ubootaddr $filesize && "               \
 858         "protect on $ubootaddr +$filesize && "                  \
 859         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 860         "consoledev=ttyS0\0"                                    \
 861         "ramdiskaddr=2000000\0"                                 \
 862         "fdtaddr=d00000\0"                                      \
 863         "bdev=sda3\0"
 864
 865 #define CONFIG_LINUX                                    \
 866         "setenv bootargs root=/dev/ram rw "             \
 867         "console=$consoledev,$baudrate $othbootargs;"   \
 868         "setenv ramdiskaddr 0x02000000;"                \
 869         "setenv fdtaddr 0x00c00000;"                    \
 870         "setenv loadaddr 0x1000000;"                    \
 871         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 872
 873 #define CONFIG_NFSBOOTCOMMAND                   \
 874         "setenv bootargs root=/dev/nfs rw "     \
 875         "nfsroot=$serverip:$rootpath "          \
 876         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 877         "console=$consoledev,$baudrate $othbootargs;"   \
 878         "tftp $loadaddr $bootfile;"             \
 879         "tftp $fdtaddr $fdtfile;"               \
 880         "bootm $loadaddr - $fdtaddr"
 881
 882 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 883
 884 /* Hash command with SHA acceleration supported in hardware */
 885 #ifdef CONFIG_FSL_CAAM
 886 #define CONFIG_CMD_HASH
 887 #define CONFIG_SHA_HW_ACCEL
 888 #endif
 889
 890 #include <asm/fsl_secure_boot.h>
 891
 892 #endif  /* __T1024QDS_H */