1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 * T1024/T1023 QDS board configuration file
13 /* High Level Configuration Options */
14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
15 #define CONFIG_ENABLE_36BIT_PHYS
17 #ifdef CONFIG_PHYS_64BIT
18 #define CONFIG_ADDR_MAP 1
19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
25 #define CONFIG_ENV_OVERWRITE
27 #define CONFIG_DEEP_SLEEP
29 #ifdef CONFIG_RAMBOOT_PBL
30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
34 #define CONFIG_SPL_PAD_TO 0x40000
35 #define CONFIG_SPL_MAX_SIZE 0x28000
36 #define RESET_VECTOR_OFFSET 0x27FFC
37 #define BOOT_PAGE_OFFSET 0x27000
38 #ifdef CONFIG_SPL_BUILD
39 #define CONFIG_SPL_SKIP_RELOCATE
40 #define CONFIG_SPL_COMMON_INIT_DDR
41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
48 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
51 #define CONFIG_SPL_NAND_BOOT
54 #ifdef CONFIG_SPIFLASH
55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
56 #define CONFIG_SPL_SPI_FLASH_MINIMAL
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
62 #ifndef CONFIG_SPL_BUILD
63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
66 #define CONFIG_SPL_SPI_BOOT
70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
71 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
72 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
73 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
74 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
76 #ifndef CONFIG_SPL_BUILD
77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
80 #define CONFIG_SPL_MMC_BOOT
83 #endif /* CONFIG_RAMBOOT_PBL */
85 #ifndef CONFIG_RESET_VECTOR_ADDRESS
86 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
89 #ifdef CONFIG_MTD_NOR_FLASH
90 #define CONFIG_FLASH_CFI_DRIVER
91 #define CONFIG_SYS_FLASH_CFI
92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
95 /* PCIe Boot - Master */
96 #define CONFIG_SRIO_PCIE_BOOT_MASTER
98 * for slave u-boot IMAGE instored in master memory space,
99 * PHYS must be aligned based on the SIZE
101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
103 #ifdef CONFIG_PHYS_64BIT
104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
111 * for slave UCODE and ENV instored in master memory space,
112 * PHYS must be aligned based on the SIZE
114 #ifdef CONFIG_PHYS_64BIT
115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
119 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
122 /* slave core release by master*/
123 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
124 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
126 /* PCIe Boot - Slave */
127 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
128 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
129 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
130 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
131 /* Set 1M boot space for PCIe boot */
132 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
133 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
134 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
135 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
138 #if defined(CONFIG_SPIFLASH)
139 #define CONFIG_SYS_EXTRA_ENV_RELOC
140 #define CONFIG_ENV_SPI_BUS 0
141 #define CONFIG_ENV_SPI_CS 0
142 #define CONFIG_ENV_SPI_MAX_HZ 10000000
143 #define CONFIG_ENV_SPI_MODE 0
144 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
145 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
146 #define CONFIG_ENV_SECT_SIZE 0x10000
147 #elif defined(CONFIG_SDCARD)
148 #define CONFIG_SYS_EXTRA_ENV_RELOC
149 #define CONFIG_SYS_MMC_ENV_DEV 0
150 #define CONFIG_ENV_SIZE 0x2000
151 #define CONFIG_ENV_OFFSET (512 * 0x800)
152 #elif defined(CONFIG_NAND)
153 #define CONFIG_SYS_EXTRA_ENV_RELOC
154 #define CONFIG_ENV_SIZE 0x2000
155 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
156 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
157 #define CONFIG_ENV_ADDR 0xffe20000
158 #define CONFIG_ENV_SIZE 0x2000
159 #elif defined(CONFIG_ENV_IS_NOWHERE)
160 #define CONFIG_ENV_SIZE 0x2000
162 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
163 #define CONFIG_ENV_SIZE 0x2000
164 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
168 unsigned long get_board_sys_clk(void);
169 unsigned long get_board_ddr_clk(void);
172 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
173 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
176 * These can be toggled for performance analysis, otherwise use default.
178 #define CONFIG_SYS_CACHE_STASHING
179 #define CONFIG_BACKSIDE_L2_CACHE
180 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
181 #define CONFIG_BTB /* toggle branch predition */
182 #define CONFIG_DDR_ECC
183 #ifdef CONFIG_DDR_ECC
184 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
185 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
188 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
189 #define CONFIG_SYS_MEMTEST_END 0x00400000
192 * Config the L3 Cache as L3 SRAM
194 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
195 #define CONFIG_SYS_L3_SIZE (256 << 10)
196 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
197 #ifdef CONFIG_RAMBOOT_PBL
198 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
200 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
201 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
202 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
203 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
205 #ifdef CONFIG_PHYS_64BIT
206 #define CONFIG_SYS_DCSRBAR 0xf0000000
207 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
211 #define CONFIG_ID_EEPROM
212 #define CONFIG_SYS_I2C_EEPROM_NXID
213 #define CONFIG_SYS_EEPROM_BUS_NUM 0
214 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
222 #define CONFIG_VERY_BIG_RAM
223 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
224 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
225 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
226 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
227 #define CONFIG_DDR_SPD
229 #define CONFIG_SYS_SPD_BUS_NUM 0
230 #define SPD_EEPROM_ADDRESS 0x51
232 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
237 #define CONFIG_SYS_FLASH_BASE 0xe0000000
238 #ifdef CONFIG_PHYS_64BIT
239 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
241 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
244 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
245 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
247 CSPR_PORT_SIZE_16 | \
250 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
251 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
252 CSPR_PORT_SIZE_16 | \
255 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
256 /* NOR Flash Timing Params */
257 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
258 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
259 FTIM0_NOR_TEADC(0x5) | \
260 FTIM0_NOR_TEAHC(0x5))
261 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
262 FTIM1_NOR_TRAD_NOR(0x1A) |\
263 FTIM1_NOR_TSEQRAD_NOR(0x13))
264 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
265 FTIM2_NOR_TCH(0x4) | \
266 FTIM2_NOR_TWPH(0x0E) | \
268 #define CONFIG_SYS_NOR_FTIM3 0x0
270 #define CONFIG_SYS_FLASH_QUIET_TEST
271 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
273 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
274 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
275 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
276 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
278 #define CONFIG_SYS_FLASH_EMPTY_INFO
279 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
280 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
281 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
282 #define QIXIS_BASE 0xffdf0000
283 #ifdef CONFIG_PHYS_64BIT
284 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
286 #define QIXIS_BASE_PHYS QIXIS_BASE
288 #define QIXIS_LBMAP_SWITCH 0x06
289 #define QIXIS_LBMAP_MASK 0x0f
290 #define QIXIS_LBMAP_SHIFT 0
291 #define QIXIS_LBMAP_DFLTBANK 0x00
292 #define QIXIS_LBMAP_ALTBANK 0x04
293 #define QIXIS_RST_CTL_RESET 0x31
294 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
295 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
296 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
297 #define QIXIS_RST_FORCE_MEM 0x01
299 #define CONFIG_SYS_CSPR3_EXT (0xf)
300 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
304 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
305 #define CONFIG_SYS_CSOR3 0x0
306 /* QIXIS Timing parameters for IFC CS3 */
307 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
308 FTIM0_GPCM_TEADC(0x0e) | \
309 FTIM0_GPCM_TEAHC(0x0e))
310 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
311 FTIM1_GPCM_TRAD(0x3f))
312 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
313 FTIM2_GPCM_TCH(0x8) | \
314 FTIM2_GPCM_TWP(0x1f))
315 #define CONFIG_SYS_CS3_FTIM3 0x0
317 #define CONFIG_NAND_FSL_IFC
318 #define CONFIG_SYS_NAND_BASE 0xff800000
319 #ifdef CONFIG_PHYS_64BIT
320 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
322 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
324 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
325 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
326 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
327 | CSPR_MSEL_NAND /* MSEL = NAND */ \
329 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
331 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
332 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
333 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
334 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
335 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
336 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
337 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
339 #define CONFIG_SYS_NAND_ONFI_DETECTION
341 /* ONFI NAND Flash mode0 Timing Params */
342 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
343 FTIM0_NAND_TWP(0x18) | \
344 FTIM0_NAND_TWCHT(0x07) | \
345 FTIM0_NAND_TWH(0x0a))
346 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
347 FTIM1_NAND_TWBE(0x39) | \
348 FTIM1_NAND_TRR(0x0e) | \
349 FTIM1_NAND_TRP(0x18))
350 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
351 FTIM2_NAND_TREH(0x0a) | \
352 FTIM2_NAND_TWHRE(0x1e))
353 #define CONFIG_SYS_NAND_FTIM3 0x0
355 #define CONFIG_SYS_NAND_DDR_LAW 11
356 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
357 #define CONFIG_SYS_MAX_NAND_DEVICE 1
359 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
361 #if defined(CONFIG_NAND)
362 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
363 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
364 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
365 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
366 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
367 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
368 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
369 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
370 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
378 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
379 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
380 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
381 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
382 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
383 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
384 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
385 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
387 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
388 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
389 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
390 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
391 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
392 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
393 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
394 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
395 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
396 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
397 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
398 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
399 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
400 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
401 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
402 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
403 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
404 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
405 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
406 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
407 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
408 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
409 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
410 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
413 #ifdef CONFIG_SPL_BUILD
414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
419 #if defined(CONFIG_RAMBOOT_PBL)
420 #define CONFIG_SYS_RAMBOOT
423 #define CONFIG_MISC_INIT_R
425 #define CONFIG_HWCONFIG
427 /* define to use L1 as initial stack */
428 #define CONFIG_L1_INIT_RAM
429 #define CONFIG_SYS_INIT_RAM_LOCK
430 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
431 #ifdef CONFIG_PHYS_64BIT
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
434 /* The assembler doesn't like typecast */
435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
436 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
437 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
443 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
445 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
446 GENERATED_GBL_DATA_SIZE)
447 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
449 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
450 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
453 #define CONFIG_SYS_NS16550_SERIAL
454 #define CONFIG_SYS_NS16550_REG_SIZE 1
455 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
457 #define CONFIG_SYS_BAUDRATE_TABLE \
458 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
460 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
461 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
462 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
463 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
466 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
467 #define CONFIG_FSL_DIU_FB
468 #ifdef CONFIG_FSL_DIU_FB
469 #define CONFIG_FSL_DIU_CH7301
470 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
471 #define CONFIG_VIDEO_LOGO
472 #define CONFIG_VIDEO_BMP_LOGO
473 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
475 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
476 * disable empty flash sector detection, which is I/O-intensive.
478 #undef CONFIG_SYS_FLASH_EMPTY_INFO
483 #define CONFIG_SYS_I2C
484 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
485 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
486 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
487 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
488 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
489 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
490 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
492 #define I2C_MUX_PCA_ADDR 0x77
493 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
494 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
495 #define I2C_RETIMER_ADDR 0x18
497 /* I2C bus multiplexer */
498 #define I2C_MUX_CH_DEFAULT 0x8
499 #define I2C_MUX_CH_DIU 0xC
500 #define I2C_MUX_CH5 0xD
501 #define I2C_MUX_CH7 0xF
503 /* LDI/DVI Encoder for display */
504 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
505 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
511 #define CONFIG_RTC_DS3231 1
512 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
515 * eSPI - Enhanced SPI
517 #define CONFIG_SPI_FLASH_BAR
518 #define CONFIG_SF_DEFAULT_SPEED 10000000
519 #define CONFIG_SF_DEFAULT_MODE 0
523 * Memory space is mapped 1-1, but I/O space must start from 0.
525 #define CONFIG_PCIE1 /* PCIE controller 1 */
526 #define CONFIG_PCIE2 /* PCIE controller 2 */
527 #define CONFIG_PCIE3 /* PCIE controller 3 */
528 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
529 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
530 #define CONFIG_PCI_INDIRECT_BRIDGE
533 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
535 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
536 #ifdef CONFIG_PHYS_64BIT
537 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
538 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
540 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
541 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
543 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
544 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
545 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
549 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
551 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
554 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
556 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
557 #ifdef CONFIG_PHYS_64BIT
558 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
559 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
561 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
562 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
564 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
565 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
566 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
567 #ifdef CONFIG_PHYS_64BIT
568 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
570 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
572 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
575 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
577 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
578 #ifdef CONFIG_PHYS_64BIT
579 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
580 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
582 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
583 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
585 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
586 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
587 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
588 #ifdef CONFIG_PHYS_64BIT
589 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
591 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
593 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
596 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
597 #endif /* CONFIG_PCI */
602 #define CONFIG_FSL_SATA_V2
603 #ifdef CONFIG_FSL_SATA_V2
604 #define CONFIG_SYS_SATA_MAX_DEVICE 1
606 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
607 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
614 #define CONFIG_HAS_FSL_DR_USB
616 #ifdef CONFIG_HAS_FSL_DR_USB
617 #define CONFIG_USB_EHCI_FSL
618 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
625 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
629 #ifndef CONFIG_NOBQFMAN
630 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
631 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
632 #ifdef CONFIG_PHYS_64BIT
633 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
635 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
637 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
638 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
639 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
640 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
641 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
642 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
643 CONFIG_SYS_BMAN_CENA_SIZE)
644 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
645 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
646 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
647 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
648 #ifdef CONFIG_PHYS_64BIT
649 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
651 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
653 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
654 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
655 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
656 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
657 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
658 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
659 CONFIG_SYS_QMAN_CENA_SIZE)
660 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
661 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
663 #define CONFIG_SYS_DPAA_FMAN
667 /* Default address of microcode for the Linux FMan driver */
668 #if defined(CONFIG_SPIFLASH)
670 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
671 * env, so we got 0x110000.
673 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
674 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
675 #define CONFIG_SYS_QE_FW_ADDR 0x130000
676 #elif defined(CONFIG_SDCARD)
678 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
679 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
680 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
682 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
683 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
684 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
685 #elif defined(CONFIG_NAND)
686 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
687 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
688 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
689 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
691 * Slave has no ucode locally, it can fetch this from remote. When implementing
692 * in two corenet boards, slave's ucode could be stored in master's memory
693 * space, the address can be mapped from slave TLB->slave LAW->
694 * slave SRIO or PCIE outbound window->master inbound window->
695 * master LAW->the ucode address in master's memory space.
697 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
698 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
700 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
701 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
702 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
704 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
705 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
706 #endif /* CONFIG_NOBQFMAN */
708 #ifdef CONFIG_SYS_DPAA_FMAN
709 #define CONFIG_FMAN_ENET
710 #define CONFIG_PHYLIB_10G
711 #define CONFIG_PHY_VITESSE
712 #define CONFIG_PHY_REALTEK
713 #define CONFIG_PHY_TERANETICS
714 #define RGMII_PHY1_ADDR 0x1
715 #define RGMII_PHY2_ADDR 0x2
716 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
717 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
718 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
719 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
720 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
721 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
722 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
725 #ifdef CONFIG_FMAN_ENET
726 #define CONFIG_MII /* MII PHY management */
727 #define CONFIG_ETHPRIME "FM1@DTSEC4"
731 * Dynamic MTD Partition support with mtdparts
733 #ifdef CONFIG_MTD_NOR_FLASH
734 #define CONFIG_MTD_DEVICE
735 #define CONFIG_MTD_PARTITIONS
736 #define CONFIG_FLASH_CFI_MTD
742 #define CONFIG_LOADS_ECHO /* echo on for serial download */
743 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
746 * Miscellaneous configurable options
748 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
751 * For booting Linux, the board info and command line data
752 * have to be in the first 64 MB of memory, since this is
753 * the maximum mapped by the Linux kernel during initialization.
755 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
756 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
758 #ifdef CONFIG_CMD_KGDB
759 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
763 * Environment Configuration
765 #define CONFIG_ROOTPATH "/opt/nfsroot"
766 #define CONFIG_BOOTFILE "uImage"
767 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
768 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
769 #define __USB_PHY_TYPE utmi
771 #define CONFIG_EXTRA_ENV_SETTINGS \
772 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
773 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
774 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
775 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
776 "fdtfile=t1024qds/t1024qds.dtb\0" \
778 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
779 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
780 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
781 "tftpflash=tftpboot $loadaddr $uboot && " \
782 "protect off $ubootaddr +$filesize && " \
783 "erase $ubootaddr +$filesize && " \
784 "cp.b $loadaddr $ubootaddr $filesize && " \
785 "protect on $ubootaddr +$filesize && " \
786 "cmp.b $loadaddr $ubootaddr $filesize\0" \
787 "consoledev=ttyS0\0" \
788 "ramdiskaddr=2000000\0" \
792 #define CONFIG_LINUX \
793 "setenv bootargs root=/dev/ram rw " \
794 "console=$consoledev,$baudrate $othbootargs;" \
795 "setenv ramdiskaddr 0x02000000;" \
796 "setenv fdtaddr 0x00c00000;" \
797 "setenv loadaddr 0x1000000;" \
798 "bootm $loadaddr $ramdiskaddr $fdtaddr"
800 #define CONFIG_NFSBOOTCOMMAND \
801 "setenv bootargs root=/dev/nfs rw " \
802 "nfsroot=$serverip:$rootpath " \
803 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
804 "console=$consoledev,$baudrate $othbootargs;" \
805 "tftp $loadaddr $bootfile;" \
806 "tftp $fdtaddr $fdtfile;" \
807 "bootm $loadaddr - $fdtaddr"
809 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
811 #include <asm/fsl_secure_boot.h>
813 #endif /* __T1024QDS_H */