include/configs/T102xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 QDS board configuration file
   8  */
   9
  10 #ifndef __T1024QDS_H
  11 #define __T1024QDS_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 #define CONFIG_DEEP_SLEEP
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  31 #define CONFIG_SPL_FLUSH_IMAGE
  32 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  48 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  50 #define CONFIG_SPL_NAND_BOOT
  51 #endif
  52
  53 #ifdef CONFIG_SPIFLASH
  54 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  55 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  60 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  61 #ifndef CONFIG_SPL_BUILD
  62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  63 #endif
  64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  65 #define CONFIG_SPL_SPI_BOOT
  66 #endif
  67
  68 #ifdef CONFIG_SDCARD
  69 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  70 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  71 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  72 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  73 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  74 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  75 #ifndef CONFIG_SPL_BUILD
  76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  77 #endif
  78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  79 #define CONFIG_SPL_MMC_BOOT
  80 #endif
  81
  82 #endif /* CONFIG_RAMBOOT_PBL */
  83
  84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  85 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  86 #endif
  87
  88 #ifdef CONFIG_MTD_NOR_FLASH
  89 #define CONFIG_FLASH_CFI_DRIVER
  90 #define CONFIG_SYS_FLASH_CFI
  91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  92 #endif
  93
  94 /* PCIe Boot - Master */
  95 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  96 /*
  97  * for slave u-boot IMAGE instored in master memory space,
  98  * PHYS must be aligned based on the SIZE
  99  */
 100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 102 #ifdef CONFIG_PHYS_64BIT
 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 105 #else
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 108 #endif
 109 /*
 110  * for slave UCODE and ENV instored in master memory space,
 111  * PHYS must be aligned based on the SIZE
 112  */
 113 #ifdef CONFIG_PHYS_64BIT
 114 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 116 #else
 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 119 #endif
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 121 /* slave core release by master*/
 122 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 123 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 124
 125 /* PCIe Boot - Slave */
 126 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 127 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 128 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 129                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 130 /* Set 1M boot space for PCIe boot */
 131 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 132 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 133                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 134 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 135 #endif
 136
 137 #if defined(CONFIG_SPIFLASH)
 138 #define CONFIG_ENV_SPI_BUS              0
 139 #define CONFIG_ENV_SPI_CS               0
 140 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 141 #define CONFIG_ENV_SPI_MODE             0
 142 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 143 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 144 #define CONFIG_ENV_SECT_SIZE            0x10000
 145 #elif defined(CONFIG_SDCARD)
 146 #define CONFIG_SYS_MMC_ENV_DEV          0
 147 #define CONFIG_ENV_SIZE                 0x2000
 148 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 149 #elif defined(CONFIG_NAND)
 150 #define CONFIG_ENV_SIZE                 0x2000
 151 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 152 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 153 #define CONFIG_ENV_ADDR         0xffe20000
 154 #define CONFIG_ENV_SIZE         0x2000
 155 #elif defined(CONFIG_ENV_IS_NOWHERE)
 156 #define CONFIG_ENV_SIZE         0x2000
 157 #else
 158 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 159 #define CONFIG_ENV_SIZE         0x2000
 160 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 161 #endif
 162
 163 #ifndef __ASSEMBLY__
 164 unsigned long get_board_sys_clk(void);
 165 unsigned long get_board_ddr_clk(void);
 166 #endif
 167
 168 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 169 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 170
 171 /*
 172  * These can be toggled for performance analysis, otherwise use default.
 173  */
 174 #define CONFIG_SYS_CACHE_STASHING
 175 #define CONFIG_BACKSIDE_L2_CACHE
 176 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 177 #define CONFIG_BTB                      /* toggle branch predition */
 178 #define CONFIG_DDR_ECC
 179 #ifdef CONFIG_DDR_ECC
 180 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 181 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 182 #endif
 183
 184 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 185 #define CONFIG_SYS_MEMTEST_END          0x00400000
 186
 187 /*
 188  *  Config the L3 Cache as L3 SRAM
 189  */
 190 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 191 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 192 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 193 #ifdef CONFIG_RAMBOOT_PBL
 194 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 195 #endif
 196 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 197 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 198 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 199
 200 #ifdef CONFIG_PHYS_64BIT
 201 #define CONFIG_SYS_DCSRBAR              0xf0000000
 202 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 203 #endif
 204
 205 /* EEPROM */
 206 #define CONFIG_ID_EEPROM
 207 #define CONFIG_SYS_I2C_EEPROM_NXID
 208 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 209 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 213
 214 /*
 215  * DDR Setup
 216  */
 217 #define CONFIG_VERY_BIG_RAM
 218 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 219 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 220 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 221 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 222 #define CONFIG_DDR_SPD
 223
 224 #define CONFIG_SYS_SPD_BUS_NUM  0
 225 #define SPD_EEPROM_ADDRESS      0x51
 226
 227 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 228
 229 /*
 230  * IFC Definitions
 231  */
 232 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 233 #ifdef CONFIG_PHYS_64BIT
 234 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 235 #else
 236 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 237 #endif
 238
 239 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 240 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 241                                 + 0x8000000) | \
 242                                 CSPR_PORT_SIZE_16 | \
 243                                 CSPR_MSEL_NOR | \
 244                                 CSPR_V)
 245 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 246 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 247                                 CSPR_PORT_SIZE_16 | \
 248                                 CSPR_MSEL_NOR | \
 249                                 CSPR_V)
 250 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 251 /* NOR Flash Timing Params */
 252 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 253 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 254                                 FTIM0_NOR_TEADC(0x5) | \
 255                                 FTIM0_NOR_TEAHC(0x5))
 256 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 257                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 258                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 259 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 260                                 FTIM2_NOR_TCH(0x4) | \
 261                                 FTIM2_NOR_TWPH(0x0E) | \
 262                                 FTIM2_NOR_TWP(0x1c))
 263 #define CONFIG_SYS_NOR_FTIM3    0x0
 264
 265 #define CONFIG_SYS_FLASH_QUIET_TEST
 266 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 267
 268 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 269 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 270 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 271 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 272
 273 #define CONFIG_SYS_FLASH_EMPTY_INFO
 274 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 275                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 276 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 277 #define QIXIS_BASE              0xffdf0000
 278 #ifdef CONFIG_PHYS_64BIT
 279 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 280 #else
 281 #define QIXIS_BASE_PHYS         QIXIS_BASE
 282 #endif
 283 #define QIXIS_LBMAP_SWITCH              0x06
 284 #define QIXIS_LBMAP_MASK                0x0f
 285 #define QIXIS_LBMAP_SHIFT               0
 286 #define QIXIS_LBMAP_DFLTBANK            0x00
 287 #define QIXIS_LBMAP_ALTBANK             0x04
 288 #define QIXIS_RST_CTL_RESET             0x31
 289 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 290 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 291 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 292 #define QIXIS_RST_FORCE_MEM             0x01
 293
 294 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 295 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 296                                 | CSPR_PORT_SIZE_8 \
 297                                 | CSPR_MSEL_GPCM \
 298                                 | CSPR_V)
 299 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 300 #define CONFIG_SYS_CSOR3        0x0
 301 /* QIXIS Timing parameters for IFC CS3 */
 302 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 303                                         FTIM0_GPCM_TEADC(0x0e) | \
 304                                         FTIM0_GPCM_TEAHC(0x0e))
 305 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 306                                         FTIM1_GPCM_TRAD(0x3f))
 307 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 308                                         FTIM2_GPCM_TCH(0x8) | \
 309                                         FTIM2_GPCM_TWP(0x1f))
 310 #define CONFIG_SYS_CS3_FTIM3            0x0
 311
 312 #define CONFIG_NAND_FSL_IFC
 313 #define CONFIG_SYS_NAND_BASE            0xff800000
 314 #ifdef CONFIG_PHYS_64BIT
 315 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 316 #else
 317 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 318 #endif
 319 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 320 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 321                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 322                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 323                                 | CSPR_V)
 324 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 325
 326 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 327                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 328                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 329                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 330                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 331                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 332                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 333
 334 #define CONFIG_SYS_NAND_ONFI_DETECTION
 335
 336 /* ONFI NAND Flash mode0 Timing Params */
 337 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 338                                         FTIM0_NAND_TWP(0x18)   | \
 339                                         FTIM0_NAND_TWCHT(0x07) | \
 340                                         FTIM0_NAND_TWH(0x0a))
 341 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 342                                         FTIM1_NAND_TWBE(0x39)  | \
 343                                         FTIM1_NAND_TRR(0x0e)   | \
 344                                         FTIM1_NAND_TRP(0x18))
 345 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 346                                         FTIM2_NAND_TREH(0x0a) | \
 347                                         FTIM2_NAND_TWHRE(0x1e))
 348 #define CONFIG_SYS_NAND_FTIM3           0x0
 349
 350 #define CONFIG_SYS_NAND_DDR_LAW         11
 351 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 352 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 353
 354 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 355
 356 #if defined(CONFIG_NAND)
 357 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 358 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 359 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 360 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 361 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 362 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 363 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 364 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 365 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 366 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 367 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 368 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 369 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 370 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 371 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 372 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 373 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 374 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 375 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 376 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 377 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 378 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 379 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 380 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 381 #else
 382 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 383 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 384 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 385 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 386 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 387 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 388 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 389 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 390 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 391 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 392 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 393 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 394 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 395 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 396 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 397 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 398 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 399 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 400 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 401 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 402 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 403 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 404 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 405 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 406 #endif
 407
 408 #ifdef CONFIG_SPL_BUILD
 409 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 410 #else
 411 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 412 #endif
 413
 414 #if defined(CONFIG_RAMBOOT_PBL)
 415 #define CONFIG_SYS_RAMBOOT
 416 #endif
 417
 418 #define CONFIG_HWCONFIG
 419
 420 /* define to use L1 as initial stack */
 421 #define CONFIG_L1_INIT_RAM
 422 #define CONFIG_SYS_INIT_RAM_LOCK
 423 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 424 #ifdef CONFIG_PHYS_64BIT
 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 427 /* The assembler doesn't like typecast */
 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 429         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 430           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 431 #else
 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 435 #endif
 436 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 437
 438 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 439                                         GENERATED_GBL_DATA_SIZE)
 440 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 441
 442 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 443 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 444
 445 /* Serial Port */
 446 #define CONFIG_SYS_NS16550_SERIAL
 447 #define CONFIG_SYS_NS16550_REG_SIZE     1
 448 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 449
 450 #define CONFIG_SYS_BAUDRATE_TABLE       \
 451         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 452
 453 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 454 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 455 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 456 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 457
 458 /* Video */
 459 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 460 #define CONFIG_FSL_DIU_FB
 461 #ifdef CONFIG_FSL_DIU_FB
 462 #define CONFIG_FSL_DIU_CH7301
 463 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 464 #define CONFIG_VIDEO_LOGO
 465 #define CONFIG_VIDEO_BMP_LOGO
 466 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 467 /*
 468  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 469  * disable empty flash sector detection, which is I/O-intensive.
 470  */
 471 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 472 #endif
 473 #endif
 474
 475 /* I2C */
 476 #define CONFIG_SYS_I2C
 477 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 478 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 479 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 480 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 481 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 482 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 483 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 484
 485 #define I2C_MUX_PCA_ADDR                0x77
 486 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 487 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 488 #define I2C_RETIMER_ADDR                0x18
 489
 490 /* I2C bus multiplexer */
 491 #define I2C_MUX_CH_DEFAULT      0x8
 492 #define I2C_MUX_CH_DIU          0xC
 493 #define I2C_MUX_CH5             0xD
 494 #define I2C_MUX_CH7             0xF
 495
 496 /* LDI/DVI Encoder for display */
 497 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 498 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 499
 500 /*
 501  * RTC configuration
 502  */
 503 #define RTC
 504 #define CONFIG_RTC_DS3231       1
 505 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 506
 507 /*
 508  * eSPI - Enhanced SPI
 509  */
 510 #define CONFIG_SPI_FLASH_BAR
 511 #define CONFIG_SF_DEFAULT_SPEED  10000000
 512 #define CONFIG_SF_DEFAULT_MODE    0
 513
 514 /*
 515  * General PCIe
 516  * Memory space is mapped 1-1, but I/O space must start from 0.
 517  */
 518 #define CONFIG_PCIE1            /* PCIE controller 1 */
 519 #define CONFIG_PCIE2            /* PCIE controller 2 */
 520 #define CONFIG_PCIE3            /* PCIE controller 3 */
 521 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 522 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 523 #define CONFIG_PCI_INDIRECT_BRIDGE
 524
 525 #ifdef CONFIG_PCI
 526 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 527 #ifdef CONFIG_PCIE1
 528 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 529 #ifdef CONFIG_PHYS_64BIT
 530 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 531 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 532 #else
 533 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 534 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 535 #endif
 536 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 537 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 538 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 539 #ifdef CONFIG_PHYS_64BIT
 540 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 541 #else
 542 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 543 #endif
 544 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 545 #endif
 546
 547 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 548 #ifdef CONFIG_PCIE2
 549 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 550 #ifdef CONFIG_PHYS_64BIT
 551 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 552 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 553 #else
 554 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 555 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 556 #endif
 557 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 558 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 559 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 560 #ifdef CONFIG_PHYS_64BIT
 561 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 562 #else
 563 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 564 #endif
 565 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 566 #endif
 567
 568 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 569 #ifdef CONFIG_PCIE3
 570 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 571 #ifdef CONFIG_PHYS_64BIT
 572 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 573 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 574 #else
 575 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 576 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 577 #endif
 578 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 579 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 580 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 581 #ifdef CONFIG_PHYS_64BIT
 582 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 583 #else
 584 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 585 #endif
 586 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 587 #endif
 588
 589 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 590 #endif  /* CONFIG_PCI */
 591
 592 /*
 593  *SATA
 594  */
 595 #define CONFIG_FSL_SATA_V2
 596 #ifdef CONFIG_FSL_SATA_V2
 597 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 598 #define CONFIG_SATA1
 599 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 600 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 601 #define CONFIG_LBA48
 602 #endif
 603
 604 /*
 605  * USB
 606  */
 607 #define CONFIG_HAS_FSL_DR_USB
 608
 609 #ifdef CONFIG_HAS_FSL_DR_USB
 610 #define CONFIG_USB_EHCI_FSL
 611 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 612 #endif
 613
 614 /*
 615  * SDHC
 616  */
 617 #ifdef CONFIG_MMC
 618 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 619 #endif
 620
 621 /* Qman/Bman */
 622 #ifndef CONFIG_NOBQFMAN
 623 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 624 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 625 #ifdef CONFIG_PHYS_64BIT
 626 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 627 #else
 628 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 629 #endif
 630 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 631 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 632 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 633 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 634 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 635 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 636                                         CONFIG_SYS_BMAN_CENA_SIZE)
 637 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 638 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 639 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 640 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 641 #ifdef CONFIG_PHYS_64BIT
 642 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 643 #else
 644 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 645 #endif
 646 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 647 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 648 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 649 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 650 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 651 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 652                                         CONFIG_SYS_QMAN_CENA_SIZE)
 653 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 654 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 655
 656 #define CONFIG_SYS_DPAA_FMAN
 657
 658 #define CONFIG_QE
 659 /* Default address of microcode for the Linux FMan driver */
 660 #if defined(CONFIG_SPIFLASH)
 661 /*
 662  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 663  * env, so we got 0x110000.
 664  */
 665 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 666 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 667 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 668 #elif defined(CONFIG_SDCARD)
 669 /*
 670  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 671  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 672  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 673  */
 674 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 675 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 676 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 677 #elif defined(CONFIG_NAND)
 678 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 679 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 680 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 681 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 682 /*
 683  * Slave has no ucode locally, it can fetch this from remote. When implementing
 684  * in two corenet boards, slave's ucode could be stored in master's memory
 685  * space, the address can be mapped from slave TLB->slave LAW->
 686  * slave SRIO or PCIE outbound window->master inbound window->
 687  * master LAW->the ucode address in master's memory space.
 688  */
 689 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 690 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 691 #else
 692 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 693 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 694 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 695 #endif
 696 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 697 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 698 #endif /* CONFIG_NOBQFMAN */
 699
 700 #ifdef CONFIG_SYS_DPAA_FMAN
 701 #define CONFIG_FMAN_ENET
 702 #define CONFIG_PHYLIB_10G
 703 #define CONFIG_PHY_VITESSE
 704 #define CONFIG_PHY_REALTEK
 705 #define CONFIG_PHY_TERANETICS
 706 #define RGMII_PHY1_ADDR         0x1
 707 #define RGMII_PHY2_ADDR         0x2
 708 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 709 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 710 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 711 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 712 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 713 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 714 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 715 #endif
 716
 717 #ifdef CONFIG_FMAN_ENET
 718 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 719 #endif
 720
 721 /*
 722  * Dynamic MTD Partition support with mtdparts
 723  */
 724 #ifdef CONFIG_MTD_NOR_FLASH
 725 #define CONFIG_FLASH_CFI_MTD
 726 #endif
 727
 728 /*
 729  * Environment
 730  */
 731 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 732 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 733
 734 /*
 735  * Miscellaneous configurable options
 736  */
 737 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 738
 739 /*
 740  * For booting Linux, the board info and command line data
 741  * have to be in the first 64 MB of memory, since this is
 742  * the maximum mapped by the Linux kernel during initialization.
 743  */
 744 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 745 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 746
 747 #ifdef CONFIG_CMD_KGDB
 748 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 749 #endif
 750
 751 /*
 752  * Environment Configuration
 753  */
 754 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 755 #define CONFIG_BOOTFILE         "uImage"
 756 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 757 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 758 #define __USB_PHY_TYPE          utmi
 759
 760 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 761         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 762         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 763         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 764         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 765         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 766         "netdev=eth0\0"                                         \
 767         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 768         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 769         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 770         "tftpflash=tftpboot $loadaddr $uboot && "               \
 771         "protect off $ubootaddr +$filesize && "                 \
 772         "erase $ubootaddr +$filesize && "                       \
 773         "cp.b $loadaddr $ubootaddr $filesize && "               \
 774         "protect on $ubootaddr +$filesize && "                  \
 775         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 776         "consoledev=ttyS0\0"                                    \
 777         "ramdiskaddr=2000000\0"                                 \
 778         "fdtaddr=d00000\0"                                      \
 779         "bdev=sda3\0"
 780
 781 #define CONFIG_LINUX                                    \
 782         "setenv bootargs root=/dev/ram rw "             \
 783         "console=$consoledev,$baudrate $othbootargs;"   \
 784         "setenv ramdiskaddr 0x02000000;"                \
 785         "setenv fdtaddr 0x00c00000;"                    \
 786         "setenv loadaddr 0x1000000;"                    \
 787         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 788
 789 #define CONFIG_NFSBOOTCOMMAND                   \
 790         "setenv bootargs root=/dev/nfs rw "     \
 791         "nfsroot=$serverip:$rootpath "          \
 792         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 793         "console=$consoledev,$baudrate $othbootargs;"   \
 794         "tftp $loadaddr $bootfile;"             \
 795         "tftp $fdtaddr $fdtfile;"               \
 796         "bootm $loadaddr - $fdtaddr"
 797
 798 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 799
 800 #include <asm/fsl_secure_boot.h>
 801
 802 #endif  /* __T1024QDS_H */