1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 * T1024/T1023 QDS board configuration file
13 /* High Level Configuration Options */
14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
15 #define CONFIG_ENABLE_36BIT_PHYS
17 #ifdef CONFIG_PHYS_64BIT
18 #define CONFIG_ADDR_MAP 1
19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
25 #define CONFIG_ENV_OVERWRITE
27 #define CONFIG_DEEP_SLEEP
29 #ifdef CONFIG_RAMBOOT_PBL
30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_PAD_TO 0x40000
33 #define CONFIG_SPL_MAX_SIZE 0x28000
34 #define RESET_VECTOR_OFFSET 0x27FFC
35 #define BOOT_PAGE_OFFSET 0x27000
36 #ifdef CONFIG_SPL_BUILD
37 #define CONFIG_SPL_SKIP_RELOCATE
38 #define CONFIG_SPL_COMMON_INIT_DDR
39 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
42 #ifdef CONFIG_MTD_RAW_NAND
43 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
44 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
45 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
47 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
50 #ifdef CONFIG_SPIFLASH
51 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
52 #define CONFIG_SPL_SPI_FLASH_MINIMAL
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
57 #ifndef CONFIG_SPL_BUILD
58 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
64 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
65 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
66 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
67 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
68 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
69 #ifndef CONFIG_SPL_BUILD
70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
75 #endif /* CONFIG_RAMBOOT_PBL */
77 #ifndef CONFIG_RESET_VECTOR_ADDRESS
78 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
81 /* PCIe Boot - Master */
82 #define CONFIG_SRIO_PCIE_BOOT_MASTER
84 * for slave u-boot IMAGE instored in master memory space,
85 * PHYS must be aligned based on the SIZE
87 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
89 #ifdef CONFIG_PHYS_64BIT
90 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
91 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
93 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
97 * for slave UCODE and ENV instored in master memory space,
98 * PHYS must be aligned based on the SIZE
100 #ifdef CONFIG_PHYS_64BIT
101 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
102 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
104 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
105 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
107 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
108 /* slave core release by master*/
109 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
110 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
112 /* PCIe Boot - Slave */
113 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
114 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
115 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
116 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
117 /* Set 1M boot space for PCIe boot */
118 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
119 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
120 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
121 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
124 #if defined(CONFIG_SPIFLASH)
125 #elif defined(CONFIG_SDCARD)
126 #define CONFIG_SYS_MMC_ENV_DEV 0
130 unsigned long get_board_sys_clk(void);
131 unsigned long get_board_ddr_clk(void);
134 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
135 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
138 * These can be toggled for performance analysis, otherwise use default.
140 #define CONFIG_SYS_CACHE_STASHING
141 #define CONFIG_BACKSIDE_L2_CACHE
142 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
143 #define CONFIG_BTB /* toggle branch predition */
144 #define CONFIG_DDR_ECC
145 #ifdef CONFIG_DDR_ECC
146 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
147 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
150 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
151 #define CONFIG_SYS_MEMTEST_END 0x00400000
154 * Config the L3 Cache as L3 SRAM
156 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
157 #define CONFIG_SYS_L3_SIZE (256 << 10)
158 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
159 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
160 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
161 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
162 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
164 #ifdef CONFIG_PHYS_64BIT
165 #define CONFIG_SYS_DCSRBAR 0xf0000000
166 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
170 #define CONFIG_ID_EEPROM
171 #define CONFIG_SYS_I2C_EEPROM_NXID
172 #define CONFIG_SYS_EEPROM_BUS_NUM 0
173 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
181 #define CONFIG_VERY_BIG_RAM
182 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
183 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
184 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
185 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
186 #define CONFIG_DDR_SPD
188 #define CONFIG_SYS_SPD_BUS_NUM 0
189 #define SPD_EEPROM_ADDRESS 0x51
191 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
196 #define CONFIG_SYS_FLASH_BASE 0xe0000000
197 #ifdef CONFIG_PHYS_64BIT
198 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
200 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
203 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
204 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
206 CSPR_PORT_SIZE_16 | \
209 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
210 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
211 CSPR_PORT_SIZE_16 | \
214 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
215 /* NOR Flash Timing Params */
216 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
217 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
218 FTIM0_NOR_TEADC(0x5) | \
219 FTIM0_NOR_TEAHC(0x5))
220 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
221 FTIM1_NOR_TRAD_NOR(0x1A) |\
222 FTIM1_NOR_TSEQRAD_NOR(0x13))
223 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
224 FTIM2_NOR_TCH(0x4) | \
225 FTIM2_NOR_TWPH(0x0E) | \
227 #define CONFIG_SYS_NOR_FTIM3 0x0
229 #define CONFIG_SYS_FLASH_QUIET_TEST
230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
232 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
233 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
237 #define CONFIG_SYS_FLASH_EMPTY_INFO
238 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
239 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
240 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
241 #define QIXIS_BASE 0xffdf0000
242 #ifdef CONFIG_PHYS_64BIT
243 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
245 #define QIXIS_BASE_PHYS QIXIS_BASE
247 #define QIXIS_LBMAP_SWITCH 0x06
248 #define QIXIS_LBMAP_MASK 0x0f
249 #define QIXIS_LBMAP_SHIFT 0
250 #define QIXIS_LBMAP_DFLTBANK 0x00
251 #define QIXIS_LBMAP_ALTBANK 0x04
252 #define QIXIS_RST_CTL_RESET 0x31
253 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
254 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
255 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
256 #define QIXIS_RST_FORCE_MEM 0x01
258 #define CONFIG_SYS_CSPR3_EXT (0xf)
259 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
263 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
264 #define CONFIG_SYS_CSOR3 0x0
265 /* QIXIS Timing parameters for IFC CS3 */
266 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
267 FTIM0_GPCM_TEADC(0x0e) | \
268 FTIM0_GPCM_TEAHC(0x0e))
269 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
270 FTIM1_GPCM_TRAD(0x3f))
271 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
272 FTIM2_GPCM_TCH(0x8) | \
273 FTIM2_GPCM_TWP(0x1f))
274 #define CONFIG_SYS_CS3_FTIM3 0x0
276 #define CONFIG_NAND_FSL_IFC
277 #define CONFIG_SYS_NAND_BASE 0xff800000
278 #ifdef CONFIG_PHYS_64BIT
279 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
281 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
283 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
284 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
285 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
286 | CSPR_MSEL_NAND /* MSEL = NAND */ \
288 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
290 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
291 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
292 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
293 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
294 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
295 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
296 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
298 #define CONFIG_SYS_NAND_ONFI_DETECTION
300 /* ONFI NAND Flash mode0 Timing Params */
301 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
302 FTIM0_NAND_TWP(0x18) | \
303 FTIM0_NAND_TWCHT(0x07) | \
304 FTIM0_NAND_TWH(0x0a))
305 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
306 FTIM1_NAND_TWBE(0x39) | \
307 FTIM1_NAND_TRR(0x0e) | \
308 FTIM1_NAND_TRP(0x18))
309 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
310 FTIM2_NAND_TREH(0x0a) | \
311 FTIM2_NAND_TWHRE(0x1e))
312 #define CONFIG_SYS_NAND_FTIM3 0x0
314 #define CONFIG_SYS_NAND_DDR_LAW 11
315 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
316 #define CONFIG_SYS_MAX_NAND_DEVICE 1
318 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
320 #if defined(CONFIG_MTD_RAW_NAND)
321 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
322 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
323 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
324 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
325 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
326 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
327 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
328 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
329 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
330 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
331 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
332 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
333 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
334 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
335 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
336 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
337 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
338 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
339 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
340 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
341 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
342 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
343 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
344 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
346 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
347 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
348 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
349 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
350 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
351 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
352 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
353 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
354 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
355 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
356 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
357 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
358 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
359 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
360 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
361 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
362 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
363 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
364 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
365 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
366 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
367 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
368 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
369 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
372 #ifdef CONFIG_SPL_BUILD
373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
378 #if defined(CONFIG_RAMBOOT_PBL)
379 #define CONFIG_SYS_RAMBOOT
382 #define CONFIG_HWCONFIG
384 /* define to use L1 as initial stack */
385 #define CONFIG_L1_INIT_RAM
386 #define CONFIG_SYS_INIT_RAM_LOCK
387 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
388 #ifdef CONFIG_PHYS_64BIT
389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
391 /* The assembler doesn't like typecast */
392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
393 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
394 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
400 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
402 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
403 GENERATED_GBL_DATA_SIZE)
404 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
406 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
407 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
410 #define CONFIG_SYS_NS16550_SERIAL
411 #define CONFIG_SYS_NS16550_REG_SIZE 1
412 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
414 #define CONFIG_SYS_BAUDRATE_TABLE \
415 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
417 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
418 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
419 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
420 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
423 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
424 #define CONFIG_FSL_DIU_FB
425 #ifdef CONFIG_FSL_DIU_FB
426 #define CONFIG_FSL_DIU_CH7301
427 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
428 #define CONFIG_VIDEO_LOGO
429 #define CONFIG_VIDEO_BMP_LOGO
430 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
432 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
433 * disable empty flash sector detection, which is I/O-intensive.
435 #undef CONFIG_SYS_FLASH_EMPTY_INFO
440 #define CONFIG_SYS_I2C
441 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
442 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
443 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
444 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
445 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
446 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
447 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
449 #define I2C_MUX_PCA_ADDR 0x77
450 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
451 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
452 #define I2C_RETIMER_ADDR 0x18
454 /* I2C bus multiplexer */
455 #define I2C_MUX_CH_DEFAULT 0x8
456 #define I2C_MUX_CH_DIU 0xC
457 #define I2C_MUX_CH5 0xD
458 #define I2C_MUX_CH7 0xF
460 /* LDI/DVI Encoder for display */
461 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
462 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
468 #define CONFIG_RTC_DS3231 1
469 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
472 * eSPI - Enhanced SPI
477 * Memory space is mapped 1-1, but I/O space must start from 0.
479 #define CONFIG_PCIE1 /* PCIE controller 1 */
480 #define CONFIG_PCIE2 /* PCIE controller 2 */
481 #define CONFIG_PCIE3 /* PCIE controller 3 */
482 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
483 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
484 #define CONFIG_PCI_INDIRECT_BRIDGE
487 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
489 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
490 #ifdef CONFIG_PHYS_64BIT
491 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
492 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
494 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
495 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
497 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
498 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
499 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
500 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
503 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
508 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
510 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
511 #ifdef CONFIG_PHYS_64BIT
512 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
513 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
515 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
516 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
518 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
519 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
520 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
521 #ifdef CONFIG_PHYS_64BIT
522 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
524 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
526 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
529 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
531 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
532 #ifdef CONFIG_PHYS_64BIT
533 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
534 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
536 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
537 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
539 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
540 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
541 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
542 #ifdef CONFIG_PHYS_64BIT
543 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
545 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
547 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
550 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
551 #endif /* CONFIG_PCI */
556 #define CONFIG_FSL_SATA_V2
557 #ifdef CONFIG_FSL_SATA_V2
558 #define CONFIG_SYS_SATA_MAX_DEVICE 1
560 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
561 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
568 #define CONFIG_HAS_FSL_DR_USB
570 #ifdef CONFIG_HAS_FSL_DR_USB
571 #define CONFIG_USB_EHCI_FSL
572 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
579 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
583 #ifndef CONFIG_NOBQFMAN
584 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
585 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
586 #ifdef CONFIG_PHYS_64BIT
587 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
589 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
591 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
592 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
593 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
594 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
595 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
596 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
597 CONFIG_SYS_BMAN_CENA_SIZE)
598 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
599 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
600 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
601 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
602 #ifdef CONFIG_PHYS_64BIT
603 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
605 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
607 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
608 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
609 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
610 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
611 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
612 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
613 CONFIG_SYS_QMAN_CENA_SIZE)
614 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
615 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
617 #define CONFIG_SYS_DPAA_FMAN
619 /* Default address of microcode for the Linux FMan driver */
620 #if defined(CONFIG_SPIFLASH)
622 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
623 * env, so we got 0x110000.
625 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
626 #define CONFIG_SYS_QE_FW_ADDR 0x130000
627 #elif defined(CONFIG_SDCARD)
629 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
630 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
631 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
633 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
634 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
635 #elif defined(CONFIG_MTD_RAW_NAND)
636 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
637 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
638 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
640 * Slave has no ucode locally, it can fetch this from remote. When implementing
641 * in two corenet boards, slave's ucode could be stored in master's memory
642 * space, the address can be mapped from slave TLB->slave LAW->
643 * slave SRIO or PCIE outbound window->master inbound window->
644 * master LAW->the ucode address in master's memory space.
646 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
648 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
649 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
651 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
652 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
653 #endif /* CONFIG_NOBQFMAN */
655 #ifdef CONFIG_SYS_DPAA_FMAN
656 #define CONFIG_PHYLIB_10G
657 #define CONFIG_PHY_VITESSE
658 #define CONFIG_PHY_REALTEK
659 #define CONFIG_PHY_TERANETICS
660 #define RGMII_PHY1_ADDR 0x1
661 #define RGMII_PHY2_ADDR 0x2
662 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
663 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
664 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
665 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
666 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
667 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
668 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
671 #ifdef CONFIG_FMAN_ENET
672 #define CONFIG_ETHPRIME "FM1@DTSEC4"
676 * Dynamic MTD Partition support with mtdparts
682 #define CONFIG_LOADS_ECHO /* echo on for serial download */
683 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
686 * Miscellaneous configurable options
688 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
691 * For booting Linux, the board info and command line data
692 * have to be in the first 64 MB of memory, since this is
693 * the maximum mapped by the Linux kernel during initialization.
695 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
696 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
698 #ifdef CONFIG_CMD_KGDB
699 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
703 * Environment Configuration
705 #define CONFIG_ROOTPATH "/opt/nfsroot"
706 #define CONFIG_BOOTFILE "uImage"
707 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
708 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
709 #define __USB_PHY_TYPE utmi
711 #define CONFIG_EXTRA_ENV_SETTINGS \
712 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
713 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
714 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
715 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
716 "fdtfile=t1024qds/t1024qds.dtb\0" \
718 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
719 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
720 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
721 "tftpflash=tftpboot $loadaddr $uboot && " \
722 "protect off $ubootaddr +$filesize && " \
723 "erase $ubootaddr +$filesize && " \
724 "cp.b $loadaddr $ubootaddr $filesize && " \
725 "protect on $ubootaddr +$filesize && " \
726 "cmp.b $loadaddr $ubootaddr $filesize\0" \
727 "consoledev=ttyS0\0" \
728 "ramdiskaddr=2000000\0" \
732 #define CONFIG_LINUX \
733 "setenv bootargs root=/dev/ram rw " \
734 "console=$consoledev,$baudrate $othbootargs;" \
735 "setenv ramdiskaddr 0x02000000;" \
736 "setenv fdtaddr 0x00c00000;" \
737 "setenv loadaddr 0x1000000;" \
738 "bootm $loadaddr $ramdiskaddr $fdtaddr"
740 #define CONFIG_NFSBOOTCOMMAND \
741 "setenv bootargs root=/dev/nfs rw " \
742 "nfsroot=$serverip:$rootpath " \
743 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
744 "console=$consoledev,$baudrate $othbootargs;" \
745 "tftp $loadaddr $bootfile;" \
746 "tftp $fdtaddr $fdtfile;" \
747 "bootm $loadaddr - $fdtaddr"
749 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
751 #include <asm/fsl_secure_boot.h>
753 #endif /* __T1024QDS_H */