Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / T102xQDS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T1024/T1023 QDS board configuration file
8  */
9
10 #ifndef __T1024QDS_H
11 #define __T1024QDS_H
12
13 /* High Level Configuration Options */
14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
15 #define CONFIG_ENABLE_36BIT_PHYS
16
17 #ifdef CONFIG_PHYS_64BIT
18 #define CONFIG_ADDR_MAP         1
19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
20 #endif
21
22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
24
25 #define CONFIG_ENV_OVERWRITE
26
27 #define CONFIG_DEEP_SLEEP
28
29 #ifdef CONFIG_RAMBOOT_PBL
30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_PAD_TO               0x40000
33 #define CONFIG_SPL_MAX_SIZE             0x28000
34 #define RESET_VECTOR_OFFSET             0x27FFC
35 #define BOOT_PAGE_OFFSET                0x27000
36 #ifdef CONFIG_SPL_BUILD
37 #define CONFIG_SPL_SKIP_RELOCATE
38 #define CONFIG_SPL_COMMON_INIT_DDR
39 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40 #endif
41
42 #ifdef CONFIG_NAND
43 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
44 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
45 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
47 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
49 #define CONFIG_SPL_NAND_BOOT
50 #endif
51
52 #ifdef CONFIG_SPIFLASH
53 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
59 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
60 #ifndef CONFIG_SPL_BUILD
61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
62 #endif
63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
64 #define CONFIG_SPL_SPI_BOOT
65 #endif
66
67 #ifdef CONFIG_SDCARD
68 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
69 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
70 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
71 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
72 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
73 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
74 #ifndef CONFIG_SPL_BUILD
75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
76 #endif
77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
78 #define CONFIG_SPL_MMC_BOOT
79 #endif
80
81 #endif /* CONFIG_RAMBOOT_PBL */
82
83 #ifndef CONFIG_RESET_VECTOR_ADDRESS
84 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
85 #endif
86
87 /* PCIe Boot - Master */
88 #define CONFIG_SRIO_PCIE_BOOT_MASTER
89 /*
90  * for slave u-boot IMAGE instored in master memory space,
91  * PHYS must be aligned based on the SIZE
92  */
93 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
95 #ifdef CONFIG_PHYS_64BIT
96 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
97 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
98 #else
99 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
101 #endif
102 /*
103  * for slave UCODE and ENV instored in master memory space,
104  * PHYS must be aligned based on the SIZE
105  */
106 #ifdef CONFIG_PHYS_64BIT
107 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
109 #else
110 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
111 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
112 #endif
113 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
114 /* slave core release by master*/
115 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
116 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
117
118 /* PCIe Boot - Slave */
119 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
120 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
121 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
122                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
123 /* Set 1M boot space for PCIe boot */
124 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
125 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
126                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
127 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
128 #endif
129
130 #if defined(CONFIG_SPIFLASH)
131 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
132 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
133 #define CONFIG_ENV_SECT_SIZE            0x10000
134 #elif defined(CONFIG_SDCARD)
135 #define CONFIG_SYS_MMC_ENV_DEV          0
136 #define CONFIG_ENV_SIZE                 0x2000
137 #define CONFIG_ENV_OFFSET               (512 * 0x800)
138 #elif defined(CONFIG_NAND)
139 #define CONFIG_ENV_SIZE                 0x2000
140 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
141 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
142 #define CONFIG_ENV_ADDR         0xffe20000
143 #define CONFIG_ENV_SIZE         0x2000
144 #elif defined(CONFIG_ENV_IS_NOWHERE)
145 #define CONFIG_ENV_SIZE         0x2000
146 #else
147 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
148 #define CONFIG_ENV_SIZE         0x2000
149 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
150 #endif
151
152 #ifndef __ASSEMBLY__
153 unsigned long get_board_sys_clk(void);
154 unsigned long get_board_ddr_clk(void);
155 #endif
156
157 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
158 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
159
160 /*
161  * These can be toggled for performance analysis, otherwise use default.
162  */
163 #define CONFIG_SYS_CACHE_STASHING
164 #define CONFIG_BACKSIDE_L2_CACHE
165 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
166 #define CONFIG_BTB                      /* toggle branch predition */
167 #define CONFIG_DDR_ECC
168 #ifdef CONFIG_DDR_ECC
169 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
170 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
171 #endif
172
173 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
174 #define CONFIG_SYS_MEMTEST_END          0x00400000
175
176 /*
177  *  Config the L3 Cache as L3 SRAM
178  */
179 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
180 #define CONFIG_SYS_L3_SIZE              (256 << 10)
181 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
182 #ifdef CONFIG_RAMBOOT_PBL
183 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
184 #endif
185 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
186 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
187 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
188
189 #ifdef CONFIG_PHYS_64BIT
190 #define CONFIG_SYS_DCSRBAR              0xf0000000
191 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
192 #endif
193
194 /* EEPROM */
195 #define CONFIG_ID_EEPROM
196 #define CONFIG_SYS_I2C_EEPROM_NXID
197 #define CONFIG_SYS_EEPROM_BUS_NUM       0
198 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
202
203 /*
204  * DDR Setup
205  */
206 #define CONFIG_VERY_BIG_RAM
207 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
208 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
209 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
210 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
211 #define CONFIG_DDR_SPD
212
213 #define CONFIG_SYS_SPD_BUS_NUM  0
214 #define SPD_EEPROM_ADDRESS      0x51
215
216 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
217
218 /*
219  * IFC Definitions
220  */
221 #define CONFIG_SYS_FLASH_BASE   0xe0000000
222 #ifdef CONFIG_PHYS_64BIT
223 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
224 #else
225 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
226 #endif
227
228 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
229 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
230                                 + 0x8000000) | \
231                                 CSPR_PORT_SIZE_16 | \
232                                 CSPR_MSEL_NOR | \
233                                 CSPR_V)
234 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
235 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
236                                 CSPR_PORT_SIZE_16 | \
237                                 CSPR_MSEL_NOR | \
238                                 CSPR_V)
239 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
240 /* NOR Flash Timing Params */
241 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
242 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
243                                 FTIM0_NOR_TEADC(0x5) | \
244                                 FTIM0_NOR_TEAHC(0x5))
245 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
246                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
247                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
248 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
249                                 FTIM2_NOR_TCH(0x4) | \
250                                 FTIM2_NOR_TWPH(0x0E) | \
251                                 FTIM2_NOR_TWP(0x1c))
252 #define CONFIG_SYS_NOR_FTIM3    0x0
253
254 #define CONFIG_SYS_FLASH_QUIET_TEST
255 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
256
257 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
258 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
259 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
260 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
261
262 #define CONFIG_SYS_FLASH_EMPTY_INFO
263 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
264                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
265 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
266 #define QIXIS_BASE              0xffdf0000
267 #ifdef CONFIG_PHYS_64BIT
268 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
269 #else
270 #define QIXIS_BASE_PHYS         QIXIS_BASE
271 #endif
272 #define QIXIS_LBMAP_SWITCH              0x06
273 #define QIXIS_LBMAP_MASK                0x0f
274 #define QIXIS_LBMAP_SHIFT               0
275 #define QIXIS_LBMAP_DFLTBANK            0x00
276 #define QIXIS_LBMAP_ALTBANK             0x04
277 #define QIXIS_RST_CTL_RESET             0x31
278 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
279 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
280 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
281 #define QIXIS_RST_FORCE_MEM             0x01
282
283 #define CONFIG_SYS_CSPR3_EXT    (0xf)
284 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
285                                 | CSPR_PORT_SIZE_8 \
286                                 | CSPR_MSEL_GPCM \
287                                 | CSPR_V)
288 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
289 #define CONFIG_SYS_CSOR3        0x0
290 /* QIXIS Timing parameters for IFC CS3 */
291 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
292                                         FTIM0_GPCM_TEADC(0x0e) | \
293                                         FTIM0_GPCM_TEAHC(0x0e))
294 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
295                                         FTIM1_GPCM_TRAD(0x3f))
296 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
297                                         FTIM2_GPCM_TCH(0x8) | \
298                                         FTIM2_GPCM_TWP(0x1f))
299 #define CONFIG_SYS_CS3_FTIM3            0x0
300
301 #define CONFIG_NAND_FSL_IFC
302 #define CONFIG_SYS_NAND_BASE            0xff800000
303 #ifdef CONFIG_PHYS_64BIT
304 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
305 #else
306 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
307 #endif
308 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
309 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
310                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
311                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
312                                 | CSPR_V)
313 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
314
315 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
316                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
317                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
318                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
319                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
320                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
321                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
322
323 #define CONFIG_SYS_NAND_ONFI_DETECTION
324
325 /* ONFI NAND Flash mode0 Timing Params */
326 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
327                                         FTIM0_NAND_TWP(0x18)   | \
328                                         FTIM0_NAND_TWCHT(0x07) | \
329                                         FTIM0_NAND_TWH(0x0a))
330 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
331                                         FTIM1_NAND_TWBE(0x39)  | \
332                                         FTIM1_NAND_TRR(0x0e)   | \
333                                         FTIM1_NAND_TRP(0x18))
334 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
335                                         FTIM2_NAND_TREH(0x0a) | \
336                                         FTIM2_NAND_TWHRE(0x1e))
337 #define CONFIG_SYS_NAND_FTIM3           0x0
338
339 #define CONFIG_SYS_NAND_DDR_LAW         11
340 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
341 #define CONFIG_SYS_MAX_NAND_DEVICE      1
342
343 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
344
345 #if defined(CONFIG_NAND)
346 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
347 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
348 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
349 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
350 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
351 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
352 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
353 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
354 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
355 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
356 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
357 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
358 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
359 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
360 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
361 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
362 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
363 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
364 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
365 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
366 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
367 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
368 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
369 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
370 #else
371 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
372 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
373 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
374 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
375 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
376 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
377 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
378 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
379 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
380 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
381 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
382 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
383 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
384 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
385 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
386 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
387 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
388 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
389 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
390 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
391 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
392 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
393 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
394 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
395 #endif
396
397 #ifdef CONFIG_SPL_BUILD
398 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
399 #else
400 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
401 #endif
402
403 #if defined(CONFIG_RAMBOOT_PBL)
404 #define CONFIG_SYS_RAMBOOT
405 #endif
406
407 #define CONFIG_HWCONFIG
408
409 /* define to use L1 as initial stack */
410 #define CONFIG_L1_INIT_RAM
411 #define CONFIG_SYS_INIT_RAM_LOCK
412 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
416 /* The assembler doesn't like typecast */
417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
418         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
419           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
420 #else
421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
424 #endif
425 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
426
427 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
428                                         GENERATED_GBL_DATA_SIZE)
429 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
430
431 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
432 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
433
434 /* Serial Port */
435 #define CONFIG_SYS_NS16550_SERIAL
436 #define CONFIG_SYS_NS16550_REG_SIZE     1
437 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
438
439 #define CONFIG_SYS_BAUDRATE_TABLE       \
440         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
441
442 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
443 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
444 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
445 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
446
447 /* Video */
448 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
449 #define CONFIG_FSL_DIU_FB
450 #ifdef CONFIG_FSL_DIU_FB
451 #define CONFIG_FSL_DIU_CH7301
452 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
453 #define CONFIG_VIDEO_LOGO
454 #define CONFIG_VIDEO_BMP_LOGO
455 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
456 /*
457  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
458  * disable empty flash sector detection, which is I/O-intensive.
459  */
460 #undef CONFIG_SYS_FLASH_EMPTY_INFO
461 #endif
462 #endif
463
464 /* I2C */
465 #define CONFIG_SYS_I2C
466 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
467 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
468 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
469 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
470 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
471 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
472 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
473
474 #define I2C_MUX_PCA_ADDR                0x77
475 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
476 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
477 #define I2C_RETIMER_ADDR                0x18
478
479 /* I2C bus multiplexer */
480 #define I2C_MUX_CH_DEFAULT      0x8
481 #define I2C_MUX_CH_DIU          0xC
482 #define I2C_MUX_CH5             0xD
483 #define I2C_MUX_CH7             0xF
484
485 /* LDI/DVI Encoder for display */
486 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
487 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
488
489 /*
490  * RTC configuration
491  */
492 #define RTC
493 #define CONFIG_RTC_DS3231       1
494 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
495
496 /*
497  * eSPI - Enhanced SPI
498  */
499
500 /*
501  * General PCIe
502  * Memory space is mapped 1-1, but I/O space must start from 0.
503  */
504 #define CONFIG_PCIE1            /* PCIE controller 1 */
505 #define CONFIG_PCIE2            /* PCIE controller 2 */
506 #define CONFIG_PCIE3            /* PCIE controller 3 */
507 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
508 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
509 #define CONFIG_PCI_INDIRECT_BRIDGE
510
511 #ifdef CONFIG_PCI
512 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
513 #ifdef CONFIG_PCIE1
514 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
515 #ifdef CONFIG_PHYS_64BIT
516 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
517 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
518 #else
519 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
520 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
521 #endif
522 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
523 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
524 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
525 #ifdef CONFIG_PHYS_64BIT
526 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
527 #else
528 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
529 #endif
530 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
531 #endif
532
533 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
534 #ifdef CONFIG_PCIE2
535 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
536 #ifdef CONFIG_PHYS_64BIT
537 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
538 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
539 #else
540 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
541 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
542 #endif
543 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
544 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
545 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
548 #else
549 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
550 #endif
551 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
552 #endif
553
554 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
555 #ifdef CONFIG_PCIE3
556 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
557 #ifdef CONFIG_PHYS_64BIT
558 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
559 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
560 #else
561 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
562 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
563 #endif
564 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
565 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
566 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
567 #ifdef CONFIG_PHYS_64BIT
568 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
569 #else
570 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
571 #endif
572 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
573 #endif
574
575 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
576 #endif  /* CONFIG_PCI */
577
578 /*
579  *SATA
580  */
581 #define CONFIG_FSL_SATA_V2
582 #ifdef CONFIG_FSL_SATA_V2
583 #define CONFIG_SYS_SATA_MAX_DEVICE      1
584 #define CONFIG_SATA1
585 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
586 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
587 #define CONFIG_LBA48
588 #endif
589
590 /*
591  * USB
592  */
593 #define CONFIG_HAS_FSL_DR_USB
594
595 #ifdef CONFIG_HAS_FSL_DR_USB
596 #define CONFIG_USB_EHCI_FSL
597 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
598 #endif
599
600 /*
601  * SDHC
602  */
603 #ifdef CONFIG_MMC
604 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
605 #endif
606
607 /* Qman/Bman */
608 #ifndef CONFIG_NOBQFMAN
609 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
610 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
611 #ifdef CONFIG_PHYS_64BIT
612 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
613 #else
614 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
615 #endif
616 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
617 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
618 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
619 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
620 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
621 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
622                                         CONFIG_SYS_BMAN_CENA_SIZE)
623 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
624 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
625 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
626 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
627 #ifdef CONFIG_PHYS_64BIT
628 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
629 #else
630 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
631 #endif
632 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
633 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
634 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
635 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
636 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
637 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
638                                         CONFIG_SYS_QMAN_CENA_SIZE)
639 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
640 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
641
642 #define CONFIG_SYS_DPAA_FMAN
643
644 #define CONFIG_QE
645 /* Default address of microcode for the Linux FMan driver */
646 #if defined(CONFIG_SPIFLASH)
647 /*
648  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
649  * env, so we got 0x110000.
650  */
651 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
652 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
653 #define CONFIG_SYS_QE_FW_ADDR   0x130000
654 #elif defined(CONFIG_SDCARD)
655 /*
656  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
657  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
658  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
659  */
660 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
661 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
662 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
663 #elif defined(CONFIG_NAND)
664 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
665 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
666 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
667 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
668 /*
669  * Slave has no ucode locally, it can fetch this from remote. When implementing
670  * in two corenet boards, slave's ucode could be stored in master's memory
671  * space, the address can be mapped from slave TLB->slave LAW->
672  * slave SRIO or PCIE outbound window->master inbound window->
673  * master LAW->the ucode address in master's memory space.
674  */
675 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
676 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
677 #else
678 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
679 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
680 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
681 #endif
682 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
683 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
684 #endif /* CONFIG_NOBQFMAN */
685
686 #ifdef CONFIG_SYS_DPAA_FMAN
687 #define CONFIG_FMAN_ENET
688 #define CONFIG_PHYLIB_10G
689 #define CONFIG_PHY_VITESSE
690 #define CONFIG_PHY_REALTEK
691 #define CONFIG_PHY_TERANETICS
692 #define RGMII_PHY1_ADDR         0x1
693 #define RGMII_PHY2_ADDR         0x2
694 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
695 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
696 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
697 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
698 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
699 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
700 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
701 #endif
702
703 #ifdef CONFIG_FMAN_ENET
704 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
705 #endif
706
707 /*
708  * Dynamic MTD Partition support with mtdparts
709  */
710
711 /*
712  * Environment
713  */
714 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
715 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
716
717 /*
718  * Miscellaneous configurable options
719  */
720 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
721
722 /*
723  * For booting Linux, the board info and command line data
724  * have to be in the first 64 MB of memory, since this is
725  * the maximum mapped by the Linux kernel during initialization.
726  */
727 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
728 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
729
730 #ifdef CONFIG_CMD_KGDB
731 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
732 #endif
733
734 /*
735  * Environment Configuration
736  */
737 #define CONFIG_ROOTPATH         "/opt/nfsroot"
738 #define CONFIG_BOOTFILE         "uImage"
739 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
740 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
741 #define __USB_PHY_TYPE          utmi
742
743 #define CONFIG_EXTRA_ENV_SETTINGS                               \
744         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
745         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
746         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
747         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
748         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
749         "netdev=eth0\0"                                         \
750         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
751         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
752         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
753         "tftpflash=tftpboot $loadaddr $uboot && "               \
754         "protect off $ubootaddr +$filesize && "                 \
755         "erase $ubootaddr +$filesize && "                       \
756         "cp.b $loadaddr $ubootaddr $filesize && "               \
757         "protect on $ubootaddr +$filesize && "                  \
758         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
759         "consoledev=ttyS0\0"                                    \
760         "ramdiskaddr=2000000\0"                                 \
761         "fdtaddr=d00000\0"                                      \
762         "bdev=sda3\0"
763
764 #define CONFIG_LINUX                                    \
765         "setenv bootargs root=/dev/ram rw "             \
766         "console=$consoledev,$baudrate $othbootargs;"   \
767         "setenv ramdiskaddr 0x02000000;"                \
768         "setenv fdtaddr 0x00c00000;"                    \
769         "setenv loadaddr 0x1000000;"                    \
770         "bootm $loadaddr $ramdiskaddr $fdtaddr"
771
772 #define CONFIG_NFSBOOTCOMMAND                   \
773         "setenv bootargs root=/dev/nfs rw "     \
774         "nfsroot=$serverip:$rootpath "          \
775         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
776         "console=$consoledev,$baudrate $othbootargs;"   \
777         "tftp $loadaddr $bootfile;"             \
778         "tftp $fdtaddr $fdtfile;"               \
779         "bootm $loadaddr - $fdtaddr"
780
781 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
782
783 #include <asm/fsl_secure_boot.h>
784
785 #endif  /* __T1024QDS_H */