2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
38 #define CONFIG_MPC824X 1
39 #define CONFIG_MPC8245 1
40 #define CONFIG_SANDPOINT 1
48 #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
49 #define CONFIG_BAUDRATE 9600
50 #define CONFIG_DRAM_SPEED 100 /* MHz */
52 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
56 * Command line configuration.
58 #include <config_cmd_default.h>
60 #define CONFIG_CMD_DHCP
61 #define CONFIG_CMD_ELF
62 #define CONFIG_CMD_I2C
63 #define CONFIG_CMD_EEPROM
64 #define CONFIG_CMD_NFS
65 #define CONFIG_CMD_PCI
66 #define CONFIG_CMD_SNTP
70 * Miscellaneous configurable options
72 #define CFG_LONGHELP 1 /* undef to save memory */
73 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
74 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
75 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
76 #define CFG_MAXARGS 16 /* max number of command args */
77 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
78 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
79 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
81 /*-----------------------------------------------------------------------
83 *-----------------------------------------------------------------------
85 #define CONFIG_PCI /* include pci support */
88 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
90 #define CONFIG_EEPRO100
91 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
92 #define CONFIG_NATSEMI
93 #define CONFIG_NS8382X
95 #define PCI_ENET0_IOADDR 0x80000000
96 #define PCI_ENET0_MEMADDR 0x80000000
97 #define PCI_ENET1_IOADDR 0x81000000
98 #define PCI_ENET1_MEMADDR 0x81000000
101 /*-----------------------------------------------------------------------
102 * Start addresses for the final memory configuration
103 * (Set up by the startup code)
104 * Please note that CFG_SDRAM_BASE _must_ start at 0
106 #define CFG_SDRAM_BASE 0x00000000
107 #define CFG_MAX_RAM_SIZE 0x10000000
109 #define CFG_RESET_ADDRESS 0xFFF00100
111 #if defined (USE_DINK32)
112 #define CFG_MONITOR_LEN 0x00030000
113 #define CFG_MONITOR_BASE 0x00090000
114 #define CFG_RAMBOOT 1
115 #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
116 #define CFG_INIT_RAM_END 0x10000
117 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
118 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
119 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
122 #define CFG_MONITOR_LEN 0x00030000
123 #define CFG_MONITOR_BASE TEXT_BASE
125 /*#define CFG_GBL_DATA_SIZE 256*/
126 #define CFG_GBL_DATA_SIZE 128
128 #define CFG_INIT_RAM_ADDR 0x40000000
129 #define CFG_INIT_RAM_END 0x1000
130 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
134 #define CFG_FLASH_BASE 0xFFF00000
136 #define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
138 #define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
140 #define CFG_ENV_IS_IN_FLASH 1
141 #define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
142 #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
144 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
146 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
147 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
149 #define CFG_EUMB_ADDR 0xFC000000
151 #define CFG_ISA_MEM 0xFD000000
152 #define CFG_ISA_IO 0xFE000000
154 #define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
155 #define CFG_FLASH_RANGE_SIZE 0x01000000
156 #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
157 #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
160 * select i2c support configuration
162 * Supported configurations are {none, software, hardware} drivers.
163 * If the software driver is chosen, there are some additional
164 * configuration items that the driver uses to drive the port pins.
166 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
167 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
168 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
169 #define CFG_I2C_SLAVE 0x7F
171 #ifdef CONFIG_SOFT_I2C
172 #error "Soft I2C is not configured properly. Please review!"
173 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
174 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
175 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
176 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
177 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
178 else iop->pdat &= ~0x00010000
179 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
180 else iop->pdat &= ~0x00020000
181 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
182 #endif /* CONFIG_SOFT_I2C */
184 #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
185 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
186 #define CFG_EEPROM_PAGE_WRITE_BITS 3
187 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
189 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
190 #define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
192 /*-----------------------------------------------------------------------
193 * Definitions for initial stack pointer and data area (in DPRAM)
197 #define CFG_WINBOND_83C553 1 /*has a winbond bridge */
198 #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
199 #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
200 #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
202 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
203 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
206 * NS87308 Configuration
208 #define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
210 #define CFG_NS87308_BADDR_10 1
212 #define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
213 CFG_NS87308_UART2 | \
214 CFG_NS87308_POWRMAN | \
215 CFG_NS87308_RTC_APC )
217 #undef CFG_NS87308_PS2MOD
219 #define CFG_NS87308_CS0_BASE 0x0076
220 #define CFG_NS87308_CS0_CONF 0x30
221 #define CFG_NS87308_CS1_BASE 0x0075
222 #define CFG_NS87308_CS1_CONF 0x30
223 #define CFG_NS87308_CS2_BASE 0x0074
224 #define CFG_NS87308_CS2_CONF 0x30
227 * NS16550 Configuration
230 #define CFG_NS16550_SERIAL
232 #define CFG_NS16550_REG_SIZE 1
234 #if (CONFIG_CONS_INDEX > 2)
235 #define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000
237 #define CFG_NS16550_CLK 1843200
240 #define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
241 #define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
242 #define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
243 #define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600)
246 * Low Level Configuration Settings
247 * (address mappings, register initial values, etc.)
248 * You should know what you are doing if you make changes here.
251 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
253 #define CFG_ROMNAL 7 /*rom/flash next access time */
254 #define CFG_ROMFAL 11 /*rom/flash access time */
256 #define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
258 /* the following are for SDRAM only*/
259 #define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
260 #define CFG_REFREC 8 /* Refresh to activate interval */
261 #define CFG_RDLAT 4 /* data latency from read command */
262 #define CFG_PRETOACT 3 /* Precharge to activate interval */
263 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
264 #define CFG_ACTORW 3 /* Activate to R/W */
265 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
266 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
268 #define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
271 #define CFG_REGISTERD_TYPE_BUFFER 1
273 #define CFG_REGDIMM 0
276 /* memory bank settings*/
278 * only bits 20-29 are actually used from these vales to set the
279 * start/end address the upper two bits will be 0, and the lower 20
280 * bits will be set to 0x00000 for a start address, or 0xfffff for an
283 #define CFG_BANK0_START 0x00000000
284 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
285 #define CFG_BANK0_ENABLE 1
286 #define CFG_BANK1_START 0x3ff00000
287 #define CFG_BANK1_END 0x3fffffff
288 #define CFG_BANK1_ENABLE 0
289 #define CFG_BANK2_START 0x3ff00000
290 #define CFG_BANK2_END 0x3fffffff
291 #define CFG_BANK2_ENABLE 0
292 #define CFG_BANK3_START 0x3ff00000
293 #define CFG_BANK3_END 0x3fffffff
294 #define CFG_BANK3_ENABLE 0
295 #define CFG_BANK4_START 0x00000000
296 #define CFG_BANK4_END 0x00000000
297 #define CFG_BANK4_ENABLE 0
298 #define CFG_BANK5_START 0x00000000
299 #define CFG_BANK5_END 0x00000000
300 #define CFG_BANK5_ENABLE 0
301 #define CFG_BANK6_START 0x00000000
302 #define CFG_BANK6_END 0x00000000
303 #define CFG_BANK6_ENABLE 0
304 #define CFG_BANK7_START 0x00000000
305 #define CFG_BANK7_END 0x00000000
306 #define CFG_BANK7_ENABLE 0
308 * Memory bank enable bitmask, specifying which of the banks defined above
309 are actually present. MSB is for bank #7, LSB is for bank #0.
311 #define CFG_BANK_ENABLE 0x01
313 #define CFG_ODCR 0xff /* configures line driver impedances, */
314 /* see 8240 book for bit definitions */
315 #define CFG_PGMAX 0x32 /* how long the 8240 retains the */
316 /* currently accessed page in memory */
317 /* see 8240 book for details */
319 /* SDRAM 0 - 256MB */
320 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
321 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
323 /* stack in DCACHE @ 1GB (no backing mem) */
324 #if defined(USE_DINK32)
325 #define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
326 #define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
328 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
329 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
333 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
334 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
336 /* Flash, config addrs, etc */
337 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
338 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
340 #define CFG_DBAT0L CFG_IBAT0L
341 #define CFG_DBAT0U CFG_IBAT0U
342 #define CFG_DBAT1L CFG_IBAT1L
343 #define CFG_DBAT1U CFG_IBAT1U
344 #define CFG_DBAT2L CFG_IBAT2L
345 #define CFG_DBAT2U CFG_IBAT2U
346 #define CFG_DBAT3L CFG_IBAT3L
347 #define CFG_DBAT3U CFG_IBAT3U
350 * For booting Linux, the board info and command line data
351 * have to be in the first 8 MB of memory, since this is
352 * the maximum mapped by the Linux kernel during initialization.
354 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
355 /*-----------------------------------------------------------------------
358 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
359 #define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
361 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
362 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
364 /*-----------------------------------------------------------------------
365 * Cache Configuration
367 #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
368 #if defined(CONFIG_CMD_KGDB)
369 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
374 * Internal Definitions
378 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
379 #define BOOTFLAG_WARM 0x02 /* Software reboot */
382 /* values according to the manual */
384 #define CONFIG_DRAM_50MHZ 1
385 #define CONFIG_SDRAM_50MHZ
388 #define NR_8259_INTS 1
391 #define CONFIG_DISK_SPINUP_TIME 1000000
394 #endif /* __CONFIG_H */