2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
38 #define CONFIG_MPC824X 1
39 #define CONFIG_MPC8245 1
40 #define CONFIG_SANDPOINT 1
48 #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
49 #define CONFIG_BAUDRATE 9600
50 #define CONFIG_DRAM_SPEED 100 /* MHz */
52 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
58 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
59 #include <cmd_confdefs.h>
63 * Miscellaneous configurable options
65 #define CFG_LONGHELP 1 /* undef to save memory */
66 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
67 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
68 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
69 #define CFG_MAXARGS 16 /* max number of command args */
70 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
71 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
72 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
74 /*-----------------------------------------------------------------------
76 *-----------------------------------------------------------------------
78 #define CONFIG_PCI /* include pci support */
81 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
83 #define CONFIG_EEPRO100
84 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
85 #define CONFIG_NATSEMI
86 #define CONFIG_NS8382X
88 #define PCI_ENET0_IOADDR 0x80000000
89 #define PCI_ENET0_MEMADDR 0x80000000
90 #define PCI_ENET1_IOADDR 0x81000000
91 #define PCI_ENET1_MEMADDR 0x81000000
94 /*-----------------------------------------------------------------------
95 * Start addresses for the final memory configuration
96 * (Set up by the startup code)
97 * Please note that CFG_SDRAM_BASE _must_ start at 0
99 #define CFG_SDRAM_BASE 0x00000000
100 #define CFG_MAX_RAM_SIZE 0x10000000
102 #define CFG_RESET_ADDRESS 0xFFF00100
104 #if defined (USE_DINK32)
105 #define CFG_MONITOR_LEN 0x00030000
106 #define CFG_MONITOR_BASE 0x00090000
107 #define CFG_RAMBOOT 1
108 #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
109 #define CFG_INIT_RAM_END 0x10000
110 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
111 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
112 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
115 #define CFG_MONITOR_LEN 0x00030000
116 #define CFG_MONITOR_BASE TEXT_BASE
118 /*#define CFG_GBL_DATA_SIZE 256*/
119 #define CFG_GBL_DATA_SIZE 128
121 #define CFG_INIT_RAM_ADDR 0x40000000
122 #define CFG_INIT_RAM_END 0x1000
123 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
127 #define CFG_FLASH_BASE 0xFFF00000
129 #define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
131 #define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
133 #define CFG_ENV_IS_IN_FLASH 1
134 #define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
135 #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
137 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
139 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
140 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
142 #define CFG_EUMB_ADDR 0xFC000000
144 #define CFG_ISA_MEM 0xFD000000
145 #define CFG_ISA_IO 0xFE000000
147 #define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
148 #define CFG_FLASH_RANGE_SIZE 0x01000000
149 #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
150 #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
153 * select i2c support configuration
155 * Supported configurations are {none, software, hardware} drivers.
156 * If the software driver is chosen, there are some additional
157 * configuration items that the driver uses to drive the port pins.
159 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
160 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
161 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
162 #define CFG_I2C_SLAVE 0x7F
164 #ifdef CONFIG_SOFT_I2C
165 #error "Soft I2C is not configured properly. Please review!"
166 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
167 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
168 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
169 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
170 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
171 else iop->pdat &= ~0x00010000
172 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
173 else iop->pdat &= ~0x00020000
174 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
175 #endif /* CONFIG_SOFT_I2C */
177 #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
178 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
179 #define CFG_EEPROM_PAGE_WRITE_BITS 3
180 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
182 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
183 #define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
185 /*-----------------------------------------------------------------------
186 * Definitions for initial stack pointer and data area (in DPRAM)
190 #define CFG_WINBOND_83C553 1 /*has a winbond bridge */
191 #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
192 #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
193 #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
195 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
196 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
199 * NS87308 Configuration
201 #define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
203 #define CFG_NS87308_BADDR_10 1
205 #define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
206 CFG_NS87308_UART2 | \
207 CFG_NS87308_POWRMAN | \
208 CFG_NS87308_RTC_APC )
210 #undef CFG_NS87308_PS2MOD
212 #define CFG_NS87308_CS0_BASE 0x0076
213 #define CFG_NS87308_CS0_CONF 0x30
214 #define CFG_NS87308_CS1_BASE 0x0075
215 #define CFG_NS87308_CS1_CONF 0x30
216 #define CFG_NS87308_CS2_BASE 0x0074
217 #define CFG_NS87308_CS2_CONF 0x30
220 * NS16550 Configuration
223 #define CFG_NS16550_SERIAL
225 #define CFG_NS16550_REG_SIZE 1
227 #if (CONFIG_CONS_INDEX > 2)
228 #define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000
230 #define CFG_NS16550_CLK 1843200
233 #define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
234 #define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
235 #define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
236 #define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600)
239 * Low Level Configuration Settings
240 * (address mappings, register initial values, etc.)
241 * You should know what you are doing if you make changes here.
244 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
246 #define CFG_ROMNAL 7 /*rom/flash next access time */
247 #define CFG_ROMFAL 11 /*rom/flash access time */
249 #define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
251 /* the following are for SDRAM only*/
252 #define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
253 #define CFG_REFREC 8 /* Refresh to activate interval */
254 #define CFG_RDLAT 4 /* data latency from read command */
255 #define CFG_PRETOACT 3 /* Precharge to activate interval */
256 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
257 #define CFG_ACTORW 3 /* Activate to R/W */
258 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
259 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
261 #define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
264 #define CFG_REGISTERD_TYPE_BUFFER 1
266 #define CFG_REGDIMM 0
269 /* memory bank settings*/
271 * only bits 20-29 are actually used from these vales to set the
272 * start/end address the upper two bits will be 0, and the lower 20
273 * bits will be set to 0x00000 for a start address, or 0xfffff for an
276 #define CFG_BANK0_START 0x00000000
277 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
278 #define CFG_BANK0_ENABLE 1
279 #define CFG_BANK1_START 0x3ff00000
280 #define CFG_BANK1_END 0x3fffffff
281 #define CFG_BANK1_ENABLE 0
282 #define CFG_BANK2_START 0x3ff00000
283 #define CFG_BANK2_END 0x3fffffff
284 #define CFG_BANK2_ENABLE 0
285 #define CFG_BANK3_START 0x3ff00000
286 #define CFG_BANK3_END 0x3fffffff
287 #define CFG_BANK3_ENABLE 0
288 #define CFG_BANK4_START 0x00000000
289 #define CFG_BANK4_END 0x00000000
290 #define CFG_BANK4_ENABLE 0
291 #define CFG_BANK5_START 0x00000000
292 #define CFG_BANK5_END 0x00000000
293 #define CFG_BANK5_ENABLE 0
294 #define CFG_BANK6_START 0x00000000
295 #define CFG_BANK6_END 0x00000000
296 #define CFG_BANK6_ENABLE 0
297 #define CFG_BANK7_START 0x00000000
298 #define CFG_BANK7_END 0x00000000
299 #define CFG_BANK7_ENABLE 0
301 * Memory bank enable bitmask, specifying which of the banks defined above
302 are actually present. MSB is for bank #7, LSB is for bank #0.
304 #define CFG_BANK_ENABLE 0x01
306 #define CFG_ODCR 0xff /* configures line driver impedances, */
307 /* see 8240 book for bit definitions */
308 #define CFG_PGMAX 0x32 /* how long the 8240 retains the */
309 /* currently accessed page in memory */
310 /* see 8240 book for details */
312 /* SDRAM 0 - 256MB */
313 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
314 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
316 /* stack in DCACHE @ 1GB (no backing mem) */
317 #if defined(USE_DINK32)
318 #define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
319 #define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
321 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
322 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
326 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
327 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
329 /* Flash, config addrs, etc */
330 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
331 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
333 #define CFG_DBAT0L CFG_IBAT0L
334 #define CFG_DBAT0U CFG_IBAT0U
335 #define CFG_DBAT1L CFG_IBAT1L
336 #define CFG_DBAT1U CFG_IBAT1U
337 #define CFG_DBAT2L CFG_IBAT2L
338 #define CFG_DBAT2U CFG_IBAT2U
339 #define CFG_DBAT3L CFG_IBAT3L
340 #define CFG_DBAT3U CFG_IBAT3U
343 * For booting Linux, the board info and command line data
344 * have to be in the first 8 MB of memory, since this is
345 * the maximum mapped by the Linux kernel during initialization.
347 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
348 /*-----------------------------------------------------------------------
351 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
352 #define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
354 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
355 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
357 /*-----------------------------------------------------------------------
358 * Cache Configuration
360 #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
361 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
362 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
367 * Internal Definitions
371 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
372 #define BOOTFLAG_WARM 0x02 /* Software reboot */
375 /* values according to the manual */
377 #define CONFIG_DRAM_50MHZ 1
378 #define CONFIG_SDRAM_50MHZ
381 #define NR_8259_INTS 1
384 #define CONFIG_DISK_SPINUP_TIME 1000000
387 #endif /* __CONFIG_H */