include/configs/SIMPC8313.h

   1 /*
   2  * Copyright (C) Sheldon Instruments, Inc. 2008
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * simpc8313 board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_NAND_U_BOOT
  33
  34 #define CONFIG_E300                     1
  35 #define CONFIG_MPC83xx                  1
  36 #define CONFIG_MPC831x                  1
  37 #define CONFIG_MPC8313                  1
  38
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00100000
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00100100
  42 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
  43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  44
  45 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  46 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  47
  48 #ifdef CONFIG_NAND_SPL
  49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  50 #else
  51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  52 #endif
  53
  54 #define CONFIG_PCI
  55 #define CONFIG_FSL_ELBC                 1
  56
  57 #define CONFIG_MISC_INIT_R
  58
  59 /*
  60  * On-board devices
  61  *
  62  * TSEC1 is Marvell PHY 88E1118
  63  */
  64
  65 #define CONFIG_SYS_33MHZ
  66
  67 #define CONFIG_83XX_CLKIN               33333333        /* in Hz */
  68
  69 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  70
  71 #define CONFIG_SYS_IMMR                 0xE0000000
  72
  73 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  74 #define CONFIG_DEFAULT_IMMR             CONFIG_SYS_IMMR
  75 #endif
  76
  77 #define CONFIG_SYS_MEMTEST_START        0x00001000
  78 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  79
  80 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  81 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  82
  83 /*
  84  * Device configurations
  85  */
  86 #define CONFIG_TSEC1
  87
  88 /*
  89  * DDR Setup
  90  */
  91                                         /* DDR is system memory*/
  92 #define CONFIG_SYS_DDR_BASE             0x00000000
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95
  96 #define CONFIG_VERY_BIG_RAM
  97 #define CONFIG_MAX_MEM_MAPPED           (512 << 20)
  98
  99 #define CONFIG_SYS_DDRCDR               (DDRCDR_EN \
 100                                         | DDRCDR_PZ_NOMZ \
 101                                         | DDRCDR_NZ_NOMZ \
 102                                         | DDRCDR_M_ODR)
 103                                         /* 0x73000002 TODO ODR & DRN ? */
 104
 105 /*
 106  * FLASH on the Local Bus
 107  */
 108 #define CONFIG_SYS_NO_FLASH
 109
 110 #if !defined(CONFIG_NAND_SPL)
 111 #define CONFIG_SYS_RAMBOOT
 112 #endif
 113
 114 #define CONFIG_SYS_INIT_RAM_LOCK        1
 115 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 116 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 117
 118 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 119                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 120 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 121
 122 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 123 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 124 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 125
 126 /*
 127  * Local Bus LCRR and LBCR regs
 128  */
 129 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 130 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 131 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 132 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 133                                 | (0xFF << LBCR_BMT_SHIFT) \
 134                                 | 0xF)  /* 0x0004ff0f */
 135
 136                                 /* LB refresh timer prescal, 266MHz/32 */
 137 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 138
 139 /* drivers/mtd/nand/nand.c */
 140 #ifdef CONFIG_NAND_SPL
 141 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 142 #else
 143 #define CONFIG_SYS_NAND_BASE            0xE2800000
 144 #endif
 145 #define CONFIG_SYS_FPGA_BASE            0xFF000000
 146
 147 #define CONFIG_CMD_NAND
 148 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 149 #define CONFIG_MTD_NAND_VERIFY_WRITE
 150 #define CONFIG_NAND_FSL_ELBC            1
 151
 152 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 153                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 154                                 | BR_PS_8               /* 8 bit Port */ \
 155                                 | BR_MS_FCM             /* MSEL = FCM */ \
 156                                 | BR_V)                 /* valid */
 157
 158 #ifdef CONFIG_NAND_SP
 159 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 160                                         | OR_FCM_CSCT \
 161                                         | OR_FCM_CST \
 162                                         | OR_FCM_CHT \
 163                                         | OR_FCM_SCY_1 \
 164                                         | OR_FCM_TRLX \
 165                                         | OR_FCM_EHTR)
 166 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 167 #define CONFIG_SYS_NAND_PAGE_SIZE       512     /* NAND chip page size */
 168                                         /* NAND chip block size */
 169 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)
 170 #define NAND_CACHE_PAGES                32
 171 #elif defined(CONFIG_NAND_LP)
 172 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_256KB \
 173                                         | OR_FCM_PGS \
 174                                         | OR_FCM_CSCT \
 175                                         | OR_FCM_CST \
 176                                         | OR_FCM_CHT \
 177                                         | OR_FCM_SCY_1 \
 178                                         | OR_FCM_TRLX \
 179                                         | OR_FCM_EHTR)
 180 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 181 #define CONFIG_SYS_NAND_PAGE_SIZE       2048    /* NAND chip page size */
 182                                         /* NAND chip block size */
 183 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 184 #define NAND_CACHE_PAGES                64
 185 #else
 186 #error Page size of NAND not defined.
 187 #endif /* CONFIG_NAND_SP */
 188
 189 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SYS_NAND_BLOCK_SIZE
 190
 191 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_NAND_BR_PRELIM
 192 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_NAND_OR_PRELIM
 193
 194 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_NAND_BASE
 195
 196 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
 197 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR0_PRELIM
 198
 199 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_FPGA_BASE \
 200                                         | BR_PS_16 \
 201                                         | BR_MS_UPMA \
 202                                         | BR_V)
 203 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_2MB \
 204                                         | OR_UPM_BCTLD)
 205
 206 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA_BASE
 207 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_2MB)
 208
 209 /*
 210  * JFFS2 configuration
 211  */
 212 #define CONFIG_JFFS2_NAND
 213 #define CONFIG_JFFS2_DEV        "nand0"
 214
 215 /* mtdparts command line support */
 216 #define CONFIG_CMD_MTDPARTS
 217 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 218 #define MTDIDS_DEFAULT          "nand0=nand0"
 219 #define MTDPARTS_DEFAULT        "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 220
 221 /* pass open firmware flat tree */
 222 #define CONFIG_OF_LIBFDT                1
 223 #define CONFIG_OF_BOARD_SETUP           1
 224 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 225
 226 /*
 227  * Serial Port
 228  */
 229 #define CONFIG_CONS_INDEX               1
 230 #define CONFIG_SYS_NS16550
 231 #define CONFIG_SYS_NS16550_SERIAL
 232 #define CONFIG_SYS_NS16550_REG_SIZE     1
 233 #ifdef CONFIG_NAND_SPL
 234 #define CONFIG_NS16550_MIN_FUNCTIONS
 235 #endif
 236
 237 #define CONFIG_SYS_BAUDRATE_TABLE       \
 238                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 239
 240 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR+0x4500)
 241 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR+0x4600)
 242
 243 /* Use the HUSH parser */
 244 #define CONFIG_SYS_HUSH_PARSER
 245 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 246
 247 /* I2C */
 248 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 249 #define CONFIG_FSL_I2C
 250 #define CONFIG_I2C_MULTI_BUS
 251 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 252 #define CONFIG_SYS_I2C_SLAVE    0x7F
 253 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
 254 #define CONFIG_SYS_I2C_OFFSET   0x3000
 255 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 256
 257 /*
 258  * General PCI
 259  * Addresses are mapped 1-1.
 260  */
 261 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 262 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 263 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 264 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 265 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 266 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 267 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 268 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 269 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 270
 271 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 272 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1057  /* Motorola */
 273
 274 /*
 275  * TSEC
 276  */
 277 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 278
 279 #define CONFIG_GMII                     /* MII PHY management */
 280
 281 #ifdef CONFIG_TSEC1
 282 #define CONFIG_HAS_ETH0
 283 #define CONFIG_TSEC1_NAME               "TSEC0"
 284 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 285 #define TSEC1_PHY_ADDR                  0x0
 286 #define TSEC1_FLAGS                     TSEC_GIGABIT
 287 #define TSEC1_PHYIDX                    0
 288 #endif
 289
 290 #ifdef CONFIG_TSEC2
 291 #define CONFIG_HAS_ETH1
 292 #define CONFIG_TSEC2_NAME               "TSEC1"
 293 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 294 #define TSEC2_PHY_ADDR                  4
 295 #define TSEC2_FLAGS                     TSEC_GIGABIT
 296 #define TSEC2_PHYIDX                    0
 297 #endif
 298
 299
 300 /* Options are: TSEC[0-1] */
 301 #define CONFIG_ETHPRIME                 "TSEC1"
 302
 303 /*
 304  * Configure on-board RTC
 305  */
 306 #define CONFIG_RTC_DS1337
 307 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 308
 309 /*
 310  * Environment
 311  */
 312 #if defined(CONFIG_NAND_U_BOOT)
 313         #define CONFIG_ENV_IS_IN_NAND   1
 314         #define CONFIG_ENV_OFFSET       (768 * 1024)
 315         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 316         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 317         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 318         #define CONFIG_ENV_RANGE        (CONFIG_ENV_SECT_SIZE * 4)
 319         #define CONFIG_ENV_OFFSET_REDUND        \
 320                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 321 #elif !defined(CONFIG_SYS_RAMBOOT)
 322         #define CONFIG_ENV_IS_IN_FLASH  1
 323         #define CONFIG_ENV_ADDR         \
 324                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 325         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 326         #define CONFIG_ENV_SIZE         0x2000
 327
 328 /* Address and size of Redundant Environment Sector */
 329 #else
 330         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 331         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 332         #define CONFIG_ENV_SIZE         0x2000
 333 #endif
 334
 335 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 337
 338 /*
 339  * BOOTP options
 340  */
 341 #define CONFIG_BOOTP_BOOTFILESIZE
 342 #define CONFIG_BOOTP_BOOTPATH
 343 #define CONFIG_BOOTP_GATEWAY
 344 #define CONFIG_BOOTP_HOSTNAME
 345
 346
 347 /*
 348  * Command line configuration.
 349  */
 350 #include <config_cmd_default.h>
 351 #undef CONFIG_CMD_IMLS
 352 #undef CONFIG_CMD_FLASH
 353
 354 #define CONFIG_CMD_PING
 355 #define CONFIG_CMD_DHCP
 356 #define CONFIG_CMD_I2C
 357 #define CONFIG_CMD_MII
 358 #define CONFIG_CMD_DATE
 359 #define CONFIG_CMD_PCI
 360 #define CONFIG_CMD_JFFS2
 361
 362 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 363         #undef CONFIG_CMD_SAVEENV
 364         #undef CONFIG_CMD_LOADS
 365 #endif
 366
 367 #define CONFIG_CMDLINE_EDITING  1
 368 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 369
 370 /*
 371  * Miscellaneous configurable options
 372  */
 373 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 374 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 375 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 376 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 377
 378 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE              \
 379                                 + sizeof(CONFIG_SYS_PROMPT)     \
 380                                 + 16)   /* Print Buffer Size */
 381 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 382                                 /* Boot Argument Buffer Size */
 383 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 384 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 385
 386 /*
 387  * For booting Linux, the board info and command line data
 388  * have to be in the first 256 MB of memory, since this is
 389  * the maximum mapped by the Linux kernel during initialization.
 390  */
 391                                 /* Initial Memory map for Linux*/
 392 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 393
 394 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST */
 395
 396 #define CONFIG_SYS_HRCW_LOW     (HRCWL_LCL_BUS_TO_SCB_CLK_1X1   \
 397                                 | 0x20000000 /* reserved */     \
 398                                 | HRCWL_DDR_TO_SCB_CLK_2X1      \
 399                                 | HRCWL_CSB_TO_CLKIN_4X1        \
 400                                 | HRCWL_CORE_TO_CSB_2_5X1)
 401
 402 #define CONFIG_SYS_NS16550_CLK  (CONFIG_83XX_CLKIN * 4)
 403
 404 #define CONFIG_SYS_HRCW_HIGH_BASE       (HRCWH_PCI_HOST \
 405                                 | HRCWH_PCI1_ARBITER_ENABLE     \
 406                                 | HRCWH_CORE_ENABLE             \
 407                                 | HRCWH_BOOTSEQ_DISABLE         \
 408                                 | HRCWH_SW_WATCHDOG_DISABLE     \
 409                                 | HRCWH_TSEC1M_IN_RGMII         \
 410                                 | HRCWH_TSEC2M_IN_RGMII         \
 411                                 | HRCWH_BIG_ENDIAN              \
 412                                 | HRCWH_LALE_NORMAL)
 413
 414 #ifdef CONFIG_NAND_LP
 415 #define CONFIG_SYS_HRCW_HIGH    (CONFIG_SYS_HRCW_HIGH_BASE      \
 416                                 | HRCWH_FROM_0XFFF00100         \
 417                                 | HRCWH_ROM_LOC_NAND_LP_8BIT    \
 418                                 | HRCWH_RL_EXT_NAND)
 419 #else
 420 #define CONFIG_SYS_HRCW_HIGH    (CONFIG_SYS_HRCW_HIGH_BASE      \
 421                                 | HRCWH_FROM_0XFFF00100         \
 422                                 | HRCWH_ROM_LOC_NAND_SP_8BIT    \
 423                                 | HRCWH_RL_EXT_NAND)
 424 #endif
 425
 426 /* System IO Config */
 427 #define CONFIG_SYS_SICRH        (SICRH_ETSEC2_B \
 428                                 | SICRH_ETSEC2_C        \
 429                                 | SICRH_ETSEC2_D        \
 430                                 | SICRH_ETSEC2_E        \
 431                                 | SICRH_ETSEC2_F        \
 432                                 | SICRH_ETSEC2_G        \
 433                                 | SICRH_TSOBI1          \
 434                                 | SICRH_TSOBI2)
 435 #define CONFIG_SYS_SICRL        (SICRL_LBC              \
 436                                 | SICRL_USBDR_10        \
 437                                 | SICRL_ETSEC2_A)
 438
 439 #define CONFIG_SYS_HID0_INIT    0x000000000
 440 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 441                                 | HID0_ENABLE_INSTRUCTION_CACHE \
 442                                 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 443
 444 #define CONFIG_SYS_HID2         HID2_HBE
 445
 446 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 447
 448 /* DDR @ 0x00000000 */
 449 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 450 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 451                                 | BATU_BL_256M \
 452                                 | BATU_VS \
 453                                 | BATU_VP)
 454 #define CONFIG_SYS_IBAT1L       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
 455                                 | BATL_PP_RW)
 456 #define CONFIG_SYS_IBAT1U       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
 457                                 | BATU_BL_256M \
 458                                 | BATU_VS \
 459                                 | BATU_VP)
 460
 461 /* PCI @ 0x80000000 */
 462 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 463 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MEM_BASE \
 464                                 | BATU_BL_256M \
 465                                 | BATU_VS \
 466                                 | BATU_VP)
 467 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MMIO_BASE \
 468                                 | BATL_PP_RW \
 469                                 | BATL_CACHEINHIBIT \
 470                                 | BATL_GUARDEDSTORAGE)
 471 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MMIO_BASE \
 472                                 | BATU_BL_256M \
 473                                 | BATU_VS \
 474                                 | BATU_VP)
 475
 476 /* PCI2 not supported on 8313 */
 477 #define CONFIG_SYS_IBAT4L       (0)
 478 #define CONFIG_SYS_IBAT4U       (0)
 479
 480 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 481 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 482                                 | BATL_PP_RW \
 483                                 | BATL_CACHEINHIBIT \
 484                                 | BATL_GUARDEDSTORAGE)
 485 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 486                                 | BATU_BL_256M \
 487                                 | BATU_VS \
 488                                 | BATU_VP)
 489
 490 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 491 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 492                                 | BATL_PP_RW \
 493                                 | BATL_GUARDEDSTORAGE)
 494 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 495                                 | BATU_BL_256M \
 496                                 | BATU_VS \
 497                                 | BATU_VP)
 498
 499 #define CONFIG_SYS_IBAT7L       (0)
 500 #define CONFIG_SYS_IBAT7U       (0)
 501
 502 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 503 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 504 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 505 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 506 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 507 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 508 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 509 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 510 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 511 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 512 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 513 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 514 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 515 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 516 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 517 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 518
 519 /*
 520  * Environment Configuration
 521  */
 522 #define CONFIG_ENV_OVERWRITE
 523
 524 #define CONFIG_NETDEV           "eth1"
 525
 526 #define CONFIG_HOSTNAME         simpc8313
 527 #define CONFIG_ROOTPATH         "/tftpboot/"
 528 #define CONFIG_BOOTFILE         "/tftpboot/uImage"
 529                                 /* U-Boot image on TFTP server */
 530 #define CONFIG_UBOOTPATH        "u-boot-nand.bin"
 531 #define CONFIG_FDTFILE          "simpc8313.dtb"
 532
 533                                 /* default location for tftp and bootm */
 534 #define CONFIG_LOADADDR         500000
 535 #define CONFIG_BOOTDELAY        5       /* 5 second delay */
 536 #define CONFIG_BAUDRATE         115200
 537
 538 #define CONFIG_BOOTCOMMAND      "nand read $loadaddr kernel 600000;" \
 539                                         "bootm $loadaddr - $fdtaddr"
 540
 541 #define XMK_STR(x)      #x
 542 #define MK_STR(x)       XMK_STR(x)
 543
 544 #define CONFIG_EXTRA_ENV_SETTINGS \
 545         "netdev=" CONFIG_NETDEV "\0"                                    \
 546         "ethprime=TSEC1\0"                                              \
 547         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 548         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 549                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 550                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "   \
 551                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 552                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 553                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 554         "fdtaddr=ae0000\0"                                              \
 555         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 556         "console=ttyS0\0"                                               \
 557         "setbootargs=setenv bootargs "                                  \
 558                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 559         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 560                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 561                                                         "$netdev:off "  \
 562                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 563         "load_uboot=tftp 100000 u-boot-nand.bin\0"                      \
 564         "burn_uboot=nand erase u-boot 80000; "                          \
 565                 "nand write 100000 u-boot $filesize\0"                  \
 566         "update_uboot=run load_uboot;run burn_uboot\0"                  \
 567         "mtdids=nand0=nand0\0"                                          \
 568         "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"      \
 569         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 570                 "nfsroot=${serverip}:${rootpath}\0"                     \
 571         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 572         "addip=setenv bootargs ${bootargs} "                            \
 573                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 574                 ":${hostname}:${netdev}:off panic=1\0"                  \
 575         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 576         "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "             \
 577                 "console=ttyS0,115200\0"                                \
 578         ""
 579
 580 #define CONFIG_NFSBOOTCOMMAND                                           \
 581         "setenv rootdev /dev/nfs;"                                      \
 582         "run setbootargs;"                                              \
 583         "run setipargs;"                                                \
 584         "tftp $loadaddr $bootfile;"                                     \
 585         "tftp $fdtaddr $fdtfile;"                                       \
 586         "bootm $loadaddr - $fdtaddr"
 587
 588 #define CONFIG_RAMBOOTCOMMAND                                           \
 589         "setenv rootdev /dev/ram;"                                      \
 590         "run setbootargs;"                                              \
 591         "tftp $ramdiskaddr $ramdiskfile;"                               \
 592         "tftp $loadaddr $bootfile;"                                     \
 593         "tftp $fdtaddr $fdtfile;"                                       \
 594         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 595
 596 #undef MK_STR
 597 #undef XMK_STR
 598
 599 #endif  /* __CONFIG_H */