2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Analogue&Micro Rattler boards.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CPU_ID_STR "MPC8248"
32 #define CONFIG_MPC8260
33 #define CPU_ID_STR "MPC8250"
34 #endif /* CONFIG_MPC8248 */
36 #define CONFIG_SYS_TEXT_BASE 0xFE000000
38 #define CONFIG_CPM2 1 /* Has a CPM2 */
40 #define CONFIG_RATTLER /* Analogue&Micro Rattler board */
42 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
43 #define CONFIG_ENV_OVERWRITE
46 * Select serial console configuration
48 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
49 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
52 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
53 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
54 #undef CONFIG_CONS_NONE /* It's not on external UART */
55 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
58 * Select ethernet configuration
60 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
61 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
64 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
65 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
68 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
69 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
70 #undef CONFIG_ETHER_NONE /* No external Ethernet */
72 #ifdef CONFIG_ETHER_ON_FCC
74 #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
76 #if (CONFIG_ETHER_INDEX == 1)
78 /* - Rx clock is CLK11
80 * - BDs/buffers on 60x bus
83 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
84 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
85 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
86 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
88 #elif (CONFIG_ETHER_INDEX == 2)
90 /* - Rx clock is CLK15
92 * - BDs/buffers on 60x bus
95 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
96 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
97 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
98 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
100 #endif /* CONFIG_ETHER_INDEX */
102 #define CONFIG_MII /* MII PHY management */
103 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
105 * GPIO pins used for bit-banged MII communications
107 #define MDIO_PORT 2 /* Port C */
108 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
109 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
110 #define MDC_DECLARE MDIO_DECLARE
112 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
113 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
114 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
116 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
117 else iop->pdat &= ~0x00400000
119 #define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
120 else iop->pdat &= ~0x00800000
122 #define MIIDELAY udelay(1)
124 #endif /* CONFIG_ETHER_ON_FCC */
126 #ifndef CONFIG_8260_CLKIN
127 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
130 #define CONFIG_BAUDRATE 38400
136 #define CONFIG_BOOTP_BOOTFILESIZE
137 #define CONFIG_BOOTP_BOOTPATH
138 #define CONFIG_BOOTP_GATEWAY
139 #define CONFIG_BOOTP_HOSTNAME
143 * Command line configuration.
145 #include <config_cmd_default.h>
147 #define CONFIG_CMD_DHCP
148 #define CONFIG_CMD_IMMAP
149 #define CONFIG_CMD_JFFS2
150 #define CONFIG_CMD_MII
151 #define CONFIG_CMD_PING
154 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
155 #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
156 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
158 #if defined(CONFIG_CMD_KGDB)
159 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
160 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
161 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
162 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
163 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
166 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
167 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
170 * Miscellaneous configurable options
172 #define CONFIG_SYS_HUSH_PARSER
173 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
174 #define CONFIG_SYS_LONGHELP /* undef to save memory */
175 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
176 #if defined(CONFIG_CMD_KGDB)
177 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
179 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
181 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
182 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
183 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
185 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
186 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
188 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
190 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
192 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
194 #define CONFIG_SYS_FLASH_BASE 0xFE000000
195 #define CONFIG_SYS_FLASH_CFI
196 #define CONFIG_FLASH_CFI_DRIVER
197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
198 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
200 #define CONFIG_SYS_DIRECT_FLASH_TFTP
202 #if defined(CONFIG_CMD_JFFS2)
203 #define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
204 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
210 /* No command line, one static partition */
211 #undef CONFIG_CMD_MTDPARTS
212 #define CONFIG_JFFS2_DEV "nor0"
213 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
214 #define CONFIG_JFFS2_PART_OFFSET 0x00100000
216 /* mtdparts command line support */
217 /* Note: fake mtd_id used, no linux mtd map file */
219 #define CONFIG_CMD_MTDPARTS
220 #define MTDIDS_DEFAULT "nor0=rattler-0"
221 #define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
223 #endif /* CONFIG_CMD_JFFS2 */
225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
226 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
227 #define CONFIG_SYS_RAMBOOT
230 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
232 #define CONFIG_ENV_IS_IN_FLASH
234 #ifdef CONFIG_ENV_IS_IN_FLASH
235 #define CONFIG_ENV_SECT_SIZE 0x10000
236 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
237 #endif /* CONFIG_ENV_IS_IN_FLASH */
239 #define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
241 #define CONFIG_SYS_IMMR 0xF0000000
243 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
244 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
245 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
246 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
248 #define CONFIG_SYS_SDRAM_BASE 0x00000000
249 #define CONFIG_SYS_SDRAM_SIZE 32
250 #define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
251 #define CONFIG_SYS_SDRAM_OR 0xFE002EC0
253 #define CONFIG_SYS_BCSR 0xFC000000
255 /* Hard reset configuration word */
256 #define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
258 #define CONFIG_SYS_HRCW_SLAVE1 0
259 #define CONFIG_SYS_HRCW_SLAVE2 0
260 #define CONFIG_SYS_HRCW_SLAVE3 0
261 #define CONFIG_SYS_HRCW_SLAVE4 0
262 #define CONFIG_SYS_HRCW_SLAVE5 0
263 #define CONFIG_SYS_HRCW_SLAVE6 0
264 #define CONFIG_SYS_HRCW_SLAVE7 0
266 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
267 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
269 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
270 #if defined(CONFIG_CMD_KGDB)
271 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
274 #define CONFIG_SYS_HID0_INIT 0
275 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
277 #define CONFIG_SYS_HID2 0
279 #define CONFIG_SYS_SIUMCR 0x0E04C000
280 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
281 #define CONFIG_SYS_BCR 0x00000000
282 #define CONFIG_SYS_SCCR SCCR_DFBRG01
284 #define CONFIG_SYS_RMR RMR_CSRE
285 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
286 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
287 #define CONFIG_SYS_RCCR 0
289 #define CONFIG_SYS_PSDMR 0x8249A452
290 #define CONFIG_SYS_PSRT 0x1F
291 #define CONFIG_SYS_MPTPR 0x2000
293 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
294 #define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
295 #define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
296 #define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
298 #define CONFIG_SYS_RESET_ADDRESS 0xC0000000
300 #endif /* __CONFIG_H */