2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Analogue&Micro Rattler boards.
7 * SPDX-License-Identifier: GPL-2.0+
14 #define CPU_ID_STR "MPC8248"
16 #define CONFIG_MPC8260
17 #define CPU_ID_STR "MPC8250"
18 #endif /* CONFIG_MPC8248 */
20 #define CONFIG_SYS_TEXT_BASE 0xFE000000
22 #define CONFIG_CPM2 1 /* Has a CPM2 */
24 #define CONFIG_RATTLER /* Analogue&Micro Rattler board */
26 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
27 #define CONFIG_ENV_OVERWRITE
30 * Select serial console configuration
32 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
33 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
36 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
37 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
38 #undef CONFIG_CONS_NONE /* It's not on external UART */
39 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
42 * Select ethernet configuration
44 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
45 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
48 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
49 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
52 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
53 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
54 #undef CONFIG_ETHER_NONE /* No external Ethernet */
56 #ifdef CONFIG_ETHER_ON_FCC
58 #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
60 #if (CONFIG_ETHER_INDEX == 1)
62 /* - Rx clock is CLK11
64 * - BDs/buffers on 60x bus
67 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
68 #define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
69 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
70 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
72 #elif (CONFIG_ETHER_INDEX == 2)
74 /* - Rx clock is CLK15
76 * - BDs/buffers on 60x bus
79 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
80 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
81 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
82 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
84 #endif /* CONFIG_ETHER_INDEX */
86 #define CONFIG_MII /* MII PHY management */
87 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
89 * GPIO pins used for bit-banged MII communications
91 #define MDIO_PORT 2 /* Port C */
92 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
93 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
94 #define MDC_DECLARE MDIO_DECLARE
96 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
97 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
98 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
100 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
101 else iop->pdat &= ~0x00400000
103 #define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
104 else iop->pdat &= ~0x00800000
106 #define MIIDELAY udelay(1)
108 #endif /* CONFIG_ETHER_ON_FCC */
110 #ifndef CONFIG_8260_CLKIN
111 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
114 #define CONFIG_BAUDRATE 38400
120 #define CONFIG_BOOTP_BOOTFILESIZE
121 #define CONFIG_BOOTP_BOOTPATH
122 #define CONFIG_BOOTP_GATEWAY
123 #define CONFIG_BOOTP_HOSTNAME
127 * Command line configuration.
129 #include <config_cmd_default.h>
131 #define CONFIG_CMD_DHCP
132 #define CONFIG_CMD_IMMAP
133 #define CONFIG_CMD_JFFS2
134 #define CONFIG_CMD_MII
135 #define CONFIG_CMD_PING
138 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
139 #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
140 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
142 #if defined(CONFIG_CMD_KGDB)
143 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
144 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
145 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
146 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
147 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
150 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
151 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
154 * Miscellaneous configurable options
156 #define CONFIG_SYS_HUSH_PARSER
157 #define CONFIG_SYS_LONGHELP /* undef to save memory */
158 #if defined(CONFIG_CMD_KGDB)
159 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
161 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
163 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
164 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
165 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
167 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
168 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
170 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
172 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
174 #define CONFIG_SYS_FLASH_BASE 0xFE000000
175 #define CONFIG_SYS_FLASH_CFI
176 #define CONFIG_FLASH_CFI_DRIVER
177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
178 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
180 #define CONFIG_SYS_DIRECT_FLASH_TFTP
182 #if defined(CONFIG_CMD_JFFS2)
183 #define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
184 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
190 /* No command line, one static partition */
191 #undef CONFIG_CMD_MTDPARTS
192 #define CONFIG_JFFS2_DEV "nor0"
193 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
194 #define CONFIG_JFFS2_PART_OFFSET 0x00100000
196 /* mtdparts command line support */
197 /* Note: fake mtd_id used, no linux mtd map file */
199 #define CONFIG_CMD_MTDPARTS
200 #define MTDIDS_DEFAULT "nor0=rattler-0"
201 #define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
203 #endif /* CONFIG_CMD_JFFS2 */
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
206 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
207 #define CONFIG_SYS_RAMBOOT
210 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
212 #define CONFIG_ENV_IS_IN_FLASH
214 #ifdef CONFIG_ENV_IS_IN_FLASH
215 #define CONFIG_ENV_SECT_SIZE 0x10000
216 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
217 #endif /* CONFIG_ENV_IS_IN_FLASH */
219 #define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
221 #define CONFIG_SYS_IMMR 0xF0000000
223 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
224 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
225 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
228 #define CONFIG_SYS_SDRAM_BASE 0x00000000
229 #define CONFIG_SYS_SDRAM_SIZE 32
230 #define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
231 #define CONFIG_SYS_SDRAM_OR 0xFE002EC0
233 #define CONFIG_SYS_BCSR 0xFC000000
235 /* Hard reset configuration word */
236 #define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
238 #define CONFIG_SYS_HRCW_SLAVE1 0
239 #define CONFIG_SYS_HRCW_SLAVE2 0
240 #define CONFIG_SYS_HRCW_SLAVE3 0
241 #define CONFIG_SYS_HRCW_SLAVE4 0
242 #define CONFIG_SYS_HRCW_SLAVE5 0
243 #define CONFIG_SYS_HRCW_SLAVE6 0
244 #define CONFIG_SYS_HRCW_SLAVE7 0
246 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
247 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
249 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
250 #if defined(CONFIG_CMD_KGDB)
251 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
254 #define CONFIG_SYS_HID0_INIT 0
255 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
257 #define CONFIG_SYS_HID2 0
259 #define CONFIG_SYS_SIUMCR 0x0E04C000
260 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
261 #define CONFIG_SYS_BCR 0x00000000
262 #define CONFIG_SYS_SCCR SCCR_DFBRG01
264 #define CONFIG_SYS_RMR RMR_CSRE
265 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
266 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
267 #define CONFIG_SYS_RCCR 0
269 #define CONFIG_SYS_PSDMR 0x8249A452
270 #define CONFIG_SYS_PSRT 0x1F
271 #define CONFIG_SYS_MPTPR 0x2000
273 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
274 #define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
275 #define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
276 #define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
278 #define CONFIG_SYS_RESET_ADDRESS 0xC0000000
280 #endif /* __CONFIG_H */