2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_RRVISION 1 /* ...on a RRvision board */
39 #define CONFIG_8xx_GCLK_FREQ 64000000
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
46 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
51 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53 #define CONFIG_PREBOOT "setenv stdout serial"
55 #undef CONFIG_BOOTARGS
56 #define CONFIG_ETHADDR 00:50:C2:00:E0:70
57 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
58 #define CONFIG_IPADDR 10.0.0.5
59 #define CONFIG_SERVERIP 10.0.0.2
60 #define CONFIG_NETMASK 255.0.0.0
61 #define CONFIG_ROOTPATH /opt/eldk/ppc_8xx
62 #define CONFIG_BOOTCOMMAND "run flash_self"
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "ramargs=setenv bootargs root=/dev/ram rw\0" \
67 "nfsargs=setenv bootargs root=/dev/nfs rw " \
68 "nfsroot=${serverip}:${rootpath}\0" \
69 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
70 ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
71 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
72 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
73 "update=protect off 1:0-8;era 1:0-8;" \
74 "cp.b 100000 40000000 ${filesize};" \
75 "setenv filesize;saveenv\0" \
76 "kernel_addr=40040000\0" \
77 "ramdisk_addr=40100000\0" \
78 "kernel_img=/tftpboot/uImage\0" \
79 "kernel_load=tftp 200000 ${kernel_img}\0" \
80 "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
81 "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
82 "flash_self=run ramargs addip addtty;" \
83 "bootm ${kernel_addr} ${ramdisk_addr}\0"
86 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
89 #undef CONFIG_WATCHDOG /* watchdog disabled */
91 #undef CONFIG_STATUS_LED /* disturbs display */
93 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
95 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
97 #define CONFIG_MAC_PARTITION
98 #define CONFIG_DOS_PARTITION
100 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
104 #define CONFIG_VIDEO 1 /* To enable the video initialization */
107 #define CONFIG_VIDEO_LOGO 1 /* Show the logo */
108 #define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
109 #define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
112 /* enable I2C and select the hardware/software driver */
113 #undef CONFIG_HARD_I2C /* I2C with hardware support */
114 #define CONFIG_SOFT_I2C /* I2C bit-banged */
116 # define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */
117 # define CFG_I2C_SLAVE 0xFE
119 #ifdef CONFIG_SOFT_I2C
121 * Software (bit-bang) I2C driver configuration
123 #define PB_SCL 0x00000020 /* PB 26 */
124 #define PB_SDA 0x00000010 /* PB 27 */
126 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
127 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
128 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
129 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
130 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
131 else immr->im_cpm.cp_pbdat &= ~PB_SDA
132 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
133 else immr->im_cpm.cp_pbdat &= ~PB_SCL
134 #define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
135 #endif /* CONFIG_SOFT_I2C */
139 * Command line configuration.
141 #include <config_cmd_default.h>
143 #define CONFIG_CMD_DHCP
144 #define CONFIG_CMD_I2C
145 #define CONFIG_CMD_IDE
146 #define CONFIG_CMD_DATE
148 #undef CONFIG_CMD_PCMCIA
149 #undef CONFIG_CMD_IDE
153 * Miscellaneous configurable options
155 #define CFG_LONGHELP /* undef to save memory */
156 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
157 #if defined(CONFIG_CMD_KGDB)
158 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
160 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
162 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
163 #define CFG_MAXARGS 16 /* max number of command args */
164 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
166 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
167 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
169 #define CFG_LOAD_ADDR 0x100000 /* default load address */
171 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
173 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
176 * Low Level Configuration Settings
177 * (address mappings, register initial values, etc.)
178 * You should know what you are doing if you make changes here.
180 /*-----------------------------------------------------------------------
181 * Internal Memory Mapped Register
183 #define CFG_IMMR 0xFFF00000
185 /*-----------------------------------------------------------------------
186 * Definitions for initial stack pointer and data area (in DPRAM)
188 #define CFG_INIT_RAM_ADDR CFG_IMMR
189 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
190 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
191 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
192 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
194 /*-----------------------------------------------------------------------
195 * Start addresses for the final memory configuration
196 * (Set up by the startup code)
197 * Please note that CFG_SDRAM_BASE _must_ start at 0
199 #define CFG_SDRAM_BASE 0x00000000
200 #define CFG_FLASH_BASE 0x40000000
201 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
202 #define CFG_MONITOR_BASE CFG_FLASH_BASE
203 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
206 * For booting Linux, the board info and command line data
207 * have to be in the first 8 MB of memory, since this is
208 * the maximum mapped by the Linux kernel during initialization.
210 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212 /*-----------------------------------------------------------------------
215 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
216 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
218 /* timeout values are in ticks = ms */
219 #define CFG_FLASH_ERASE_TOUT (120*CFG_HZ) /* Timeout for Flash Erase */
220 #define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */
222 #define CFG_ENV_IS_IN_FLASH 1
223 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
224 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
226 /* Address and size of Redundant Environment Sector */
227 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
228 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
230 /*-----------------------------------------------------------------------
231 * Cache Configuration
233 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
234 #if defined(CONFIG_CMD_KGDB)
235 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
238 /*-----------------------------------------------------------------------
239 * SYPCR - System Protection Control 11-9
240 * SYPCR can only be written once after reset!
241 *-----------------------------------------------------------------------
242 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
244 #if defined(CONFIG_WATCHDOG)
245 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
248 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
251 /*-----------------------------------------------------------------------
252 * SIUMCR - SIU Module Configuration 11-6
253 *-----------------------------------------------------------------------
254 * PCMCIA config., multi-function pin tri-state
256 #ifndef CONFIG_CAN_DRIVER
257 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
258 #else /* we must activate GPL5 in the SIUMCR for CAN */
259 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
260 #endif /* CONFIG_CAN_DRIVER */
262 /*-----------------------------------------------------------------------
263 * TBSCR - Time Base Status and Control 11-26
264 *-----------------------------------------------------------------------
265 * Clear Reference Interrupt Status, Timebase freezing enabled
267 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
269 /*-----------------------------------------------------------------------
270 * RTCSC - Real-Time Clock Status and Control Register 11-27
271 *-----------------------------------------------------------------------
273 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
275 /*-----------------------------------------------------------------------
276 * PISCR - Periodic Interrupt Status and Control 11-31
277 *-----------------------------------------------------------------------
278 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
280 #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
282 /*-----------------------------------------------------------------------
283 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
284 *-----------------------------------------------------------------------
285 * Reset PLL lock status sticky bit, timer expired status bit and timer
286 * interrupt status bit
289 /* for 64 MHz, we use a 16 MHz clock * 4 */
290 #define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
292 /*-----------------------------------------------------------------------
293 * SCCR - System Clock and reset Control Register 15-27
294 *-----------------------------------------------------------------------
295 * Set clock output, timebase and RTC source and divider,
296 * power management and some other internal clocks
298 #define SCCR_MASK SCCR_EBDF11
299 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \
300 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
301 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
304 /*-----------------------------------------------------------------------
306 *-----------------------------------------------------------------------
309 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
310 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
311 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
312 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
313 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
314 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
315 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
316 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
318 /*-----------------------------------------------------------------------
319 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
320 *-----------------------------------------------------------------------
323 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
325 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
326 #undef CONFIG_IDE_LED /* LED for ide not supported */
327 #undef CONFIG_IDE_RESET /* reset for ide not supported */
329 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
330 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
332 #define CFG_ATA_IDE0_OFFSET 0x0000
334 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
336 /* Offset for data I/O */
337 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
339 /* Offset for normal register accesses */
340 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
342 /* Offset for alternate registers */
343 #define CFG_ATA_ALT_OFFSET 0x0100
345 /*-----------------------------------------------------------------------
347 *-----------------------------------------------------------------------
350 /*#define CFG_DER 0x2002000F*/
354 * Init Memory Controller:
359 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
361 /* used to re-map FLASH both when starting from SRAM or FLASH:
362 * restrict access enough to keep SRAM working (if any)
363 * but not too much to meddle with FLASH accesses
365 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
366 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
371 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
372 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
373 OR_SCY_3_CLK | OR_EHTR | OR_BI)
375 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
376 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
377 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
380 * BR2/3 and OR2/3 (SDRAM)
383 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
384 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
385 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
387 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
388 #define CFG_OR_TIMING_SDRAM 0x00000A00
390 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
391 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
393 #ifndef CONFIG_CAN_DRIVER
394 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
395 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
396 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
397 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
398 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
399 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
400 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
401 BR_PS_8 | BR_MS_UPMB | BR_V )
402 #endif /* CONFIG_CAN_DRIVER */
405 * Memory Periodic Timer Prescaler
407 * The Divider for PTA (refresh timer) configuration is based on an
408 * example SDRAM configuration (64 MBit, one bank). The adjustment to
409 * the number of chip selects (NCS) and the actually needed refresh
410 * rate is done by setting MPTPR.
412 * PTA is calculated from
413 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
415 * gclk CPU clock (not bus clock!)
416 * Trefresh Refresh cycle * 4 (four word bursts used)
418 * 4096 Rows from SDRAM example configuration
419 * 1000 factor s -> ms
420 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
421 * 4 Number of refresh cycles per period
422 * 64 Refresh cycle in ms per number of rows
423 * --------------------------------------------
424 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
426 * 50 MHz => 50.000.000 / Divider = 98
427 * 66 Mhz => 66.000.000 / Divider = 129
428 * 80 Mhz => 80.000.000 / Divider = 156
430 #define CFG_MAMR_PTA 129
433 * For 16 MBit, refresh rates could be 31.3 us
434 * (= 64 ms / 2K = 125 / quad bursts).
435 * For a simpler initialization, 15.6 us is used instead.
437 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
438 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
440 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
441 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
443 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
444 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
445 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
448 * MAMR settings for SDRAM
452 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
453 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
454 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
456 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
457 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
458 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
462 * Internal Definitions
466 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
467 #define BOOTFLAG_WARM 0x02 /* Software reboot */
469 #endif /* __CONFIG_H */