4 #define CONFIG_SYS_TEXT_BASE 0x80F00000
6 /*****************************************************************************
8 * These settings must match the way _your_ board is set up
10 *****************************************************************************/
11 /* for the AY-Revision which does not use the HRCW */
12 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
14 /* What is the oscillator's (UX2) frequency in Hz? */
15 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
17 /* How is switch S2 set? We really only want the MODCK[1-3] bits, so
18 * only the 3 least significant bits are important.
20 #define CONFIG_SYS_SBC_S2 0x04
22 /* What should MODCK_H be? It is dependent on the oscillator
23 * frequency, MODCK[1-3], and desired CPM and core frequencies.
24 * Some example values (all frequencies are in MHz):
26 * MODCK_H MODCK[1-3] Osc CPM Core
32 #define CONFIG_SYS_SBC_MODCK_H 0x06
34 #define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */
35 #undef CONFIG_SYS_SBC_BOOT_LOW
37 /* What should the base address of the main FLASH be and how big is
38 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
39 * The main FLASH is whichever is connected to *CS0. U-Boot expects
40 * this to be the SIMM.
42 #define CONFIG_SYS_FLASH0_BASE 0x80000000
43 #define CONFIG_SYS_FLASH0_SIZE 16
45 /* What should the base address of the secondary FLASH be and how big
46 * is it (in Mbytes)? The secondary FLASH is whichever is connected
47 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
48 * want it enabled, don't define these constants.
50 #define CONFIG_SYS_FLASH1_BASE 0
51 #define CONFIG_SYS_FLASH1_SIZE 0
52 #undef CONFIG_SYS_FLASH1_BASE
53 #undef CONFIG_SYS_FLASH1_SIZE
55 /* What should be the base address of SDRAM DIMM and how big is
58 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
59 #define CONFIG_SYS_SDRAM0_SIZE 64
61 /* What should be the base address of SDRAM DIMM and how big is
64 #define CONFIG_SYS_SDRAM1_BASE 0x04000000
65 #define CONFIG_SYS_SDRAM1_SIZE 32
67 /* What should be the base address of the LEDs and switch S0?
68 * If you don't want them enabled, don't define this.
70 #define CONFIG_SYS_LED_BASE 0x00000000
73 * select serial console configuration
75 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
76 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
79 * if CONFIG_CONS_NONE is defined, then the serial console routines must
82 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
83 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
84 #undef CONFIG_CONS_NONE /* define if console on neither */
85 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
88 * select ethernet configuration
90 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
91 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
94 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
95 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
97 #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
98 #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
99 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
100 #define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
102 #if ( CONFIG_ETHER_INDEX == 3 )
107 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
108 * - Enable Half Duplex in FSMR
110 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
111 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
112 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
113 /*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
114 # define CONFIG_SYS_FCC_PSMR 0
116 #else /* CONFIG_ETHER_INDEX */
117 # error "on RPX Super ethernet must be FCC3"
118 #endif /* CONFIG_ETHER_INDEX */
120 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
121 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
122 #define CONFIG_SYS_I2C_SLAVE 0x7F
125 /* Define this to reserve an entire FLASH sector (256 KB) for
126 * environment variables. Otherwise, the environment will be
127 * put in the same sector as U-Boot, and changing variables
128 * will erase U-Boot temporarily
130 #define CONFIG_ENV_IN_OWN_SECT
132 /* Define to allow the user to overwrite serial and ethaddr */
133 #define CONFIG_ENV_OVERWRITE
135 /* What should the console's baud rate be? */
136 #define CONFIG_BAUDRATE 115200
138 /* Ethernet MAC address */
139 #define CONFIG_ETHADDR 08:00:22:50:70:63
141 #define CONFIG_IPADDR 192.168.1.99
142 #define CONFIG_SERVERIP 192.168.1.3
144 /* Set to a positive value to delay for running BOOTCOMMAND */
145 #define CONFIG_BOOTDELAY -1
147 /* undef this to save memory */
148 #define CONFIG_SYS_LONGHELP
150 /* Monitor Command Prompt */
156 #define CONFIG_BOOTP_BOOTFILESIZE
157 #define CONFIG_BOOTP_BOOTPATH
158 #define CONFIG_BOOTP_GATEWAY
159 #define CONFIG_BOOTP_HOSTNAME
163 * Command line configuration.
165 #include <config_cmd_default.h>
167 #define CONFIG_CMD_IMMAP
168 #define CONFIG_CMD_ASKENV
169 #define CONFIG_CMD_I2C
170 #define CONFIG_CMD_REGINFO
172 #undef CONFIG_CMD_KGDB
175 /* Where do the internal registers live? */
176 #define CONFIG_SYS_IMMR 0xF0000000
178 /* Where do the on board registers (CS4) live? */
179 #define CONFIG_SYS_REGS_BASE 0xFA000000
181 /*****************************************************************************
183 * You should not have to modify any of the following settings
185 *****************************************************************************/
187 #define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
188 #define CONFIG_CPM2 1 /* Has a CPM2 */
190 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
191 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
194 * Miscellaneous configurable options
196 #if defined(CONFIG_CMD_KGDB)
197 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
199 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
202 /* Print Buffer Size */
203 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
205 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */
207 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
209 #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
210 #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
212 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
214 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
217 * Low Level Configuration Settings
218 * (address mappings, register initial values, etc.)
219 * You should know what you are doing if you make changes here.
222 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
223 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
225 /*-----------------------------------------------------------------------
226 * Hard Reset Configuration Words
228 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
229 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
231 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
232 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
234 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
235 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
236 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
237 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
239 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\
241 CONFIG_SYS_SBC_HRCW_IMMR |\
246 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
247 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
250 #define CONFIG_SYS_HRCW_SLAVE1 0
251 #define CONFIG_SYS_HRCW_SLAVE2 0
252 #define CONFIG_SYS_HRCW_SLAVE3 0
253 #define CONFIG_SYS_HRCW_SLAVE4 0
254 #define CONFIG_SYS_HRCW_SLAVE5 0
255 #define CONFIG_SYS_HRCW_SLAVE6 0
256 #define CONFIG_SYS_HRCW_SLAVE7 0
258 /*-----------------------------------------------------------------------
259 * Definitions for initial stack pointer and data area (in DPRAM)
261 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
262 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
263 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
264 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
266 /*-----------------------------------------------------------------------
267 * Start addresses for the final memory configuration
268 * (Set up by the startup code)
269 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
270 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
272 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
274 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
275 # define CONFIG_SYS_RAMBOOT
278 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
279 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
282 * For booting Linux, the board info and command line data
283 * have to be in the first 8 MB of memory, since this is
284 * the maximum mapped by the Linux kernel during initialization.
286 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
288 /*-----------------------------------------------------------------------
289 * FLASH and environment organization
291 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
292 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
294 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
295 #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
297 #ifndef CONFIG_SYS_RAMBOOT
298 # define CONFIG_ENV_IS_IN_FLASH 1
300 # ifdef CONFIG_ENV_IN_OWN_SECT
301 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
302 # define CONFIG_ENV_SECT_SIZE 0x40000
304 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
305 # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
306 # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
307 # endif /* CONFIG_ENV_IN_OWN_SECT */
309 # define CONFIG_ENV_IS_IN_NVRAM 1
310 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
311 # define CONFIG_ENV_SIZE 0x200
312 #endif /* CONFIG_SYS_RAMBOOT */
314 /*-----------------------------------------------------------------------
315 * Cache Configuration
317 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
319 #if defined(CONFIG_CMD_KGDB)
320 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
323 /*-----------------------------------------------------------------------
324 * HIDx - Hardware Implementation-dependent Registers 2-11
325 *-----------------------------------------------------------------------
326 * HID0 also contains cache control - initially enable both caches and
327 * invalidate contents, then the final state leaves only the instruction
328 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
329 * but Soft reset does not.
331 * HID1 has only read-only information - nothing to set.
333 #define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\
340 #define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
344 #define CONFIG_SYS_HID2 0
346 /*-----------------------------------------------------------------------
347 * RMR - Reset Mode Register
348 *-----------------------------------------------------------------------
350 #define CONFIG_SYS_RMR 0
352 /*-----------------------------------------------------------------------
353 * BCR - Bus Configuration 4-25
354 *-----------------------------------------------------------------------
356 #define CONFIG_SYS_BCR (BCR_EBM |\
361 /*-----------------------------------------------------------------------
362 * SIUMCR - SIU Module Configuration 4-31
363 *-----------------------------------------------------------------------
366 #define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
371 /*-----------------------------------------------------------------------
372 * SYPCR - System Protection Control 11-9
373 * SYPCR can only be written once after reset!
374 *-----------------------------------------------------------------------
375 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
377 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
384 /*-----------------------------------------------------------------------
385 * TMCNTSC - Time Counter Status and Control 4-40
386 *-----------------------------------------------------------------------
387 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
388 * and enable Time Counter
390 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
395 /*-----------------------------------------------------------------------
396 * PISCR - Periodic Interrupt Status and Control 4-42
397 *-----------------------------------------------------------------------
398 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
401 #define CONFIG_SYS_PISCR (PISCR_PS |\
405 /*-----------------------------------------------------------------------
406 * SCCR - System Clock Control 9-8
407 *-----------------------------------------------------------------------
409 #define CONFIG_SYS_SCCR (SCCR_DFBRG01)
411 /*-----------------------------------------------------------------------
412 * RCCR - RISC Controller Configuration 13-7
413 *-----------------------------------------------------------------------
415 #define CONFIG_SYS_RCCR 0
418 * Init Memory Controller:
420 * Bank Bus Machine PortSz Device
421 * ---- --- ------- ------ ------
422 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
423 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
424 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
426 * 4 60x GPCM 8 bit Board Regs, LEDs, switches
439 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
445 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
454 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
459 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
461 ORxS_ROWST_PBI0_A8 |\
465 #define CONFIG_SYS_PSDMR 0x014DA412
466 #define CONFIG_SYS_PSRT 0x79
472 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
477 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
479 ORxS_ROWST_PBI0_A9 |\
482 #define CONFIG_SYS_LSDMR 0x0169A512
483 #define CONFIG_SYS_LSRT 0x79
485 #define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK)
487 /* Bank 4 - On board registers
490 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
495 #define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
501 #endif /* __CONFIG_H */