3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
25 * U-Boot port on RPXlite board
34 * High Level Configuration Options
39 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
40 #define CONFIG_RPXLITE 1
42 #define CONFIG_SYS_TEXT_BASE 0xfff00000
44 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45 #undef CONFIG_8xx_CONS_SMC2
46 #undef CONFIG_8xx_CONS_NONE
47 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
49 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
51 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
54 #undef CONFIG_BOOTARGS
55 #define CONFIG_BOOTCOMMAND \
57 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
61 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
62 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64 #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
70 #define CONFIG_BOOTP_SUBNETMASK
71 #define CONFIG_BOOTP_GATEWAY
72 #define CONFIG_BOOTP_HOSTNAME
73 #define CONFIG_BOOTP_BOOTPATH
74 #define CONFIG_BOOTP_BOOTFILESIZE
78 * Command line configuration.
80 #include <config_cmd_default.h>
84 * Miscellaneous configurable options
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
87 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
88 #if defined(CONFIG_CMD_KGDB)
89 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
91 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
94 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
95 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
97 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
98 #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
100 #define CONFIG_SYS_RESET_ADDRESS 0x09900000
102 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
104 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
106 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
109 * Low Level Configuration Settings
110 * (address mappings, register initial values, etc.)
111 * You should know what you are doing if you make changes here.
113 /*-----------------------------------------------------------------------
114 * Internal Memory Mapped Register
116 #define CONFIG_SYS_IMMR 0xFA200000
118 /*-----------------------------------------------------------------------
119 * Definitions for initial stack pointer and data area (in DPRAM)
121 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
122 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
123 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
124 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
125 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
127 /*-----------------------------------------------------------------------
128 * Start addresses for the final memory configuration
129 * (Set up by the startup code)
130 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
132 #define CONFIG_SYS_SDRAM_BASE 0x00000000
133 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
135 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
137 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
139 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
140 #endif /* CONFIG_BZIP2 */
143 * For booting Linux, the board info and command line data
144 * have to be in the first 8 MB of memory, since this is
145 * the maximum mapped by the Linux kernel during initialization.
147 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
149 /*-----------------------------------------------------------------------
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
153 #define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
155 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
158 #define CONFIG_SYS_DIRECT_FLASH_TFTP
160 #define CONFIG_ENV_IS_IN_FLASH 1
161 #define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
162 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
164 #define CONFIG_ENV_OVERWRITE
166 /*-----------------------------------------------------------------------
167 * Cache Configuration
169 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
170 #if defined(CONFIG_CMD_KGDB)
171 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
174 /*-----------------------------------------------------------------------
175 * SYPCR - System Protection Control 11-9
176 * SYPCR can only be written once after reset!
177 *-----------------------------------------------------------------------
178 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
180 #if defined(CONFIG_WATCHDOG)
181 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
182 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
184 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
187 /*-----------------------------------------------------------------------
188 * SIUMCR - SIU Module Configuration 11-6
189 *-----------------------------------------------------------------------
190 * PCMCIA config., multi-function pin tri-state
192 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
194 /*-----------------------------------------------------------------------
195 * TBSCR - Time Base Status and Control 11-26
196 *-----------------------------------------------------------------------
197 * Clear Reference Interrupt Status, Timebase freezing enabled
199 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
201 /*-----------------------------------------------------------------------
202 * RTCSC - Real-Time Clock Status and Control Register 11-27
203 *-----------------------------------------------------------------------
205 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
206 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
208 /*-----------------------------------------------------------------------
209 * PISCR - Periodic Interrupt Status and Control 11-31
210 *-----------------------------------------------------------------------
211 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
213 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
215 /*-----------------------------------------------------------------------
216 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
217 *-----------------------------------------------------------------------
218 * Reset PLL lock status sticky bit, timer expired status bit and timer
219 * interrupt status bit
221 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
223 /* up to 50 MHz we use a 1:1 clock */
224 #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
226 /*-----------------------------------------------------------------------
227 * SCCR - System Clock and reset Control Register 15-27
228 *-----------------------------------------------------------------------
229 * Set clock output, timebase and RTC source and divider,
230 * power management and some other internal clocks
232 #define SCCR_MASK SCCR_EBDF00
233 /* up to 50 MHz we use a 1:1 clock */
234 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
236 /*-----------------------------------------------------------------------
238 *-----------------------------------------------------------------------
241 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
242 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
243 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
244 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
245 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
246 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
247 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
248 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
250 /*-----------------------------------------------------------------------
251 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
252 *-----------------------------------------------------------------------
255 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
257 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
258 #undef CONFIG_IDE_LED /* LED for ide not supported */
259 #undef CONFIG_IDE_RESET /* reset for ide not supported */
261 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
262 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
264 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
266 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
268 /* Offset for data I/O */
269 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
271 /* Offset for normal register accesses */
272 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
274 /* Offset for alternate registers */
275 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
277 /*-----------------------------------------------------------------------
279 *-----------------------------------------------------------------------
282 /*#define CONFIG_SYS_DER 0x2002000F*/
283 #define CONFIG_SYS_DER 0
286 * Init Memory Controller:
288 * BR0 and OR0 (FLASH)
291 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
292 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
294 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
295 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
297 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
298 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
301 * BR1 and OR1 (SDRAM)
304 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
305 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
307 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
308 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
310 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
311 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
313 /* RPXLITE mem setting */
314 #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
315 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
316 #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
317 #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
320 * Memory Periodic Timer Prescaler
323 /* periodic timer for refresh */
324 #define CONFIG_SYS_MAMR_PTA 58
327 * Refresh clock Prescalar
329 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
332 * MAMR settings for SDRAM
335 /* 10 column SDRAM */
336 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
337 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
338 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
340 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
341 /* Configuration variable added by yooth. */
342 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
347 * Board Status and Control Registers
351 #define BCSR0 0xFA400000
352 #define BCSR1 0xFA400001
353 #define BCSR2 0xFA400002
354 #define BCSR3 0xFA400003
356 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
357 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
358 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
359 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
360 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
361 #define BCSR0_COLTEST 0x20
362 #define BCSR0_ETHLPBK 0x40
363 #define BCSR0_ETHEN 0x80
365 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
366 #define BCSR1_PCVCTL6 0x02
367 #define BCSR1_PCVCTL5 0x04
368 #define BCSR1_PCVCTL4 0x08
369 #define BCSR1_IPB5SEL 0x10
371 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
372 #define BCSR2_ENUSBCLK 0x10
373 #define BCSR2_USBPWREN 0x20
374 #define BCSR2_USBSPD 0x40
375 #define BCSR2_USBSUSP 0x80
377 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
378 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
379 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
380 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
381 #define BCSR3_D27 0x10 /* Dip Switch settings */
382 #define BCSR3_D26 0x20
383 #define BCSR3_D25 0x40
384 #define BCSR3_D24 0x80
386 #endif /* __CONFIG_H */