2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
12 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
13 * U-Boot port on RPXlite board
19 #define RPXClassic_50MHz
22 * High Level Configuration Options
26 #define CONFIG_MPC860 1
27 #define CONFIG_RPXCLASSIC 1
29 #define CONFIG_SYS_TEXT_BASE 0xff000000
31 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
32 #undef CONFIG_8xx_CONS_SMC2
33 #undef CONFIG_8xx_CONS_NONE
34 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
36 /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
37 #define CONFIG_FEC_ENET
38 #ifdef CONFIG_FEC_ENET
39 #define CONFIG_SYS_DISCOVER_PHY 1
41 #endif /* CONFIG_FEC_ENET */
42 #define CONFIG_MISC_INIT_R
44 /* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
46 #define CONFIG_VIDEO_SED13806
47 #define CONFIG_NEC_NL6448BC20
48 #define CONFIG_VIDEO_SED13806_16BPP
50 #define CONFIG_CFB_CONSOLE
51 #define CONFIG_VIDEO_LOGO
52 #define CONFIG_VIDEO_BMP_LOGO
53 #define CONFIG_CONSOLE_EXTRA_INFO
54 #define CONFIG_VGA_AS_SINGLE_DEVICE
55 #define CONFIG_VIDEO_SW_CURSOR
59 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
61 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
64 #define CONFIG_ZERO_BOOTDELAY_CHECK 1
66 #undef CONFIG_BOOTARGS
67 #define CONFIG_BOOTCOMMAND \
69 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
73 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
74 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
76 #undef CONFIG_WATCHDOG /* watchdog disabled */
81 #define CONFIG_BOOTP_SUBNETMASK
82 #define CONFIG_BOOTP_GATEWAY
83 #define CONFIG_BOOTP_HOSTNAME
84 #define CONFIG_BOOTP_BOOTPATH
85 #define CONFIG_BOOTP_BOOTFILESIZE
88 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
92 * Command line configuration.
94 #include <config_cmd_default.h>
96 #define CONFIG_CMD_ELF
100 * Miscellaneous configurable options
102 #define CONFIG_SYS_RESET_ADDRESS 0x80000000
103 #define CONFIG_SYS_LONGHELP /* undef to save memory */
104 #if defined(CONFIG_CMD_KGDB)
105 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
107 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113 #define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
114 #define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
116 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
118 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
121 * Low Level Configuration Settings
122 * (address mappings, register initial values, etc.)
123 * You should know what you are doing if you make changes here.
125 /*-----------------------------------------------------------------------
126 * Internal Memory Mapped Register
128 #define CONFIG_SYS_IMMR 0xFA200000
130 /*-----------------------------------------------------------------------------
132 *-----------------------------------------------------------------------------
134 #define CONFIG_SYS_I2C_SPEED 50000
135 #define CONFIG_SYS_I2C_SLAVE 0x34
138 /* enable I2C and select the hardware/software driver */
139 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
140 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
142 #if defined(CONFIG_SYS_I2C_SOFT)
143 #define CONFIG_SYS_I2C 1
145 * Software (bit-bang) I2C driver configuration
147 #define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
148 #define I2C_ACTIVE (iop->pdir |= 0x00000010)
149 #define I2C_TRISTATE (iop->pdir &= ~0x00000010)
150 #define I2C_READ ((iop->pdat & 0x00000010) != 0)
151 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
152 else iop->pdat &= ~0x00000010
153 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
154 else iop->pdat &= ~0x00000020
155 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
158 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
159 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x34
162 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
163 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
164 /* mask of address bits that overflow into the "EEPROM chip address" */
165 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
167 /*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
170 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
171 #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
172 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
173 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
175 /*-----------------------------------------------------------------------
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
180 #define CONFIG_SYS_SDRAM_BASE 0x00000000
181 #define CONFIG_SYS_FLASH_BASE 0xFF000000
183 #if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
186 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
188 #define CONFIG_SYS_MONITOR_BASE 0xFF000000
189 /*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
190 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
193 * For booting Linux, the board info and command line data
194 * have to be in the first 8 MB of memory, since this is
195 * the maximum mapped by the Linux kernel during initialization.
197 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
199 /*-----------------------------------------------------------------------
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
205 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
209 #define CONFIG_ENV_IS_IN_FLASH 1
210 #define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
211 #define CONFIG_ENV_SECT_SIZE 0x8000
212 #define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
214 #define CONFIG_ENV_IS_IN_NVRAM 1
215 #define CONFIG_ENV_ADDR 0xfa000100
216 #define CONFIG_ENV_SIZE 0x1000
219 /*-----------------------------------------------------------------------
220 * Cache Configuration
222 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
223 #if defined(CONFIG_CMD_KGDB)
224 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
227 /*-----------------------------------------------------------------------
228 * SYPCR - System Protection Control 11-9
229 * SYPCR can only be written once after reset!
230 *-----------------------------------------------------------------------
231 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
233 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
236 /*-----------------------------------------------------------------------
237 * SIUMCR - SIU Module Configuration 11-6
238 *-----------------------------------------------------------------------
239 * PCMCIA config., multi-function pin tri-state
241 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
243 /*-----------------------------------------------------------------------
244 * TBSCR - Time Base Status and Control 11-26
245 *-----------------------------------------------------------------------
246 * Clear Reference Interrupt Status, Timebase freezing enabled
248 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
250 /*-----------------------------------------------------------------------
251 * RTCSC - Real-Time Clock Status and Control Register 11-27
252 *-----------------------------------------------------------------------
254 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
255 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
257 /*-----------------------------------------------------------------------
258 * PISCR - Periodic Interrupt Status and Control 11-31
259 *-----------------------------------------------------------------------
260 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
262 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
264 /*-----------------------------------------------------------------------
265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
266 *-----------------------------------------------------------------------
267 * Reset PLL lock status sticky bit, timer expired status bit and timer
268 * interrupt status bit
270 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
272 /* up to 50 MHz we use a 1:1 clock */
273 #define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
275 /*-----------------------------------------------------------------------
276 * SCCR - System Clock and reset Control Register 15-27
277 *-----------------------------------------------------------------------
278 * Set clock output, timebase and RTC source and divider,
279 * power management and some other internal clocks
281 #define SCCR_MASK SCCR_EBDF00
282 /* up to 50 MHz we use a 1:1 clock */
283 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
285 /*-----------------------------------------------------------------------
287 *-----------------------------------------------------------------------
290 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
291 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
292 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
293 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
294 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
295 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
296 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
297 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
299 /*-----------------------------------------------------------------------
300 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
301 *-----------------------------------------------------------------------
304 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
305 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
307 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
308 #undef CONFIG_IDE_LED /* LED for ide not supported */
309 #undef CONFIG_IDE_RESET /* reset for ide not supported */
311 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
312 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
314 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
316 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
318 /* Offset for data I/O */
319 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
321 /* Offset for normal register accesses */
322 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
324 /* Offset for alternate registers */
325 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
327 /*-----------------------------------------------------------------------
329 *-----------------------------------------------------------------------
332 /* #define CONFIG_SYS_DER 0x2002000F */
333 #define CONFIG_SYS_DER 0
336 * Init Memory Controller:
338 * BR0 and OR0 (FLASH)
341 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
342 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
344 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
345 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
347 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
348 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
351 * BR1 and OR1 (SDRAM)
354 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
355 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
357 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
358 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
360 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
361 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
363 /* RPXLITE mem setting */
364 #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
365 #define CONFIG_SYS_OR3_PRELIM 0xff7f8970
366 #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
367 #define CONFIG_SYS_OR4_PRELIM 0xFFF80970
369 /* ECCX CS settings */
370 #define SED13806_OR 0xFFC00108 /* - 4 Mo
373 #define SED13806_REG_ADDR 0xa0000000
374 #define SED13806_ACCES 0x801 /* 16 bit access */
377 /* Global definitions for the ECCX board */
378 #define ECCX_CSR_ADDR (0xfac00000)
379 #define ECCX_CSR8_OFFSET (0x8)
380 #define ECCX_CSR11_OFFSET (0xB)
381 #define ECCX_CSR12_OFFSET (0xC)
383 #define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
384 #define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
385 #define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
388 #define REG_GPIO_CTRL 0x008
390 /* Definitions for CSR8 */
391 #define ECCX_ENEPSON 0x80 /* Bit 0:
392 0= disable and reset SED1386
394 /* Bit 1: 0= SED1386 in Big Endian mode */
395 /* 1= SED1386 in little endian mode */
399 /* Bit 2,3: Selection */
401 /* 01 = CS2 is used for the SED1386 */
402 /* 10 = CS5 is used for the SED1386 */
404 #define ECCX_CS2 0x10
405 #define ECCX_CS5 0x20
407 /* Definitions for CSR12 */
409 #define ECCX_860 0x01
412 * Memory Periodic Timer Prescaler
415 /* periodic timer for refresh */
416 #define CONFIG_SYS_MAMR_PTA 58
419 * Refresh clock Prescalar
421 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
424 * MAMR settings for SDRAM
427 /* 10 column SDRAM */
428 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
429 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
430 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
432 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
433 /* Configuration variable added by yooth. */
434 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
439 * Board Status and Control Registers
443 #define BCSR0 0xFA400000
444 #define BCSR1 0xFA400001
445 #define BCSR2 0xFA400002
446 #define BCSR3 0xFA400003
448 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
449 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
450 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
451 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
452 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
453 #define BCSR0_COLTEST 0x20
454 #define BCSR0_ETHLPBK 0x40
455 #define BCSR0_ETHEN 0x80
457 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
458 #define BCSR1_PCVCTL6 0x02
459 #define BCSR1_PCVCTL5 0x04
460 #define BCSR1_PCVCTL4 0x08
461 #define BCSR1_IPB5SEL 0x10
463 #define BCSR2_MIIRST 0x80
464 #define BCSR2_MIIPWRDWN 0x40
465 #define BCSR2_MIICTL 0x08
467 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
468 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
469 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
470 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
471 #define BCSR3_D27 0x10 /* Dip Switch settings */
472 #define BCSR3_D26 0x20
473 #define BCSR3_D25 0x40
474 #define BCSR3_D24 0x80
478 * Environment setting
481 /* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
482 /* #define CONFIG_IPADDR 10.10.106.1 */
483 /* #define CONFIG_SERVERIP 10.10.104.11 */
485 #endif /* __CONFIG_H */