include/configs/PPChameleonEVB.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * (C) Copyright 2003
   6  * DAVE Srl
   7  *
   8  * http://www.dave-tech.it
   9  * http://www.wawnet.biz
  10  * mailto:info@wawnet.biz
  11  *
  12  * Credits: Stefan Roese, Wolfgang Denk
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 /*
  18  * board/config.h - configuration options, board specific
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 #define CONFIG_PPCHAMELEON_MODULE_BA    0       /* Basic    Model */
  25 #define CONFIG_PPCHAMELEON_MODULE_ME    1       /* Medium   Model */
  26 #define CONFIG_PPCHAMELEON_MODULE_HI    2       /* High-End Model */
  27 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  28 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  29 #endif
  30
  31
  32 /* Only one of the following two symbols must be defined (default is 25 MHz)
  33  * CONFIG_PPCHAMELEON_CLK_25
  34  * CONFIG_PPCHAMELEON_CLK_33
  35  */
  36 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  37 #define CONFIG_PPCHAMELEON_CLK_25
  38 #endif
  39
  40 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  41 #error "* Two external frequencies (SysClk) are defined! *"
  42 #endif
  43
  44 #undef  CONFIG_PPCHAMELEON_SMI712
  45
  46 /*
  47  * Debug stuff
  48  */
  49 #undef  __DEBUG_START_FROM_SRAM__
  50 #define __DISABLE_MACHINE_EXCEPTION__
  51
  52 #ifdef __DEBUG_START_FROM_SRAM__
  53 #define CONFIG_SYS_DUMMY_FLASH_SIZE             1024*1024*4
  54 #endif
  55
  56 /*
  57  * High Level Configuration Options
  58  * (easy to change)
  59  */
  60
  61 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  62 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  63 #define CONFIG_PPCHAMELEONEVB   1       /* ...on a PPChameleonEVB board */
  64
  65 #define CONFIG_SYS_TEXT_BASE    0xFFFB0000      /* Reserve 320 kB for Monitor */
  66 #define CONFIG_SYS_LDSCRIPT     "board/dave/PPChameleonEVB/u-boot.lds"
  67
  68 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  69 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  70
  71
  72 #ifdef CONFIG_PPCHAMELEON_CLK_25
  73 # define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
  74 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  75 # define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
  76 #else
  77 # error "* External frequency (SysClk) not defined! *"
  78 #endif
  79
  80 #define CONFIG_BAUDRATE         115200
  81 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  82
  83 #undef  CONFIG_BOOTARGS
  84
  85 /* Ethernet stuff */
  86 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  87 #define CONFIG_ETHADDR  00:50:c2:1e:af:fe
  88 #define CONFIG_HAS_ETH1
  89 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
  90
  91 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  92 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  93
  94 #undef CONFIG_EXT_PHY
  95
  96 #define CONFIG_PPC4xx_EMAC
  97 #define CONFIG_MII              1       /* MII PHY management           */
  98 #ifndef  CONFIG_EXT_PHY
  99 #define CONFIG_PHY_ADDR         1       /* EMAC0 PHY address            */
 100 #define CONFIG_PHY1_ADDR        2       /* EMAC1 PHY address            */
 101 #else
 102 #define CONFIG_PHY_ADDR         2       /* PHY address                  */
 103 #endif
 104 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
 105
 106
 107 /*
 108  * BOOTP options
 109  */
 110 #define CONFIG_BOOTP_BOOTFILESIZE
 111 #define CONFIG_BOOTP_BOOTPATH
 112 #define CONFIG_BOOTP_GATEWAY
 113 #define CONFIG_BOOTP_HOSTNAME
 114
 115
 116 /*
 117  * Command line configuration.
 118  */
 119 #include <config_cmd_default.h>
 120
 121 #define CONFIG_CMD_DATE
 122 #define CONFIG_CMD_DHCP
 123 #define CONFIG_CMD_ELF
 124 #define CONFIG_CMD_EEPROM
 125 #define CONFIG_CMD_I2C
 126 #define CONFIG_CMD_IRQ
 127 #define CONFIG_CMD_JFFS2
 128 #define CONFIG_CMD_MII
 129 #define CONFIG_CMD_NAND
 130 #define CONFIG_CMD_NFS
 131 #define CONFIG_CMD_PCI
 132 #define CONFIG_CMD_SNTP
 133
 134
 135 #define CONFIG_MAC_PARTITION
 136 #define CONFIG_DOS_PARTITION
 137
 138 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 139
 140 #define CONFIG_RTC_M41T11       1       /* uses a M41T00 RTC            */
 141 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 142 #define CONFIG_SYS_M41T11_BASE_YEAR     1900
 143
 144 /*
 145  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 146  */
 147 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 148
 149 /* SDRAM timings used in datasheet */
 150 #define CONFIG_SYS_SDRAM_CL            2
 151 #define CONFIG_SYS_SDRAM_tRP           20
 152 #define CONFIG_SYS_SDRAM_tRC           65
 153 #define CONFIG_SYS_SDRAM_tRCD          20
 154 #undef  CONFIG_SYS_SDRAM_tRFC
 155
 156 /*
 157  * Miscellaneous configurable options
 158  */
 159 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 160
 161 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 162
 163 #if defined(CONFIG_CMD_KGDB)
 164 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 165 #else
 166 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 167 #endif
 168 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 169 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 170 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 171
 172 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 173
 174 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 175
 176 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 177 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 178
 179 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 180 #define CONFIG_SYS_NS16550
 181 #define CONFIG_SYS_NS16550_SERIAL
 182 #define CONFIG_SYS_NS16550_REG_SIZE     1
 183 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 184
 185 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK             /* no external serial clock used */
 186 #define CONFIG_SYS_BASE_BAUD            691200
 187
 188 /* The following table includes the supported baudrates */
 189 #define CONFIG_SYS_BAUDRATE_TABLE       \
 190         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 191          57600, 115200, 230400, 460800, 921600 }
 192
 193 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 194 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 195
 196 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 197
 198 /*-----------------------------------------------------------------------
 199  * NAND-FLASH stuff
 200  *-----------------------------------------------------------------------
 201  */
 202
 203 /*
 204  * nand device 1 on dave (PPChameleonEVB) needs more time,
 205  * so we just introduce additional wait in nand_wait(),
 206  * effectively for both devices.
 207  */
 208 #define PPCHAMELON_NAND_TIMER_HACK
 209
 210 #define CONFIG_SYS_NAND0_BASE 0xFF400000
 211 #define CONFIG_SYS_NAND1_BASE 0xFF000000
 212 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
 213 #define NAND_BIG_DELAY_US       25
 214 #define CONFIG_SYS_MAX_NAND_DEVICE      2       /* Max number of NAND devices */
 215
 216 #define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)   /* our CE is GPIO1 */
 217 #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)   /* our RDY is GPIO4 */
 218 #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)   /* our CLE is GPIO2 */
 219 #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)   /* our ALE is GPIO3 */
 220
 221 #define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
 222 #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 223 #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 224 #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
 225
 226 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 227 { \
 228         switch((unsigned long)nandptr) \
 229         { \
 230             case CONFIG_SYS_NAND0_BASE: \
 231                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
 232                 break; \
 233             case CONFIG_SYS_NAND1_BASE: \
 234                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
 235                 break; \
 236         } \
 237 } while(0)
 238
 239 #define MACRO_NAND_ENABLE_CE(nandptr) do \
 240 { \
 241         switch((unsigned long)nandptr) \
 242         { \
 243             case CONFIG_SYS_NAND0_BASE: \
 244                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
 245                 break; \
 246             case CONFIG_SYS_NAND1_BASE: \
 247                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
 248                 break; \
 249         } \
 250 } while(0)
 251
 252 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
 253 { \
 254         switch((unsigned long)nandptr) \
 255         { \
 256             case CONFIG_SYS_NAND0_BASE: \
 257                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
 258                 break; \
 259             case CONFIG_SYS_NAND1_BASE: \
 260                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
 261                 break; \
 262         } \
 263 } while(0)
 264
 265 #define MACRO_NAND_CTL_SETALE(nandptr) do \
 266 { \
 267         switch((unsigned long)nandptr) \
 268         { \
 269             case CONFIG_SYS_NAND0_BASE: \
 270                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
 271                 break; \
 272             case CONFIG_SYS_NAND1_BASE: \
 273                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
 274                 break; \
 275         } \
 276 } while(0)
 277
 278 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 279 { \
 280         switch((unsigned long)nandptr) \
 281         { \
 282             case CONFIG_SYS_NAND0_BASE: \
 283                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
 284                 break; \
 285             case CONFIG_SYS_NAND1_BASE: \
 286                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
 287                 break; \
 288         } \
 289 } while(0)
 290
 291 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 292         switch((unsigned long)nandptr) { \
 293         case CONFIG_SYS_NAND0_BASE: \
 294                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
 295                 break; \
 296         case CONFIG_SYS_NAND1_BASE: \
 297                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
 298                 break; \
 299         } \
 300 } while(0)
 301
 302 /*-----------------------------------------------------------------------
 303  * PCI stuff
 304  *-----------------------------------------------------------------------
 305  */
 306 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 307 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 308 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 309
 310 #define CONFIG_PCI                      /* include pci support          */
 311 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 312 #define CONFIG_PCI_HOST PCI_HOST_FORCE   /* select pci host function     */
 313 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 314                                         /* resource configuration       */
 315
 316 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 317
 318 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* PCI Vendor ID: IBM   */
 319 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: ---   */
 320 #define CONFIG_SYS_PCI_CLASSCODE        0x0b20  /* PCI Class Code: Processor/PPC*/
 321
 322 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 323 #define CONFIG_SYS_PCI_PTM1MS   0xfc000001      /* 64MB, enable hard-wired to 1 */
 324 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 325 #define CONFIG_SYS_PCI_PTM2LA   0xffc00000      /* point to flash               */
 326 #define CONFIG_SYS_PCI_PTM2MS   0xffc00001      /* 4MB, enable                  */
 327 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 328
 329 /*-----------------------------------------------------------------------
 330  * Start addresses for the final memory configuration
 331  * (Set up by the startup code)
 332  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 333  */
 334 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 335
 336 /* Reserve 256 kB for Monitor   */
 337 /*
 338 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 339 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 340 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
 341 */
 342
 343 /* Reserve 320 kB for Monitor   */
 344 #define CONFIG_SYS_FLASH_BASE           0xFFFB0000
 345 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 346 #define CONFIG_SYS_MONITOR_LEN          (320 * 1024)
 347
 348 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 349
 350 /*
 351  * For booting Linux, the board info and command line data
 352  * have to be in the first 8 MB of memory, since this is
 353  * the maximum mapped by the Linux kernel during initialization.
 354  */
 355 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 356 /*-----------------------------------------------------------------------
 357  * FLASH organization
 358  */
 359 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 360 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 361
 362 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 363 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 364
 365 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 366 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 367 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 368 /*
 369  * The following defines are added for buggy IOP480 byte interface.
 370  * All other boards should use the standard values (CPCI405 etc.)
 371  */
 372 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 373 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 374 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 375
 376 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 377
 378 /*-----------------------------------------------------------------------
 379  * Environment Variable setup
 380  */
 381 #ifdef ENVIRONMENT_IN_EEPROM
 382
 383 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 384 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 385 #define CONFIG_ENV_SIZE         0x700   /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
 386
 387 #else   /* DEFAULT: environment in flash, using redundand flash sectors */
 388
 389 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 390 #define CONFIG_ENV_ADDR         0xFFFF8000      /* environment starts at the first small sector */
 391 #define CONFIG_ENV_SECT_SIZE    0x2000  /* 8196 bytes may be used for env vars*/
 392 #define CONFIG_ENV_ADDR_REDUND  0xFFFFA000
 393 #define CONFIG_ENV_SIZE_REDUND  0x2000
 394
 395 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 396
 397 #endif  /* ENVIRONMENT_IN_EEPROM */
 398
 399
 400 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 401 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 402
 403 /*-----------------------------------------------------------------------
 404  * I2C EEPROM (CAT24WC16) for environment
 405  */
 406 #define CONFIG_SYS_I2C
 407 #define CONFIG_SYS_I2C_PPC4XX
 408 #define CONFIG_SYS_I2C_PPC4XX_CH0
 409 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 410 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 411
 412 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 413 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 414 /* mask of address bits that overflow into the "EEPROM chip address"    */
 415 /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW   0x07*/
 416 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 417                                         /* 16 byte page write mode using*/
 418                                         /* last 4 bits of the address   */
 419 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 420
 421 /*
 422  * Init Memory Controller:
 423  *
 424  * BR0/1 and OR0/1 (FLASH)
 425  */
 426
 427 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 428
 429 /*-----------------------------------------------------------------------
 430  * External Bus Controller (EBC) Setup
 431  */
 432
 433 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 434 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 435 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 436
 437 /* Memory Bank 1 (External SRAM) initialization                                 */
 438 /* Since this must replace NOR Flash, we use the same settings for CS0          */
 439 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 440 #define CONFIG_SYS_EBC_PB1CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 441
 442 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
 443 #define CONFIG_SYS_EBC_PB2AP            0x92015480
 444 #define CONFIG_SYS_EBC_PB2CR            0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
 445
 446 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
 447 #define CONFIG_SYS_EBC_PB3AP            0x92015480
 448 #define CONFIG_SYS_EBC_PB3CR            0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
 449
 450 #ifdef CONFIG_PPCHAMELEON_SMI712
 451 /*
 452  * Video console (graphic: SMI LynxEM)
 453  */
 454 #define CONFIG_VIDEO
 455 #define CONFIG_CFB_CONSOLE
 456 #define CONFIG_VIDEO_SMI_LYNXEM
 457 #define CONFIG_VIDEO_LOGO
 458 /*#define CONFIG_VIDEO_BMP_LOGO*/
 459 #define CONFIG_CONSOLE_EXTRA_INFO
 460 #define CONFIG_VGA_AS_SINGLE_DEVICE
 461 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
 462 #define CONFIG_SYS_ISA_IO 0xE8000000
 463 /* see also drivers/video/videomodes.c */
 464 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
 465 #endif
 466
 467 /*-----------------------------------------------------------------------
 468  * FPGA stuff
 469  */
 470 /* FPGA internal regs */
 471 #define CONFIG_SYS_FPGA_MODE            0x00
 472 #define CONFIG_SYS_FPGA_STATUS          0x02
 473 #define CONFIG_SYS_FPGA_TS              0x04
 474 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 475 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 476 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 477 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 478 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 479 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 480 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 481 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 482 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 483
 484 /* FPGA Mode Reg */
 485 #define CONFIG_SYS_FPGA_MODE_CF_RESET   0x0001
 486 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 487 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 488 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR   0x2000
 489
 490 /* FPGA Status Reg */
 491 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 492 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 493 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 494 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 495 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 496
 497 #define CONFIG_SYS_FPGA_SPARTAN2        1               /* using Xilinx Spartan 2 now    */
 498 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024        /* 128kByte is enough for XC2S50E*/
 499
 500 /* FPGA program pin configuration */
 501 #define CONFIG_SYS_FPGA_PRG             0x04000000      /* FPGA program pin (ppc output) */
 502 #define CONFIG_SYS_FPGA_CLK             0x02000000      /* FPGA clk pin (ppc output)     */
 503 #define CONFIG_SYS_FPGA_DATA            0x01000000      /* FPGA data pin (ppc output)    */
 504 #define CONFIG_SYS_FPGA_INIT            0x00010000      /* FPGA init pin (ppc input)     */
 505 #define CONFIG_SYS_FPGA_DONE            0x00008000      /* FPGA done pin (ppc input)     */
 506
 507 /*-----------------------------------------------------------------------
 508  * Definitions for initial stack pointer and data area (in data cache)
 509  */
 510 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 511 #define CONFIG_SYS_TEMP_STACK_OCM       1
 512
 513 /* On Chip Memory location */
 514 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 515 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 516 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 517 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 518
 519 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 520 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 521
 522 /*-----------------------------------------------------------------------
 523  * Definitions for GPIO setup (PPC405EP specific)
 524  *
 525  * GPIO0[0]     - External Bus Controller BLAST output
 526  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 527  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 528  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 529  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 530  * GPIO0[24-27] - UART0 control signal inputs/outputs
 531  * GPIO0[28-29] - UART1 data signal input/output
 532  * GPIO0[30]    - EMAC0 input
 533  * GPIO0[31]    - EMAC1 reject packet as output
 534  */
 535 #define CONFIG_SYS_GPIO0_OSRL           0x40000550
 536 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 537 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 538 /*#define CONFIG_SYS_GPIO0_ISR1H        0x15555445*/
 539 #define CONFIG_SYS_GPIO0_ISR1H          0x15555444
 540 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 541 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 542 #define CONFIG_SYS_GPIO0_TCR            0xF7FF8014
 543
 544 #define CONFIG_NO_SERIAL_EEPROM
 545
 546 /*--------------------------------------------------------------------*/
 547
 548 #ifdef CONFIG_NO_SERIAL_EEPROM
 549
 550 /*
 551 !-----------------------------------------------------------------------
 552 ! Defines for entry options.
 553 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
 554 !       are plugged in the board will be utilized as non-ECC DIMMs.
 555 !-----------------------------------------------------------------------
 556 */
 557 #undef          AUTO_MEMORY_CONFIG
 558 #define         DIMM_READ_ADDR 0xAB
 559 #define         DIMM_WRITE_ADDR 0xAA
 560
 561 /* Defines for CPC0_PLLMR1 Register fields */
 562 #define PLL_ACTIVE              0x80000000
 563 #define CPC0_PLLMR1_SSCS        0x80000000
 564 #define PLL_RESET               0x40000000
 565 #define CPC0_PLLMR1_PLLR        0x40000000
 566     /* Feedback multiplier */
 567 #define PLL_FBKDIV              0x00F00000
 568 #define CPC0_PLLMR1_FBDV        0x00F00000
 569 #define PLL_FBKDIV_16           0x00000000
 570 #define PLL_FBKDIV_1            0x00100000
 571 #define PLL_FBKDIV_2            0x00200000
 572 #define PLL_FBKDIV_3            0x00300000
 573 #define PLL_FBKDIV_4            0x00400000
 574 #define PLL_FBKDIV_5            0x00500000
 575 #define PLL_FBKDIV_6            0x00600000
 576 #define PLL_FBKDIV_7            0x00700000
 577 #define PLL_FBKDIV_8            0x00800000
 578 #define PLL_FBKDIV_9            0x00900000
 579 #define PLL_FBKDIV_10           0x00A00000
 580 #define PLL_FBKDIV_11           0x00B00000
 581 #define PLL_FBKDIV_12           0x00C00000
 582 #define PLL_FBKDIV_13           0x00D00000
 583 #define PLL_FBKDIV_14           0x00E00000
 584 #define PLL_FBKDIV_15           0x00F00000
 585     /* Forward A divisor */
 586 #define PLL_FWDDIVA             0x00070000
 587 #define CPC0_PLLMR1_FWDVA       0x00070000
 588 #define PLL_FWDDIVA_8           0x00000000
 589 #define PLL_FWDDIVA_7           0x00010000
 590 #define PLL_FWDDIVA_6           0x00020000
 591 #define PLL_FWDDIVA_5           0x00030000
 592 #define PLL_FWDDIVA_4           0x00040000
 593 #define PLL_FWDDIVA_3           0x00050000
 594 #define PLL_FWDDIVA_2           0x00060000
 595 #define PLL_FWDDIVA_1           0x00070000
 596     /* Forward B divisor */
 597 #define PLL_FWDDIVB             0x00007000
 598 #define CPC0_PLLMR1_FWDVB       0x00007000
 599 #define PLL_FWDDIVB_8           0x00000000
 600 #define PLL_FWDDIVB_7           0x00001000
 601 #define PLL_FWDDIVB_6           0x00002000
 602 #define PLL_FWDDIVB_5           0x00003000
 603 #define PLL_FWDDIVB_4           0x00004000
 604 #define PLL_FWDDIVB_3           0x00005000
 605 #define PLL_FWDDIVB_2           0x00006000
 606 #define PLL_FWDDIVB_1           0x00007000
 607     /* PLL tune bits */
 608 #define PLL_TUNE_MASK           0x000003FF
 609 #define PLL_TUNE_2_M_3          0x00000133      /*  2 <= M <= 3                 */
 610 #define PLL_TUNE_4_M_6          0x00000134      /*  3 <  M <= 6                 */
 611 #define PLL_TUNE_7_M_10         0x00000138      /*  6 <  M <= 10                */
 612 #define PLL_TUNE_11_M_14        0x0000013C      /* 10 <  M <= 14                */
 613 #define PLL_TUNE_15_M_40        0x0000023E      /* 14 <  M <= 40                */
 614 #define PLL_TUNE_VCO_LOW        0x00000000      /* 500MHz <= VCO <=  800MHz     */
 615 #define PLL_TUNE_VCO_HI         0x00000080      /* 800MHz <  VCO <= 1000MHz     */
 616
 617 /* Defines for CPC0_PLLMR0 Register fields */
 618     /* CPU divisor */
 619 #define PLL_CPUDIV              0x00300000
 620 #define CPC0_PLLMR0_CCDV        0x00300000
 621 #define PLL_CPUDIV_1            0x00000000
 622 #define PLL_CPUDIV_2            0x00100000
 623 #define PLL_CPUDIV_3            0x00200000
 624 #define PLL_CPUDIV_4            0x00300000
 625     /* PLB divisor */
 626 #define PLL_PLBDIV              0x00030000
 627 #define CPC0_PLLMR0_CBDV        0x00030000
 628 #define PLL_PLBDIV_1            0x00000000
 629 #define PLL_PLBDIV_2            0x00010000
 630 #define PLL_PLBDIV_3            0x00020000
 631 #define PLL_PLBDIV_4            0x00030000
 632     /* OPB divisor */
 633 #define PLL_OPBDIV              0x00003000
 634 #define CPC0_PLLMR0_OPDV        0x00003000
 635 #define PLL_OPBDIV_1            0x00000000
 636 #define PLL_OPBDIV_2            0x00001000
 637 #define PLL_OPBDIV_3            0x00002000
 638 #define PLL_OPBDIV_4            0x00003000
 639     /* EBC divisor */
 640 #define PLL_EXTBUSDIV           0x00000300
 641 #define CPC0_PLLMR0_EPDV        0x00000300
 642 #define PLL_EXTBUSDIV_2         0x00000000
 643 #define PLL_EXTBUSDIV_3         0x00000100
 644 #define PLL_EXTBUSDIV_4         0x00000200
 645 #define PLL_EXTBUSDIV_5         0x00000300
 646     /* MAL divisor */
 647 #define PLL_MALDIV              0x00000030
 648 #define CPC0_PLLMR0_MPDV        0x00000030
 649 #define PLL_MALDIV_1            0x00000000
 650 #define PLL_MALDIV_2            0x00000010
 651 #define PLL_MALDIV_3            0x00000020
 652 #define PLL_MALDIV_4            0x00000030
 653     /* PCI divisor */
 654 #define PLL_PCIDIV              0x00000003
 655 #define CPC0_PLLMR0_PPFD        0x00000003
 656 #define PLL_PCIDIV_1            0x00000000
 657 #define PLL_PCIDIV_2            0x00000001
 658 #define PLL_PCIDIV_3            0x00000002
 659 #define PLL_PCIDIV_4            0x00000003
 660
 661 #ifdef CONFIG_PPCHAMELEON_CLK_25
 662 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
 663 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 664                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 665                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 666 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_8  |  \
 667                               PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
 668                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 669
 670 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 671                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 672                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 673 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
 674                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 675                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 676
 677 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 678                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 679                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 680 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 681                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 682                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 683
 684 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 685                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 686                               PLL_MALDIV_1 | PLL_PCIDIV_2)
 687 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 688                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 689                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 690
 691 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
 692
 693 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
 694 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 695                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 696                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 697 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_4  |  \
 698                                   PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 699                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 700
 701 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 702                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 703                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 704 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 705                                   PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 706                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 707
 708 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 709                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 710                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 711 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 712                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 713                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 714
 715 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 716                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 717                                   PLL_MALDIV_1 | PLL_PCIDIV_2)
 718 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 719                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 720                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 721
 722 #else
 723 #error "* External frequency (SysClk) not defined! *"
 724 #endif
 725
 726 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 727 /* Model HI */
 728 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_333_111_37_55_55
 729 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_333_111_37_55_55
 730 #define CONFIG_SYS_OPB_FREQ     55555555
 731 /* Model ME */
 732 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 733 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_266_133_33_66_33
 734 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_266_133_33_66_33
 735 #define CONFIG_SYS_OPB_FREQ     66666666
 736 #else
 737 /* Model BA (default) */
 738 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_133_133_33_66_33
 739 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_133_133_33_66_33
 740 #define CONFIG_SYS_OPB_FREQ     66666666
 741 #endif
 742
 743 #endif /* CONFIG_NO_SERIAL_EEPROM */
 744
 745 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 746 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
 747
 748 /*
 749  * JFFS2 partitions
 750  */
 751
 752 /* No command line, one static partition */
 753 #undef CONFIG_CMD_MTDPARTS
 754 #define CONFIG_JFFS2_DEV                "nand0"
 755 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 756 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 757
 758 /* mtdparts command line support */
 759 /*
 760 #define CONFIG_CMD_MTDPARTS
 761 #define MTDIDS_DEFAULT          "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
 762 */
 763
 764 /* 256 kB U-boot image */
 765 /*
 766 #define MTDPARTS_DEFAULT        "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
 767                                         "1792k(user),256k(u-boot);" \
 768                                 "ppchameleonevb-nand:-(nand)"
 769 */
 770
 771 /* 320 kB U-boot image */
 772 /*
 773 #define MTDPARTS_DEFAULT        "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
 774                                         "1728k(user),320k(u-boot);" \
 775                                 "ppchameleonevb-nand:-(nand)"
 776 */
 777
 778 #endif  /* __CONFIG_H */