2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * pm854 board configuration file
28 * Please refer to doc/README.mpc85xx for more info.
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_MPC8540 1 /* MPC8540 specific */
42 #define CONFIG_PM854 1 /* PM854 board specific */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
53 * Two valid values are:
57 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
58 * is likely the desired value here, so that is now the default.
59 * The board, however, can run at 66MHz. In any event, this value
60 * must match the settings of some switches. Details can be found
61 * in the README.mpc85xxads.
64 #ifndef CONFIG_SYS_CLK_FREQ
65 #define CONFIG_SYS_CLK_FREQ 66000000
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_L2_CACHE /* toggle L2 cache */
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
77 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
79 #define CONFIG_SYS_MEMTEST_END 0x00400000
83 * Base addresses -- Note these are effective addresses where the
84 * actual resources get mapped (not physical addresses)
86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
87 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
89 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
93 #define CONFIG_FSL_DDR1
94 #undef CONFIG_FSL_DDR_INTERACTIVE
95 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
97 #define CONFIG_DDR_DLL /* possible DLL fix needed */
98 #define CONFIG_DDR_ECC /* only for ECC DDR module */
100 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104 #define CONFIG_VERY_BIG_RAM
106 #define CONFIG_NUM_DDR_CONTROLLERS 1
107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
108 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
110 /* I2C addresses of SPD EEPROMs */
111 #define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
113 /* Manually set up DDR parameters */
114 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */
115 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
116 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
117 #define CONFIG_SYS_DDR_TIMING_1 0x47444321
118 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
119 #define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
120 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
121 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
124 * SDRAM on the Local Bus
126 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
127 #define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
129 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */
130 #define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
132 #define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */
133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
135 #undef CONFIG_SYS_FLASH_CHECKSUM
136 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
139 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
142 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
143 #define CONFIG_SYS_RAMBOOT
145 #undef CONFIG_SYS_RAMBOOT
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_EMPTY_INFO
152 #undef CONFIG_CLOCKS_IN_MHZ
155 * Local Bus Definitions
157 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
158 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
159 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
160 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
163 #define CONFIG_SYS_INIT_RAM_LOCK 1
164 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
165 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
167 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
168 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
169 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
171 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
172 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
175 #define CONFIG_CONS_INDEX 1
176 #undef CONFIG_SERIAL_SOFTWARE_FIFO
177 #define CONFIG_SYS_NS16550
178 #define CONFIG_SYS_NS16550_SERIAL
179 #define CONFIG_SYS_NS16550_REG_SIZE 1
180 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
182 #define CONFIG_SYS_BAUDRATE_TABLE \
183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
188 /* Use the HUSH parser */
189 #define CONFIG_SYS_HUSH_PARSER
190 #ifdef CONFIG_SYS_HUSH_PARSER
191 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
197 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
198 #define CONFIG_HARD_I2C /* I2C with hardware support*/
199 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
200 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
201 #define CONFIG_SYS_I2C_SLAVE 0x7F
202 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
203 #define CONFIG_SYS_I2C_OFFSET 0x3000
206 * EEPROM configuration
208 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
210 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
216 #define CONFIG_RTC_PCF8563
217 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
220 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
221 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
222 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
226 * Addresses are mapped 1-1.
228 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
229 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
230 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
231 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
232 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
233 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
235 #if defined(CONFIG_PCI)
237 #define CONFIG_NET_MULTI
238 #define CONFIG_PCI_PNP /* do pci plug-and-play */
240 #define CONFIG_EEPRO100
244 #if !defined(CONFIG_PCI_PNP)
245 #define PCI_ENET0_IOADDR 0xe0000000
246 #define PCI_ENET0_MEMADDR 0xe0000000
247 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
250 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
253 #endif /* CONFIG_PCI */
256 #if defined(CONFIG_TSEC_ENET)
258 #ifndef CONFIG_NET_MULTI
259 #define CONFIG_NET_MULTI 1
262 #define CONFIG_MII 1 /* MII PHY management */
263 #define CONFIG_TSEC1 1
264 #define CONFIG_TSEC1_NAME "TSEC0"
265 #define CONFIG_TSEC2 1
266 #define CONFIG_TSEC2_NAME "TSEC1"
267 #define TSEC1_PHY_ADDR 0
268 #define TSEC2_PHY_ADDR 1
269 #define TSEC1_PHYIDX 0
270 #define TSEC2_PHYIDX 0
271 #define TSEC1_FLAGS TSEC_GIGABIT
272 #define TSEC2_FLAGS TSEC_GIGABIT
274 #define CONFIG_MPC85XX_FEC 1
275 #define CONFIG_MPC85XX_FEC_NAME "FEC"
276 #define FEC_PHY_ADDR 3
280 /* Options are: TSEC[0-1] */
281 #define CONFIG_ETHPRIME "TSEC0"
283 #define CONFIG_HAS_ETH0
284 #define CONFIG_HAS_ETH1 1
285 #define CONFIG_HAS_ETH2 1
287 #endif /* CONFIG_TSEC_ENET */
293 #ifndef CONFIG_SYS_RAMBOOT
294 #define CONFIG_ENV_IS_IN_FLASH 1
295 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000)
296 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
297 #define CONFIG_ENV_SIZE 0x2000
299 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
300 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
301 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
302 #define CONFIG_ENV_SIZE 0x2000
305 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
306 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
312 #define CONFIG_BOOTP_BOOTFILESIZE
313 #define CONFIG_BOOTP_BOOTPATH
314 #define CONFIG_BOOTP_GATEWAY
315 #define CONFIG_BOOTP_HOSTNAME
319 * Command line configuration.
321 #include <config_cmd_default.h>
323 #define CONFIG_CMD_PING
324 #define CONFIG_CMD_I2C
325 #define CONFIG_CMD_MII
326 #define CONFIG_CMD_DATE
327 #define CONFIG_CMD_EEPROM
329 #if defined(CONFIG_PCI)
330 #define CONFIG_CMD_PCI
333 #if defined(CONFIG_SYS_RAMBOOT)
334 #undef CONFIG_CMD_SAVEENV
335 #undef CONFIG_CMD_LOADS
339 #undef CONFIG_WATCHDOG /* watchdog disabled */
342 * Miscellaneous configurable options
344 #define CONFIG_SYS_LONGHELP /* undef to save memory */
345 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
346 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348 #if defined(CONFIG_CMD_KGDB)
349 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
351 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
354 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
355 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
356 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
357 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
361 * For booting Linux, the board info and command line data
362 * have to be in the first 8 MB of memory, since this is
363 * the maximum mapped by the Linux kernel during initialization.
365 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
368 * Internal Definitions
372 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
373 #define BOOTFLAG_WARM 0x02 /* Software reboot */
375 #if defined(CONFIG_CMD_KGDB)
376 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
377 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
382 * Environment Configuration
385 /* The mac addresses for all ethernet interface */
386 #if defined(CONFIG_TSEC_ENET)
387 #define CONFIG_ETHADDR 00:40:42:01:00:00
388 #define CONFIG_ETH1ADDR 00:40:42:01:00:01
389 #define CONFIG_ETH2ADDR 00:40:42:01:00:02
393 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
394 #define CONFIG_BOOTFILE pm854/uImage
396 #define CONFIG_HOSTNAME pm854
397 #define CONFIG_IPADDR 192.168.0.103
398 #define CONFIG_SERVERIP 192.168.0.64
399 #define CONFIG_GATEWAYIP 192.168.0.1
400 #define CONFIG_NETMASK 255.255.255.0
402 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
404 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
405 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
407 #define CONFIG_BAUDRATE 9600
409 #define CONFIG_EXTRA_ENV_SETTINGS \
411 "consoledev=ttyS0\0" \
412 "ramdiskaddr=400000\0" \
413 "ramdiskfile=pm854/uRamdisk\0"
415 #define CONFIG_NFSBOOTCOMMAND \
416 "setenv bootargs root=/dev/nfs rw " \
417 "nfsroot=$serverip:$rootpath " \
418 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
419 "console=$consoledev,$baudrate $othbootargs;" \
420 "tftp $loadaddr $bootfile;" \
423 #define CONFIG_RAMBOOTCOMMAND \
424 "setenv bootargs root=/dev/ram rw " \
425 "console=$consoledev,$baudrate $othbootargs;" \
426 "tftp $ramdiskaddr $ramdiskfile;" \
427 "tftp $loadaddr $bootfile;" \
428 "bootm $loadaddr $ramdiskaddr"
430 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
432 #endif /* __CONFIG_H */