2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5200
33 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
34 #define CONFIG_PM520 1 /* ... on PM520 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
42 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
43 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
47 * Serial console configuration
49 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
50 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
51 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
54 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
57 * 0x40000000 - 0x4fffffff - PCI Memory
58 * 0x50000000 - 0x50ffffff - PCI IO Space
61 #define CONFIG_PCI_PNP 1
62 #define CONFIG_PCI_SCAN_SHOW 1
64 #define CONFIG_PCI_MEM_BUS 0x40000000
65 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
66 #define CONFIG_PCI_MEM_SIZE 0x10000000
68 #define CONFIG_PCI_IO_BUS 0x50000000
69 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
70 #define CONFIG_PCI_IO_SIZE 0x01000000
72 #define CONFIG_NET_MULTI 1
73 #define CONFIG_EEPRO100 1
74 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
77 #define ADD_PCI_CMD CFG_CMD_PCI
81 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
88 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
89 CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_DATE)
91 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
92 #include <cmd_confdefs.h>
97 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
98 #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
99 #define CONFIG_BOOTARGS "root=/dev/ram rw"
101 #if defined(CONFIG_MPC5200)
103 * IPB Bus clocking configuration.
105 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
110 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
111 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
113 #define CFG_I2C_SPEED 100000 /* 100 kHz */
114 #define CFG_I2C_SLAVE 0x7F
117 * EEPROM configuration
119 #define CFG_I2C_EEPROM_ADDR 0x58
120 #define CFG_I2C_EEPROM_ADDR_LEN 1
121 #define CFG_EEPROM_PAGE_WRITE_BITS 4
122 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
127 #define CONFIG_RTC_PCF8563
128 #define CFG_I2C_RTC_ADDR 0x51
131 * Flash configuration
133 #define CFG_FLASH_BASE 0xff800000
134 #define CFG_FLASH_SIZE 0x00800000
135 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
136 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
138 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
140 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
141 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
142 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
143 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
144 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
146 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
148 #undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
152 * Environment settings
154 #define CFG_ENV_IS_IN_FLASH 1
155 #define CFG_ENV_SIZE 0x10000
156 #define CFG_ENV_SECT_SIZE 0x40000
157 #define CONFIG_ENV_OVERWRITE 1
162 #define CFG_MBAR 0xf0000000
163 #define CFG_SDRAM_BASE 0x00000000
164 #define CFG_DEFAULT_MBAR 0x80000000
166 /* Use SRAM until RAM will be available */
167 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
168 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
171 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
172 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175 #define CFG_MONITOR_BASE TEXT_BASE
176 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
177 # define CFG_RAMBOOT 1
180 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
181 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
182 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
185 * Ethernet configuration
187 #define CONFIG_MPC5xxx_FEC 1
189 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
191 /* #define CONFIG_FEC_10MBIT 1 */
192 #define CONFIG_PHY_ADDR 0x00
197 #define CFG_GPS_PORT_CONFIG 0x10000004
200 * Miscellaneous configurable options
202 #define CFG_LONGHELP /* undef to save memory */
203 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
204 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
205 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
207 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
209 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
210 #define CFG_MAXARGS 16 /* max number of command args */
211 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
213 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
214 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
216 #define CFG_LOAD_ADDR 0x100000 /* default load address */
218 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
221 * Various low-level settings
223 #if defined(CONFIG_MPC5200)
224 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
225 #define CFG_HID0_FINAL HID0_ICE
227 #define CFG_HID0_INIT 0
228 #define CFG_HID0_FINAL 0
231 #define CFG_BOOTCS_START CFG_FLASH_BASE
232 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
233 #define CFG_BOOTCS_CFG 0x0004fb00
234 #define CFG_CS0_START CFG_FLASH_BASE
235 #define CFG_CS0_SIZE CFG_FLASH_SIZE
237 #define CFG_CS_BURST 0x00000000
238 #define CFG_CS_DEADCYCLE 0x33333333
240 #define CFG_RESET_ADDRESS 0xff000000
242 #endif /* __CONFIG_H */