3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 /***********************************************************
16 * High Level Configuration Options
18 ***********************************************************/
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20 #define CONFIG_PIP405 1 /* ...on a PIP405 board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
24 /***********************************************************
26 ***********************************************************/
27 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
32 #define CONFIG_BOOTP_BOOTFILESIZE
33 #define CONFIG_BOOTP_BOOTPATH
34 #define CONFIG_BOOTP_GATEWAY
35 #define CONFIG_BOOTP_HOSTNAME
38 * Command line configuration.
40 #define CONFIG_CMD_PCI
41 #define CONFIG_CMD_IRQ
42 #define CONFIG_CMD_REGINFO
44 #define CONFIG_CMD_SDRAM
45 #define CONFIG_CMD_SAVES
47 /**************************************************************
49 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
51 * Caution: on the same bus is the SPD (Serial Presens Detect
53 * The Atmel EEPROM uses 16Bit addressing.
54 ***************************************************************/
55 #define CONFIG_SYS_I2C
56 #define CONFIG_SYS_I2C_PPC4XX
57 #define CONFIG_SYS_I2C_PPC4XX_CH0
58 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
59 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
61 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
62 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
63 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
64 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
65 #define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
67 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
68 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
69 /* 64 byte page write mode using*/
70 /* last 6 bits of the address */
71 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
73 /***************************************************************
74 * Definitions for Serial Presence Detect EEPROM address
75 * (to get SDRAM settings)
76 ***************************************************************/
77 #define SPD_EEPROM_ADDRESS 0x50
79 #define CONFIG_BOARD_EARLY_INIT_R
81 /**************************************************************
82 * Environment definitions
83 **************************************************************/
85 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
86 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
88 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
89 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
91 #define CONFIG_IPADDR 10.0.0.100
92 #define CONFIG_SERVERIP 10.0.0.1
93 #define CONFIG_PREBOOT
94 /***************************************************************
95 * defines if an overwrite_console function exists
96 *************************************************************/
97 /***************************************************************
98 * defines if the overwrite_console should be stored in the
100 **************************************************************/
102 /**************************************************************
104 *************************************************************/
105 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
106 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
108 #define CONFIG_MISC_INIT_R
109 /***********************************************************
110 * Miscellaneous configurable options
111 **********************************************************/
112 #define CONFIG_SYS_LONGHELP /* undef to save memory */
113 #if defined(CONFIG_CMD_KGDB)
114 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
116 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
122 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
123 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
125 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
126 #define CONFIG_SYS_NS16550_SERIAL
127 #define CONFIG_SYS_NS16550_REG_SIZE 1
128 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
130 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
131 #define CONFIG_SYS_BASE_BAUD 691200
133 /* The following table includes the supported baudrates */
134 #define CONFIG_SYS_BAUDRATE_TABLE \
135 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
136 57600, 115200, 230400, 460800, 921600 }
138 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
139 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
141 /*-----------------------------------------------------------------------
143 *-----------------------------------------------------------------------
145 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
146 #define PCI_HOST_FORCE 1 /* configure as pci host */
147 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
149 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
150 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
151 /* resource configuration */
152 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
153 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
154 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
155 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
156 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
157 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
158 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
159 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
161 /*-----------------------------------------------------------------------
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
166 #define CONFIG_SYS_SDRAM_BASE 0x00000000
167 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
169 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
170 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
173 * For booting Linux, the board info and command line data
174 * have to be in the first 8 MB of memory, since this is
175 * the maximum mapped by the Linux kernel during initialization.
177 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
178 /*-----------------------------------------------------------------------
181 #define CONFIG_SYS_UPDATE_FLASH_SIZE
182 #define CONFIG_SYS_FLASH_PROTECTION
183 #define CONFIG_SYS_FLASH_EMPTY_INFO
185 #define CONFIG_SYS_FLASH_CFI
186 #define CONFIG_FLASH_CFI_DRIVER
188 #define CONFIG_FLASH_SHOW_PROGRESS 45
190 #define CONFIG_SYS_MAX_FLASH_BANKS 1
191 #define CONFIG_SYS_MAX_FLASH_SECT 256
194 * Init Memory Controller:
196 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
197 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
198 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
199 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
201 /* Configuration Port location */
202 #define CONFIG_PORT_ADDR 0xF4000000
203 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
205 /*-----------------------------------------------------------------------
206 * Definitions for initial stack pointer and data area (in On Chip SRAM)
208 #define CONFIG_SYS_TEMP_STACK_OCM 1
209 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
210 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
211 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
212 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
213 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
214 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
216 /***********************************************************************
217 * External peripheral base address
218 ***********************************************************************/
219 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
221 /***********************************************************************
223 ***********************************************************************/
224 #define CONFIG_LAST_STAGE_INIT
225 /************************************************************
227 ***********************************************************/
228 #define CONFIG_PPC4xx_EMAC
229 #define CONFIG_MII 1 /* MII PHY management */
230 #define CONFIG_PHY_ADDR 1 /* PHY address */
231 /************************************************************
233 ***********************************************************/
234 #define CONFIG_RTC_MC146818
235 #undef CONFIG_WATCHDOG /* watchdog disabled */
237 /************************************************************
239 ************************************************************/
240 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
241 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
243 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
244 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
245 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
246 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
247 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
248 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
250 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
251 #undef CONFIG_IDE_LED /* no led for ide supported */
252 #define CONFIG_IDE_RESET /* reset for ide supported... */
253 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
254 #define CONFIG_SUPPORT_VFAT
256 /************************************************************
257 * ATAPI support (experimental)
258 ************************************************************/
259 #define CONFIG_ATAPI /* enable ATAPI Support */
261 /************************************************************
262 * SCSI support (experimental) only SYM53C8xx supported
263 ************************************************************/
264 #define CONFIG_SCSI_SYM53C8XX
265 #define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
266 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
267 #define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
268 #define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
270 /************************************************************
271 * Disk-On-Chip configuration
272 ************************************************************/
273 #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
274 #define CONFIG_SYS_DOC_SHORT_TIMEOUT
275 #define CONFIG_SYS_DOC_SUPPORT_2000
276 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
278 /************************************************************
279 * DISK Partition support
280 ************************************************************/
282 /************************************************************
284 ************************************************************/
285 #define CONFIG_VIDEO_LOGO
286 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
288 /************************************************************
290 ************************************************************/
291 #define CONFIG_USB_UHCI
293 /* Enable needed helper functions */
295 /************************************************************
297 ************************************************************/
298 #if defined(CONFIG_CMD_KGDB)
299 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
302 /************************************************************
303 * support BZIP2 compression
304 ************************************************************/
305 #define CONFIG_BZIP2 1
307 #endif /* __CONFIG_H */